Configurable Logic Research Articles

Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management.

The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4 configurable logic blocks (CLBs) to accommodate the RO bank.

Advancing Molecular-Scale Logic Devices through Multistage Switching in a Luminescent Bimetallic Ru(II)-Terpyridine Complex.

Stimuli-responsive multistep switching phenomena of a luminescent bimetallic Ru(II) complex are employed herein to fabricate multiple configurable logic devices. The complex exhibits "off-on" and "on-off" emission switching upon alternative treatment with visible and UV light. Additionally, remarkable augmentation of the rate as well as quantum yield of photoisomerization was achieved via the use of a chemical oxidant (Ce4+) as well as a reductant (metallic sodium). Upon exploiting the emission spectral response of the complex, several advanced Boolean logic functions, including IMPLICATION as well as 2-input 2-output and 3-input 2-output complex combinational logic gates, are successfully implemented. Additionally, by utilizing the vast efficacy of Python, a novel "logic_circuit" model is devised that is capable of making accurate decisions under the influence of various input combinations. This model transcends traditional Boolean logic gates, offering flexibility and intuition to design logical functions tailored to specific chemical contexts. By integrating principles of logic circuits with chemical processes, this innovative approach enables structure determination of the chemical states based on input conditions, thereby unlocking avenues for exploring intricate interactions and reactions beyond conventional Boolean logic paradigms.

Toward a more complete understanding of institutional logic configuration in an merger project

AbstractThe frequency and scale of mergers and acquisitions (M&A) have significantly increased in the last two decades, in spite of continuous reports on their high failure rates. M&A scholars call for insights to be sought on the merger process to help understand the complexity of these operations and decrease their failure rate. M&A scholars advocate paying attention to institutional logics' configuration shaping a firm's decisions to grasp merger process complexity. Institutional studies show how specific logics have a powerful influence on the strategic decisions and priorities of organizations. Yet, few studies have empirically combined multiple levels by framing logics' configuration fostering specific strategic decisions. This study addresses this issue. Using a longitudinal case study, we analyze how institutional logics' configuration at organizational and inter‐organizational levels supports firms' strategic decisions to merge and to end the deal. We demonstrate that despite the alignment of logics at the organizational level, the multiplicity of logics at the inter‐organizational level led to deal failure.

Evaluation of Traffic Efficiency and Energy-Saving Benefits of L3 Smart Vehicles under the Urban Expressway Scenario

An L3 smart vehicle (L3 SV) could behave differently from human-driven vehicles due to its intelligent configuration and decision-making logic, and may consequently exert influences on traffic flow. In order to clarify the L3 SV’s traffic impacts and accelerate L3 SV implementation, this paper conducted an evaluation on the traffic efficiency and energy consumption influences of L3 SVs based on a microscopic traffic simulation. Taking Beijing as a case, the relevant traffic economic benefits were calculated with the help of the previously proposed traffic economic benefits model. Before modeling L3 SVs, a two-dimensional general modeling architecture for SVs was proposed. According to the architecture, the driving behavior model, as well as behavior selection models of L3 SVs, was eventually determined, based on which the intelligent driving model of L3 SVs was established. Urban expressways were selected as the simulation road type, and scenario analysis was conducted on various proportions of L3 SVs and L3 connected and autonomous vehicles (L3 CAVs), as well as the input traffic flow rates. It was found that L3 SVs can significantly reduce the travel time and energy consumption and enlarge the actual road capacity. The improvement will become particularly prominent under saturated or supersaturated traffic flow and increasing the proportion of L3 SVs and L3 CAVs can also amplify the effect of traffic optimization. The related economic benefit is considerable, which is CNY 3.104 billion a year based on Beijing’s travel and traffic conditions.

Erasable and Field Programmable DNA Circuits Based on Configurable Logic Blocks.

DNA is commonly employed as a substrate for the building of artificial logic networks due to its excellent biocompatibility and programmability. Till now, DNA logic circuits are rapidly evolving to accomplish advanced operations. Nonetheless, nowadays, most DNA circuits remain to be disposable and lack of field programmability and thereby limits their practicability. Herein, inspired by the Configurable Logic Block (CLB), the CLB-based erasable field-programmable DNA circuit that uses clip strands as its operation-controlling signals is presented. It enables users to realize diverse functions with limited hardware. CLB-based basic logic gates (OR and AND) are first constructed and demonstrated their erasability and field programmability. Furthermore, by adding the appropriate operation-controlling strands, multiple rounds of programming are achieved among five different logic operations on a two-layer circuit. Subsequently, a circuit is successfully built to implement two fundamental binary calculators: half-adder and half-subtractor, proving that the design can imitate silicon-based binary circuits. Finally, a comprehensive CLB-based circuit is built that enables multiple rounds of switch among seven different logic operations including half-adding and half-subtracting. Overall, the CLB-based erasable field-programmable circuit immensely enhances their practicability. It is believed that design can be widely used in DNA logic networks due to its efficiency and convenience.

Real-Time Hardware Emulation of Microgrid Forming Wireless Power Transfer Systems

The prevalence of wireless charging approaches has manifested a grid-supporting potential which can be evaluated by hardware-based methodologies. In this work, real-time emulation of a bidirectional wireless power transfer (WPT) system capable of DC microgrid formation is investigated on the field-programmable gate array (FPGA). Following a detailed analysis of the transfer characteristics of the dual-active bridge with a series-compensated resonant tank in between, a unified control scheme utilizing a phase-shift strategy is proposed for a flexible voltage or current regulation, thereby enabling the DC microgrid-forming capability. Electromagnetic transient modeling is then carried out so that an accurate digital emulation platform is feasible for prototyping. The fact that the WPT has a high frequency compels a small computation step size, which poses a dramatic challenge to real-time execution. A partition-iteration approach is therefore proposed for matrix dimension reduction which ultimately results in an alleviated processing burden. In the meantime, the parallelism of configurable logic blocks and the pipelined architecture of the FPGA are explored to achieve a low hardware latency. The analytical models, as well as the proposed control method, are validated experimentally, and then real-time hardware emulation of a DC microgrid consisting of WPT systems is performed for an integration study.

Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications

Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is at 40 MHz, which is 92.94% energy reduction compared to its CMOS counterpart. Further, the three proposed adiabatic-logic-based memory cells are 14T, 16T, and 12T designs with at least 88.2%, 84.2%, and 87.2% energy savings. Also, we evaluated the performance of the proposed CLBs using an adiabatic-logic-based LUT (AL-LUT) interfacing with adiabatic-logic-based memory cells. The proposed design shows significant energy reduction compared to a CMOS LUT interface with SRAM cells for different frequencies; the energy savings are at least 91.6% for AL-LUT 14T, 89.7% for AL-LUT 16T, and 91.3% AL-LUT 12T.

Implementation of EnDat Interface Master Using Configurable Logic Block in MCU

In this study, we propose an implementation method of the Encoder Data (EnDat) interface master for slave encoders using only a configurable logic block (CLB) and a serial peripheral interface (SPI) integrated into microcontroller units. By programming the CLB device to execute logic functions and finite state machines designed for the EnDat interface master operation, we realize the EnDat and SPI clocks that are required for the EnDat interface master operation. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are unnecessary for the master implementation. We build a one-axis feed drive system that is powered by an AC motor and equipped with an EnDat linear encoder for measuring table speed and position. By performing various experiments for table position and speed control based on the built feed drive system, we verify the performance and practical usefulness of the implemented EnDat interface master. The maximum EnDat clock frequency without the propagation delay compensation is achieved by 2 MHz, which can cope with 16 kHz control cycle frequency. The usefulness is demonstrated by showing the table speed and position control performance that are acceptable in real applications.

Approaches to Extend FPGA Reverse-Engineering Technology from ISE to Vivado

SRAM-based FPGA(Field Programmable Logic Arrays) requires external memory since its internal memory gets erased when power is cut off. The process of transmitting the circuit netlist in bitstream from external memory during power-up in FPGA is vulnerable to malicious attacks such as bitstream theft and tampering. Previous FPGA reverse-engineering methods focus on FPGAs, supported by ISE (ISE Design Suite). This is because ISE provides XDLRC (Xilinx Design Language Routing Configurable logic) and XDL (Xilinx Design language) files, which are essential for reverse engineering. However, Vivado Design Suite (Vivado) does not offer those files, making it impossible to extend the coverage of reverse engineering to the FPGAs supported by Vivado. In this paper, we propose a method to generate XDLRC and XDL through Vivado. According to experimental results, the XDLRC and XDL generated through Vivado, respectively, match 99% and 75% with those generated in ISE for Artix-7 100T. As a result, this paper has expanded the scope of reverse engineering from being mainly focused on ISE to now also include Vivado. It is important to note that this paper does not encourage bitstream attacks through reverse engineering but rather highlights the risk associated with malicious attacks and emphasizes the importance of security.

Sustainable Innovation in the Biopharmaceutical Industry: An Analysis of the Impact of Policy Configuration

To achieve sustainable development, it is necessary to consider the business model adjustment of the industry in advance, from the development stage to the mature stage. In China, strategic emerging industries are industries that achieve technological breakthroughs, but such industries often have the characteristics of high investment, high technology, high risk, high returns, and long research and development times. This type of industry relies heavily on national resource support from the exploration period to the development period, but its high-profit characteristics also attract policy bias from the governments of other countries internationally. Therefore, understanding the resource requirements of such industries in different periods in advance will help the government to adjust resource allocation and strategic layout through policy means. This will facilitate the smooth transition of the entire industry from the development period to the mature period, and achieve its overall sustainable development. To assist the government in achieving reasonable predictions for policy adjustments, this study focuses on the biopharmaceutical industry, which is one of the representatives of the strategic emerging industries in China’s Yangtze River Delta. Considering that policies are not used in a single manner, and that the observation period needs to span the development and platform periods of the industry, the traditional Qualitative Comparative Analysis method (QCA) does not consider the analysis of data from multiple periods. Therefore, this study innovatively uses the Multi-Time Qualitative Comparative Analysis method (mtQCA), adding the dimension of time change and exploring the policy configuration logic behind the differences in local industrial innovation performance. Extracting general rules from specific policy configuration patterns is meaningful for a better analysis and resolution of complex, dynamic management issues, which will promote the sustainable development of strategic emerging industries.

Development of PLC-Based Hardware Test-Bench Prototype for Solar-Wind-Battery-Based Microgrid System’s Control Algorithm Validation

Programmable Logic Controllers (PLCs) are gaining traction in microgrid operation due to their real-time deployment, reliable and robust operation, and fast response, even in harsh environments. Recognizing the critical need for robust and reconfigurable microgrid control and operation, this research proposes a hardware test-bench prototype using the Reconfigurable Allen-Bradley—Micro820/2080-LC20-20QBB PLC to demonstrate control algorithms aiming for efficient control, energy management, and resilient microgrid automation. The design and construction of a prototype controller test bench, along with the PLC configuration, wiring diagrams, and control logic, constitute the significant contributions of this research. The proposed controller test bench’s performance is evaluated through similar condition simulations in the presence of disturbances induced by the reduced contributions of renewable energy sources, such as solar and wind. The results illustrate the effectiveness of the developed control algorithm implemented in the proposed controller, ensuring the stable operation of the microgrid. Consequently, this work advances the simulation-based validation of microgrid control algorithms and provides insights into the practical application of a PLC-based hardware test bench under various environmental conditions.

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

Marx’s Critical Theory of Slavery

Abstract Marx’s critical theory of slavery is the operational subtext throughout his critique of political economy. For Marx, the movement from modern slavery to capital represents a historical transition of significance, not only (or foremost) as an empirical transition but also as a transformation of social substance. Marx reveals why, in retrospect, production based on slavery, as logical configuration, must give way to the generalising logic of wage labour. Marx’s critical theory of slavery historicises wage labour (qua category) as the dissolution and inversion of enslaved labour (qua category). Plantation slavery production in the colonised territories initiates a qualitative development that constitutes the historical condition for the emergence of a mode of sociality that we can call ‘value’. Marx’s theoretical account of modern slavery is a lever in his broader critique of capital and is fundamentally distinct from empirical, historical accounts.

A novel low hardware configurable ring oscillator (CRO) PUF for lightweight security applications

Physical unclonable function (PUF) is a promising hardware security primitive that can generate a unique secret key peculiar to each chip by extracting the differences of non-reproducible manufacturing variations for the same implementations. Although there are several types of PUF designs and structures, ring oscillator (RO) PUF is one of the most prominent PUFs due to its straightforward implementation and remarkable performance. However, the traditional RO-PUF does not support large sizes of input/output combinations or challenge-response pairs (CRPs), as it is called in the scope of PUFs. Consequently, RO-PUF is more vulnerable to adversary attacks which can reveal the PUFs’ CRPs using a machine learning approach. Increasing the size of RO-PUF's CRPs requires a high increase in the circuit size leading to unacceptable area overhead for lightweight applications. The primary technique used to increase RO-PUF CRPs’ size without increasing the size of the required hardware is to develop a configurable ring oscillator (CRO) PUF. In this paper, we propose a configurable logic unit (CLU) that can be utilized to build a low-hardware CRO-PUF. The proposed CLU consists of a 1-XOR gate and a 1-XNOR gate. Building a CRO-PUF using the proposed CLU dramatically increases the CRPs size while minimizing the required hardware. The proposed CRO-PUF achieves excellent evaluation results, with measured uniqueness of 50.1 %, uniformity of 49.45 %, and reliability of 98.33 %. These values are in close proximity to the ideal targets of 50 % for uniqueness and uniformity, and 100 % for reliability

The fabrication of fluorescent sensor for Fe3+ detection and configurable logic gate operation based on N-doped carbon dots

Herein, fluorescent N-doped carbon dots (N-CDs) were obtained using hydrothermal treatment of polyethyleneimine and melamine. The N-CDs exhibit nanoscale structure, good water solubility, photostability and excellent fluorescence property with a high fluorescence quantum yield of 26 %. The as-prepared N-CDs were selected for the detection of Fe3+ with a fluorescence “OFF-ON” strategy by the mechanism of internal filtration effect (IFE). A good linear relationship can be observed for the concentration of Fe3+ from 0 to 500 μM, and the calculated detection limit (LOD) for Fe3+ was 0.88 μM (3σ/slope). Meanwhile, the N-CDs based sensor can be utilized for tracing Fe3+ in real water samples. In addition, the quenched fluorescence can be recovered with the treatment of l-cysteine, and thus can be designed for quantitative determination of l-cysteine with a fluorescent “ON-OFF-ON” switch. Moreover, a set of resettable, multireadout logic gate operations including OR and AND have been realized for the N-CDs.

A configurational approach to political risks and institutional logics

Advancing our understanding of political risks is crucial for international management (IM) research and practice. This study addresses how multiple institutional logics that govern multinational enterprises (MNEs), as latent tensions of political risks, may work together for superior or inferior performance. Methodologically, we adopt a configurational approach to predict how varying state logic and market logic combinations affect performance in the context of internationalization among Chinese financial services firms. Employing fuzzy-set Qualitative Comparative Analysis (fsQCA), we identify a specific taxonomy of four political risk prototypes that lead to different performance outcomes. Overall, this study provides novel insights into political risk variations of internationalizing firms and links different institutional logic configurations with performance outcomes.

Optimization of a Mealy Automaton Circuit in a Mixed Element Basis

Introduction. The control device is one of the most important blocks of any digital system. The main function of the control device is to coordinate the interaction of the remaining units of the system. Therefore, the characteristics of the control device circuit have a significant impact on the quality of the overall system. To represent the law of functioning of the control device, the models of the microprogrammed automaton (MPA) by Moore and Mealy are used. When synthesizing MPA circuits, it is necessary to solve a number of optimization problems: reducing hardware costs, increasing performance, minimizing power consumption, and jointly optimizing hardware-time characteristics. Methods for solving these problems largely depend on the elemental basis used. Currently, one of the main bases in which modern digital systems are implemented is the FPGA. The main blocks in the FPGA are configurable logic blocks, a programmable interconnect matrix, a timing tree, and programmable inputs and outputs. To implement MPA schemes, two types of configurable logic blocks can be used: tabular logic elements (TLE) and built-in memory blocks (VBP), which have the property of reconfiguration. However, VBPs are widely used to implement various operating blocks of digital systems. Therefore, the controller circuit designer can use a limited number of such memory blocks. Purpose of the article. The article deals with the issues of MPA synthesis when there are a limited number of "free" blocks of EBP. In this case, the microprogram automaton circuit is represented by a network consisting of VBP and TLE blocks. A method for the synthesis of a microprogram automaton with optimization of the number of TLEs is proposed when only one VBP can be used in the microprogram automaton circuit. The proposed method is based on the use of a built-in memory block that performs the replacement of input variables and the coding of the automaton outputs. Results. Studies of the effectiveness of the proposed method were carried out on standard machines. FPGAs of the Virtex-7 family from Xilinx were used as the elemental basis. To implement the proposed MPA, the Vivado package was used. The results of the research showed that the use of the VBP block made it possible to reduce the number of SLE blocks by an average of 14 % – 18 % compared to schemes consisting only of SLE. For the Virtex-7 family FPGA, the number of TLE inputs Io= 6 was sufficient for a single-level implementation of the output system. Conclusions. The effectiveness of the proposed method makes it possible to recommend it for use in the synthesis of microprogram automata under conditions of an extremely limited number of BVPs. Keywords: Mealy automaton, synthesis, coding of inputs, coding of sets of outputs.

Micro- and Nanocircuits with Configurable Logic

The work considers controversial problems with the introduction of specialized and at the same time universal large integrated circuits, which are clarified at the initial stages of automated hierarchical design. Universal micro- and nanocircuits with configurable logic are created in the article to increase the efficiency of automated design systems. The article provides effective methods of programming multiplexer micro- and nanocircuits with configured logic for implementing Boolean and majority logic functions. The obtained results are used to configure the multiplexer functional blocks. With the help of modern automated design systems, comparative modeling of logic micro- and nanocircuits with configured logic was performed, which proved the adequacy of their functioning, the advantages of frequency and disadvantages of temperature characteristics of nanomultiplexer circuits.

Enhancing Quality and Security of the PLL-TRNG

Field Programmable Gate Arrays (FPGAs) are used more and more frequently to implement cryptographic systems, which need random number generators (RNGs) to be embedded in the same device. The main challenge related to the implementation of a generator running inside FPGAs is that the physical source of randomness, such as jittered clock generator, is implemented in the configurable logic area, i.e. in the close vicinity of noisy running algorithms, which can have significant impact on generated numbers or even serve to attack the generator. A possible approach to prevent such influence is the use of Phase-Lock Loops (PLLs), which are separated from the re-configurable logic area inside the FPGA chip. In this paper, we propose a new architecture of the PLL-based TRNG including a method to avoid correlation in the output through control of timing in the sampling process, as well as new embedded tests based on the enhanced stochastic model. We also propose a workflow to help find the best parameters, such as output bitrate and entropy rate. We show that bitrates of around 400 kb/s or more can be achieved, while guaranteeing min-entropy rates per bit higher than 0.98 as required by the latest security standards.

A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design

Configuration circuitry is an essential component of a field-programmable gate array (FPGA) fabric, which enables the configuration of each programmable logic and takes over 40% of the FPGA chip area. Following the recent trends of automated custom FPGA design, it is essential to study the impact on the area and power of the configuration circuitry. This study compares the performance of different configuration circuitries using a strictly automated and complete standard cell-based semi-custom design methodology. We leverage an open-source framework, OpenFPGA, and extended it to support two configuration protocols: shift-register-based configuration (SRC) and memory-bank-based configuration (MBC) circuitries and their variants. We proposed area optimization strategies to improve the physical implementation of each configuration circuitry. Our results show that compared with naive SRC implementation, the proposed optimization strategies minimize the area overhead by more than 30% and power dissipation during programming by 20%. Whereas compared with MBC implementation, the optimized SRC implementation requires approximately a similar area. However, considering the more practical implementation of MBC with the write-verify functionality with optimized SRC implementation, the MBC implementation requires an 11% higher area and 30% higher routing wirelength, but results in a 62% reduction in the power dissipation during programming.