Configurable Logic Research Articles

Infrastructure for component-based DDS application development

Enterprise distributed real-time and embedded (DRE) systems are increasingly being developed with the use of component-based software techniques. Unfortunately, commonly used component middleware platforms provide limited support for event-based publish/subscribe (pub/sub) mechanisms that meet both quality-of-service (QoS) and configurability requirements of DRE systems. On the other hand, although pub/sub technologies, such as OMG Data Distribution Service (DDS), support a wide range of QoS settings, the level of abstraction they provide make it hard to configure them due to the significant source-level configuration that must be hard-coded at compile time or tailored at run-time using proprietary, ad hoc configuration logic. Moreover, developers of applications using native pub/sub technologies must write large amounts of boilerplate "glue" code to support run-time configuration of QoS properties, which is tedious and error-prone. This paper describes a novel, generative approach that combines the strengths of QoS-enabled pub/sub middleware with component-based middleware technologies. In particular, this paper describes the design and implementation of DDS4CIAO which addresses a number of inherent and accidental complexities in the DDS4CCM standard. DDS4CIAO simplifies the development, deployment, and configuration of component-based DRE systems that leverage DDS's powerful QoS capabilities by provisioning DDS QoS policy settings and simplifying the development of DDS applications.

Reimagining Critical Theory

This paper discusses Critical Theory, a model of theorizing in the field of the political sociology of education. We argue for a reimagined Critical Theory to herald an empowering, liberatory education that fosters curiosity and critical thinking, and a means for successful bottom-up, top-down political engagement. We present arguments at a theoretical and meta-theoretical level, leaving empirical analysis to a future writing. We hold it impossible: to fully dissociate normative from the analytical in constructing scientific thought, thus showing the importance of the notion of a good society to guide varied intellectual explorations; to deny the political role of education; and to detach from historicity of thought and policy prescriptions emerging from such theorizing, as not all social constructions are equal in terms of logical configuration, methodological rigor, or solid empirical proof. What follows are snapshots of how we can reimagine the historical present, and how Critical Theory can impact the new theorizing of sociology of education.

Application Study on Complex Product Based DMU in Product Life Cycle

The design characteristic and effect of DMU (Digital Mock-Up) are simply introduced. According as the design characteristic of complex product, the request for DMU platform in product life cycle is analyzed, and function analysis of DMU platform is finished. The whole frame and logic configuration are illuminated based function analysis, the realization method of design validation and optimization, design cooperation, maintenance support are emphatically analyzed, and some applied examples of DMU are displayed. The future imperative studies for DMU are discussed based the developed work and existent problem.

SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs

Although triple modular redundancy (TMR) has been widely used to mitigate single event upsets (SEUs) in static random access memory-based field-programmable gate arrays (FPGAs), SEU-caused bridging faults between the triplicated modules do not guarantee the correctness of TMR designs under all SEUs. In this paper, we present a novel computer-aided design flow for redundancy-based applications on FPGAs in order to mitigate the impact of SEUs in the configuration bitstreams. We introduce the notions of modular redundancy conflicts and vulnerability-gap conflicts which maintain the fundamental assumption underlying the integrity of redundancy-based designs (i.e., self-containment of SEU-induced faults within a single replica of redundant resources). When the impact of SEU-induced bridging faults is considered in high-level synthesis as well as physical synthesis, on average more than 30% improvement in the number of potential SEU-induced bridging faults can be reached as well as improvements in the performance and area utilization, compared to post-synthesis TMR, in which the voters are applied to the feedback structures in the circuit. Compared to the extreme case of post-synthesis TMR in which the voters are applied at the end of every configurable logic block, we reach 38% (26%) improvement in performance(area) of the implemented circuits.

Study and Implementation of MUX Based FPGA in QCA Technology

This paper presents a simple Multiplexer based Field programmable gate arrays with interconnects based on quantum cellular automata technology. Quantum cellular automata (QCA) technology is a promising nanotechnology of the future. QCA based 4:1 Multiplexer are designed and constructed as a module in a FPGA. Multiplexer based designs are used to implement complex Boolean functions and each module can act as a logic element or simple Multiplexer. We have studied here, NOR based logic to implement Sum function of an adder in a QCA FPGA. Finally we have designed and simulated the MUX based logic elements to construct QCA FPGA. This study can be useful for building complex Configurable logic blocks to design a complete FPGA.

A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA

Research efforts to develop a novel memory technology that combines the desired traits of nonvolatility, high endurance, high speed, and low power have resulted in the emergence of spin-torque transfer RAM (STTRAM) as a promising next-generation universal memory. Although industrial efforts have been made to design efficient embedded memory arrays using STTRAM, the prospect of developing a nonvolatile field-programmable gate array (FPGA) framework with STTRAM exploiting its high integration density remains largely unexplored. In this paper, we propose a novel CMOS-STTRAM hybrid FPGA framework, identify the key design challenges, and propose optimization techniques at circuit, architecture, and application mapping levels. We show that intrinsic properties of STTRAM that distinguish it from conventional static RAM (SRAM), such as asymmetric readout power, where a cell storing “0” has 5× less read power than a cell storing “1”, can be leveraged to skew lookup table contents for FPGA power reduction. We also argue that the proposed framework should operate on static voltage-sensing-based logic evaluation. We identify static power dissipation during logic evaluation and read noise margin as key design concerns and present an optimized resistor-divider design for voltage sensing to reduce static power and noise margin. Finally, we investigate the effectiveness of Shannon-decomposition-based supply gating to reduce static power. Simulation results show improvement of 44.39% in logic area and 22.28% in delay of a configurable logic block (CLB) and average improvement of 16.1% dynamic power over a conventional CMOS FPGA design for a set of benchmark circuits.

A declarative language approach to device configuration

C remains the language of choice for hardware programming (device drivers, bus configuration, etc.): it is fast, allows low-level access, and is trusted by OS developers. However, the algorithms required to configure and reconfigure hardware devices and interconnects are becoming more complex and diverse, with the added burden of legacy support, quirks, and hardware bugs to work around. Even programming PCI bridges in a modern PC is a surprisingly complex problem, and is getting worse as new functionality such as hotplug appears. Existing approaches use relatively simple algorithms, hard-coded in C and closely coupled with low-level register access code, generally leading to suboptimal configurations. We investigate the merits and drawbacks of a new approach: separating hardware configuration logic (algorithms to determine configuration parameter values) from mechanism (programming device registers). The latter we keep in C, and the former we encode in a declarative programming language with constraint-satisfaction extensions. As a test case, we have implemented full PCI configuration, resource allocation, and interrupt assignment in the Barrelfish research operating system, using a concise expression of efficient algorithms in constraint logic programming. We show that the approach is tractable, and can successfully configure a wide range of PCs with competitive runtime cost. Moreover, it requires about half the code of the C-based approach in Linux while offering considerably more functionality. Additionally it easily accommodates adaptations such as hotplug, fixed regions, and quirks.

A declarative language approach to device configuration

C remains the language of choice for hardware programming (device drivers, bus configuration, etc.): it is fast, allows low-level access, and is trusted by OS developers. However, the algorithms required to configure and reconfigure hardware devices and interconnects are becoming more complex and diverse, with the added burden of legacy support, quirks, and hardware bugs to work around. Even programming PCI bridges in a modern PC is a surprisingly complex problem, and is getting worse as new functionality such as hotplug appears. Existing approaches use relatively simple algorithms, hard-coded in C and closely coupled with low-level register access code, generally leading to suboptimal configurations. We investigate the merits and drawbacks of a new approach: separating hardware configuration logic (algorithms to determine configuration parameter values) from mechanism (programming device registers). The latter we keep in C, and the former we encode in a declarative programming language with constraint-satisfaction extensions. As a test case, we have implemented full PCI configuration, resource allocation, and interrupt assignment in the Barrelfish research operating system, using a concise expression of efficient algorithms in constraint logic programming. We show that the approach is tractable, and can successfully configure a wide range of PCs with competitive runtime cost. Moreover, it requires about half the code of the C-based approach in Linux while offering considerably more functionality. Additionally it easily accommodates adaptations such as hotplug, fixed regions, and quirks.

Preliminary Circuit Design for Robotics Environment Mapping Utilizing Ambient Light, Reflected Light and Stationary Infrared Radiation

Preliminary Circuit Design for Robotics Environment Mapping Utilizing Ambient Light, Reflected Light and Stationary Infrared RadiationThe paper deals with robotics mobility and a proposed topology for the acquisition of the necessary data to enable accurate mapping of a given environment, be that for basic maneuverability, (obstacle avoidance) or for higher level applications such as fire detection or item location. The topology is composed of a four layered system of analogue components which lends itself not only to excellent linearity but allows the system to control peripheral devices directly through any logic configuration, or to provide data needed for microcontrollers and their user defined algorithms. The various layers have been analyzed through simulation and to date confirmed though physical observation of the working model. The conclusions about the prospective solution are made.

Analysis of photonic logic gates based on single hexagonal-lattice photonic crystal ring resonator

We devised a new configuration of optical logic gates based on a single hexagonal-lattice photonic crystal ring resonator (PCRR) composed of two-dimensional (2D) cylindrical silicon rods in air. The modal behavior of the proposed logic gates was comprehensively analyzed with a topology optimization technique based on the principle of beam interference and perturbation theory. It was then numerically verified by using a 2D finite-difference time-domain technique. The predictions have a very good agreement with the numerical results. This new single PCRR can really function as NOT and NOR gates. And the logic "0" and "1" of the hexagonal ring can be defined as less than 8% and greater than 86%, respectively, much better than earlier reported square-lattice results.

Product Configuration Management in ICT Companies: The Practitioners’ Perspective

This article studies practical challenges experienced by ICT (Information and Communication Technology) companies when managing product configuration under the circumstances of various customer requirements, different product portfolios, and extensive product complexity. The analysis from interview results concentrates on the prioritised issues and how to ensure effective product configuration from practitioners’ perspective. The results of this study indicate that typical challenges for product configuration formalisation include fuzzy product offering, lack of configuration strategy, mechanisms, and general product structure. This research highlights the need for industrial managers to adapt a top-down approach starting from business and strategy, instead of focusing on the challenges of single products when formalising product configuration. Companies need systematic configuration logic over their entire product portfolio and not to focus only single product variant options. Consequently, they need to define a generic product structure to support product configurations that covers all product types such as hardware, software and services. This study also highlights the need for better formalization of service products since they have become an integral part of ICT products. These findings are derived from actual business circumstances and their current difficulties.

Cone-based placement for field programmable gate arrays

Deterministic greedy methods have been proposed to place the netlist of configurable logic blocks (CLBs) and primary input output blocks (IOBs) quickly on a two-dimensional (2D) island-style field programmable gate array (FPGA) consisting of either one or multiple 2D island-style arrays of CLBs and IOBs. The first method, ‘ConeCLBPlace’, starts with a random placement of the primary output blocks along the periphery of the 2D array of CLBs, then places the CLBs and primary input blocks in a greedy deterministic way. In the second method, ‘ConeIOBPlace’, the IOBs are first placed on the periphery of the FPGA chip using a deterministic heuristic, and then the CLBs are placed within the 2D array using a typical simulated annealing (SA) flow. The third method, ‘ConePlace’, combines the above two deterministic approaches by first placing the IOBs only using ConeIOBPlace, and then the CLBs using ConeCLBPlace deterministically. Finally, a low-temperature SA is executed in order to obtain a high-quality final placement. ConeCLBPlace and ConePlace produce placements 2.34× and 1.83× faster than the placement step of popular FPGA place-and-route tool VPR (versatile place and route) on the average. The bounding box costs of placement produced by ConeCLBPlace and ConePlace, after execution of the iterative SA steps, are 1.05× and 1.14× of VPR, respectively, on the average, whereas the critical path delay obtained after routing is 1.03× of VPR for both methods on the average, implying almost the same quality of VPR. This justifies the utility of the methods proposed.

Latency/area analysis and optimization of asynchronous nanowire reconfigurable crossbar system

With continued scaling of complementary metal-oxide-silicon (CMOS) technology, numerous challenges have arisen making it difficult to progress with. These challenges include the increase of integrated circuit complexity, non-recoverable expenses, frequency and power density. Nanotechnologies are expected to take the forefront of continuing the technological revolution. In this work, a novel model-based latency/area analysis and optimization method for the newly proposed Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) is presented and validated. ANRCA is based on a self-timed logic referred to as the Null Convention Logic (NCL). There is no global clocking and clock distribution network, all failure modes related to timing will be either eliminated or relaxed. The proposed architecture is anticipated to have higher manufacturability and robustness that are critical factors in nanoscale systems due to the nondeterministic nature of nanoassemblies and also suitable computing frameworks for asynchronous nanoscale communication networks. In order to facilitate efficient programming and flexible reconfiguration, a new hierarchical reconfigurable architecture for ANRCA is also proposed. Various configurable logic block structures have been considered and also their programming and reconfiguration issues are discussed. The proposed measurement and optimization method can be used to estimate area and latency measurements for different configurable logic blocks and also applied to find the optimal structure for the given arbitrary logic to map.

Built-in Self-Test Design for Fault Detection of MUXFXs in SRAM-Based FPGAs

This paper proposes a built-in self-test (BIST) design for MUXFXs in SRAM-based FPGAs. This approach can test both the interconnect resources and MUXFXs in the configurable logic blocks (CLBs). Because the test pattern generator (TPG) and output response analyzer (ORA)are configured by existing CLBs in FPGAs, no extra area overhead is needed for the proposed BIST structure. Open/short , stuck on/off faults in PSs, and stuck-at-0/1 faults in MUXFXs will be detected through the target fault detection/diagnosis of the proposed BIST structure.

A Genealogia da Lógica e a Filosofia da Lebenswelt

Abstract This paper is divided into three parts. The first part addresses the main tenets of Husserl ‘s conception of formal logic, its different levels and its relationship with formal mathematics and formal ontology. It will, therefore, undertake a delimitation of the logical domain, in its autonomy, taking as its point of departure the presentation Husserl makes of this subject in his works of maturity, particularly in Forma/e und. transzendentale Logik. The second ·part shows why, for phenomenology, the analysis of objective logical configurations has to be completed by a subjective analysis of the intentional achievements in which these configurations have their genesis. ln other words, we will try to ground such an autonomy in. the very nature of logical reason. Finally, the third and last part, following the text of the first two sections of Erfahrung und Urteil, adresses the roots of the logical-categorical activity in the ante-predicative passive experience.

Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures

Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. In an on-demand computing environment, a dynamically invoked application is assigned resources such as data bandwidth, configurable logic. The limited logic resources are customized during application execution by exploiting partial RTR. In this article, we propose an approach that maximizes application performance when available bandwidth and logic resources are limited. Our proposed approach is based on theoretical principles of minimizing application schedule length under bandwidth and logic resource constraints. It includes detailed microarchitectural considerations on a commercially popular reconfigurable device, and it exploits partial RTR very effectively by utilizing data-parallelism property of common image-processing applications. We present extensive application case studies on a cycle-accurate simulation platform that includes detailed resource considerations of the Xilinx Virtex XC2V3000. Our experimental results demonstrate that applying our proposed approach to common image-filtering applications leads to 15--20% performance gain in scenarios with limited bandwidth, when compared to prior work that also exploits data-parallelism with RTR but includes simpler bandwidth considerations. Last but not the least, we also demonstrate how our proposed theoretical principles can be directly applied to solve related problems such as minimizing schedule length under logic resource and power constraints.

An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays

State-of-the-art configurable logic platforms, such as Field-Programmable Gate Arrays (FPGAs), consist of a heterogeneous mixture of different component types. Compared to traditional homogeneous configurable platforms, heterogeneity provides speed and density advantages. This is due to the replacement of inefficient programmable logic and routing with specialized logic and fixed interconnect in components such as memories, embedded processor units, and fused arithmetic units. Given the increasing complexity of these components, this article introduces a method to automatically propose and explore the benefits of different types of fused arithmetic units. The methods are based on common subgraph extraction techniques, meaning that it is possible to explore different subcircuits that occur frequently across a set of benchmarks. A quantitative analysis is performed of the various fused arithmetic circuits identified by our tool, which are then automatically synthesized to an ASIC process, providing a study of the speed and area benefits of the components. The results of this study provide bounds on the performance of heterogeneous FPGAs: by incorporating coarse-grain components which match the specific needs of a set of benchmarks we show that significant improvements in circuit speed and area can be made.

Architecture and operating system support for two-dimensional runtime partial reconfiguration

Reconfigurable machines based on field programmable gate array (FPGA) chips adapt to applications' needs through hardware reconfiguration. Partial reconfiguration allows the configuration of a portion of a chip while the rest of the chip is busy working on tasks. This paper considers a two-dimensional partially reconfigurable FPGA chip that allows the dynamic swap in and out of circuit modules. Such a chip supports the concurrent execution of multiple applications or an application that is otherwise too large to fit. A challenging issue for 2-D runtime partial reconfiguration is how to support the efficient connection, or routing, between circuit modules or between modules and I/O pins, when those modules may be placed on any area of a chip. Because commercial chips are not efficient in 2-D runtime routing, a new FPGA architecture is proposed based on an array of clusters of configurable logic blocks and a mesh of segmented buses. To evaluate the runtime performance of the architecture, an operating system is specified and implemented which takes care of the scheduling, placement, and routing of circuits on the architecture. Simulation is used to evaluate the efficiency of the OS kernel and to determine the optimal cluster size of the architecture.

Hardware-in-the-Loop Simulation for Spacecraft Formation Flying

This paper presents a hardware-in-the-loop (HITL) simulation approach for multiple spacecraft formation flying. Considering a leader-follower formation flying configuration, a Fuzzy Logic controller is developed first to maintain the desired formation shape under external perturbations and the initial position offsets. Cold-gas on/off thrusters are developed to be introduced to the simulation loop, and the HITL simulations are conducted to validate the effectiveness of the proposed simulation configuration and Fuzzy Logic control.

A system architecting tool for mechatronic systems design

System architecting in mechatronic systems design is a crucial task to define physical and logical configurations of subsystems and components that realize desired functions and behaviors. Particularly, it is crucial to consider sensor–actuator configurations that control the quality of desired functions. The paper proposes a computer-based tool based on extended Function-Behavior-State (FBS) modeling method that incorporates visualization of geometric information and introduction of an interval-temporal logic. These extensions allow system architects to communicate with experts in different domains and domain experts to conduct domain specific design tasks without having quantitative design information about physical configuration.