Conditional Branches Research Articles

Selecting an appropriate multimedia authoring language

Multimedia is the integration of sound, pictures, videos, and text in such a way that users can navigate, explore, investigate, and create. The essence of multimedia computer-based training (CBT) is the use of conditional branching. Five multimedia authoring programs were compared: Multimedia Toolbook CBT, Director, Authorware Professional, IconAuthor, Action!, Quest, and Supercard. Comparisons include such factors as initial cost, distribution costs, platform, metaphor and logic, strengths, and support. The most critical factors, and their order of importance, in selecting an authoring language are delivery platform, level of interactivity required, need for database connectivity, the kind of support available, and the metaphor. We chose Multimedia Toolbook CBT for our use because of the availability of outside support, low cost, platform, the book metaphor, and similarity to other familiar languages (HyperCard and BASIC).

Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches

Pipeline stalls due to conditional branches represent one of the most significant impediments to realizing the performance potential of deeply pipelined, superscalar processors. Many branch predictors have been proposed to help alleviate this problem, including the Two-Level Adaptive Branch Predictor, and more recently, two-component hybrid branch predictors.In a less idealized environment, such as a time-shared system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. In this paper, we introduce a new hybrid branch predictor and show that it is more accurate (for a given cost) than any previously published scheme, especially if the branch histories are periodically flushed due to the presence of context switches.

Branch Classification: A New Mechanism for Improving Branch Predictor Performance

There is wide agreement that one of the most significant impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Speculative execution is one solution to the branch problem, but speculative work is discarded if a branch is mispredicted. For it to be effective, speculative execution requires a very accurate branch predictor; 95% accuracy is not good enough. This paper proposes branch classification, a methodology for building more accurate branch predictors. Branch classification allows an individual branch instruction to be associated with the branch predictor best suited to predict its direction. Using this approach, a hybrid branch predictor can be constructed such that each component branch predictor predicts those branches for which it is best suited. To demonstrate the usefulness of branch classification, an example classification scheme is given and a new hybrid predictor is built based on this scheme which achieves a higher prediction accuracy than any branch predictor previously reported in the literature.

An efficient graph algorithm for FSM scheduling

This paper presents a new algorithm for scheduling control-dominated designs during high-level synthesis. Our algorithm can schedule systems with arbitrary control flow, including conditional branches and multiple loops. It can handle both upper bound and lower bound timing constraints. The timing constraints can cross basic block boundaries, span different iterations of a loop, and form interlocking cycles in the control flow. A scheduling problem is described by the behavior finite-state machine model, an automaton model for the behavioral specification and synthesis of control-dominated systems. We optimize the performance of the produced digital circuit implementation by minimizing the execution time of each state transition in the state transition graph. The finite-state machines (FSM) scheduling algorithm is based on previous work on cylindrical layout compaction; we extend that work to handle upper bound constraints, allow multiple loops, and not require an initial feasible solution. Experimental results for examples derived from real designs and benchmark descriptions demonstrate that the algorithm can handle complex combinations of constraints very efficiently.

Sufficient conditions for existence of a fixed point in stochastic reward net-based iterative models

Stochastic Petri net models of large systems that are solved by generating the underlying Markov chain pose the problem of largeness of the state-space of the Markov chain. Hierarchical and iterative models of systems have been used extensively to solve this problem. A problem with models which use fixed-point iteration is the theoretical proof of the existence, uniqueness and convergence of the fixed-point equations, which still remains an art. In this paper, we establish conditions, in terms of the net structure and the characteristics of the iterated variables, under which existence of a solution is guaranteed when fixed-point iteration is used in stochastic Petri nets. We use these conditions to establish the existence of a fixed point for a model of a priority scheduling system, at which tasks may arrive according to a Poisson process or due to spawning or conditional branching of other tasks in the system.

Exploring the architecture of an early machine: the historical relevance of the ENIAC machine architecture

After presenting the historiographical background to the ENIAC development, this paper examines the technical history of the machine. The technical section looks at the architecture of the accumulators and the master programmer unit in an attempt to illustrate both the advantages and the shortcomings of the design. In particular a description of a conditional branch mechanism and parallel operations are provided-together with a discussion of reasons why they were not used in any extensive way.

A geometric approach to integer condition codes and branch instructions

article Free Access Share on A geometric approach to integer condition codes and branch instructions Author: James W. Benham Department of Mathematics and Computer Science, Montclair State University, Upper Montclair, NJ Department of Mathematics and Computer Science, Montclair State University, Upper Montclair, NJView Profile Authors Info & Claims ACM SIGCSE BulletinVolume 27Issue 4Dec. 1995 pp 35–38https://doi.org/10.1145/216511.216532Published:01 December 1995Publication History 0citation135DownloadsMetricsTotal Citations0Total Downloads135Last 12 Months19Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Global scheduling with code-motions for high-level synthesis applications

In this paper, we present a global scheduling technique for synthesis applications. The algorithm accepts a specification containing conditional branches and while-loop constructs and schedules it for a given set of resources. The algorithm performs several types of code motions across different basic blocks and trades off cost with performance. Several real-life examples taken from Numerical Recipes in C are used to demonstrate the efficacy of the approach. The results indicate that code-motions are very important for achieving significant speed-ups for synthesis applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Conceptual Proofs of $L$ Log $L$ Criteria for Mean Behavior of Branching Processes

The Kesten-Stigum theorem is a fundamental criterion for the rate of growth of a supercritical branching process, showing that an $L \log L$ condition is decisive. In critical and subcritical cases, results of Kolmogorov and later authors give the rate of decay of the probability that the process survives at least $n$ generations. We give conceptual proofs of these theorems based on comparisons of Galton-Watson measure to another measure on the space of trees. This approach also explains Yaglom's exponential limit law for conditioned critical branching processes via a simple characterization of the exponential distribution.

Avoiding conditional branches by code replication

Avoiding conditional branches by code replication

Next cache line and set prediction

Accurate instruction fetch and branch prediction is increasingly important on today's wide-issue architectures. Fetch prediction is the process of determining the next instruction to request from the memory subsystem. Branch prediction is the process of predicting the likely out-come of branch instructions. Several researchers have proposed very effective fetch and branch prediction mechanisms including branch target buffers (BTB) that store the target addresses of taken branches. An alternative approach fetches the instruction following a branch by using an index into the cache instead of a branch target address. We call such an index a next cache line and set (NLS) predictor. A NLS predictor is a pointer into the instruction cache, indicating the target instruction of a branch.In this paper we examine the use of NLS predictors for efficient and accurate fetch and branch prediction. Previous studies associated each NLS predictor with a cache line and provided only one-bit conditional branch predictors. Our study examines the use of NLS predictors with highly accurate two-level correlated conditional branch architectures. We examine the performance of decoupling the NLS predictors from the cache line and storing them in a separate tag-less memory buffer. Our results show that the decoupled architecture performs better than associating the NLS predictors with the cache line, that the NLS architecture benefits from reduced cache miss rates, and it is particularly effective for programs containing many branches. We also provide an in-depth comparison between the NLS and BTB architectures, showing that the NLS architecture is a competitive alternative to the BTB design.

A comparative analysis of schemes for correlated branch prediction

Modern high-performance architectures require extremely accurate branch prediction to overcome the performance limitations of conditional branches. We present a framework that categorizes branch prediction schemes by the way in which they partition dynamic branches and by the kind of predictor that they use. The framework allows us to compare and contrast branch prediction schemes, and to analyze why they work. We use the framework to show how a static correlated branch prediction scheme increases branch bias and thus improves overall branch prediction accuracy. We also use the framework to identify the fundamental differences between static and dynamic correlated branch prediction schemes. This study shows that there is room to improve the prediction accuracy of existing branch prediction schemes.

A Fortran 90 environment for research and prototyping of enclosure algorithms for nonlinear equations and global optimization

An environment for general research into and prototyping of algorithms for reliable constrained and unconstrained global nonlinear optimization and reliable enclosure of all roots of nonlinear systems of equations, with or without inequality constraints, is being developed. This environment should be portable, easy to learn, use, and maintain, and sufficiently fast for some production work. The motivation, design principles, uses, and capabilities for this environment are outlined. The environment includes an interval data type, a symbolic form of automatic differentiation to obtain an internal representation for functions, a special technique to allow conditional branches with operator overloading and interval computations, and generic routines to give interval and noninterval function and derivative information. Some of these generic routines use a special version of the backward mode of automatic differentiation. The package also includes dynamic data structures for exhaustive search algorithms.

Static Scheduling of Conditional Branches in Parallel Programs

The problem of scheduling non-deterministic graphs arises in several situations in scheduling parallel programs, particularly in the cases of loops and conditional branching. When scheduling loops in a parallel program, non-determinism arises because the number of loop iterations may not be known before the execution of the program. However, since loops from a restricted class of conditional branching, there is a higher degree of non-determinism associated with scheduling conditional branching. In this case, the direction of every branch remains unknown before run time. It follows that entire subprograms of the parallel program may or may not get executed, which in turn increases the amount of non-determinism and complicates the scheduling process. Thus, the term non-determinism is frequently associated with conditional branching in the literature. In this paper, we study the problem of constructing a static schedule for task graphs that contain conditional branching on parallel computers. Generally, it is difficult to obtain optimal solutions for solving various scheduling problems, even in the deterministic case. When non-determinism is added to the scheduling problem through conditional branching, an optimal solution will be even harder to obtain. We start the paper with a brief discussion of the scheduling problem, then we introduce a model for representing parallel programs that contain branches. We present a two-step scheduling technique which employs two different approaches: a graph theoretic appraoch and a multi-phase approach. The first approach is based on exploring several graph theoretic properties of the model. This approach is used as a preprocessing step to decrease the amount of non-determinism before applying the multi-phase approach. In the second step, several execution instances of the program are generated, a schedule for every instance is obtained, and a unified schedule is constructed by merging the obtained schedules. Finally, we report the results of the experiments that we conducted to measure the performance of the techniques introduced in this paper.

Parallelizing iterative loops with conditional branching

This paper considers automatic restructuring of loops with branching for parallel processing, especially a class of loops termed conditional cyclic loops. A cyclic loop possesses a dependence cycle caused by branching across loop iterations, which makes it difficult to parallelize. In general, parallel execution of a cyclic loop provides little benefit due to the need of solving a full-order nonlinear Boolean recurrence relation. However, the Boolean recurrence in practice is often of simpler forms. With the simpler forms, the number of possible predicate values of branching is reduced drastically compared to a general cyclic loop, These simple forms of cyclic loops found in practice can be parallelized for O(p/ log p) speedup with p processors. >

A speculative execution scheme of macrotasks for parallel processing systems

AbstractThis paper considers the high‐speed execution of FORTRAN programs on parallel processing systems and proposes the parallelizing scheme of the program and execution based on the speculative execution over multiple conditional branches. Several techniques have been proposed that parallelize the program including conditional branches.A method which does not use the speculative execution is: (1) the method called earliest execution condition determination. As the methods which use the speculative execution are: (2) speculative evaluation scheme for a single conditional branch for the superscalar processor or VLIW computer; and (3) multiple speculative execution scheme assuming particular loops.There are the following problems: (1) sufficient parallelism is not extracted only by determining the earliest execution condition; (2) the speed improvement that can be realized by the speculative execution of a single conditional branch is at most twofold; and (3) the scheme can be applied only to particular loops.This paper divides the program into macrotasks, and defines the multiple stage speculative execution scheme between macrotasks on the general parallel processing system. Then, the macrotask execution control for the individual macrotask is proposed, using the execution start condition, the control establishment condition and the execution stop condition.

Development of Monte Carlo Machine for Particle Transport Problem.

Monte Carlo machine, Monte-4 has been developed to realize high performance computing of Monte Carlo codes for particle transport. The calculation for particle tracking in a complex geometry requires (1) classification of particles by the region types using multi-way conditional branches, and (2) determination whether intersections of particle paths with surfaces of the regions are on the boundaries of the regions or not, using nests of conditional branches. How-ever, these procedures require scalar operations or unusual vector operations. Thus the speedup ratios have been low, i.e. nearly two times, in vector processing of Monte Carlo codes for particle transport on conventional vector processors. The Monte Carlo machine Monte-4 has been equipped with the special hardware called Monte Carlo pipelines to process these procedures with high performance. Additionally Monte-4 has been equipped with enhanced load/store pipelines to realize fast transfer of indirectly addressed data for the purpose of resolving imbalances between the performance of data transfers and arithmetic operations in vector processing of Monte Carlo codes on conventional vector processors. Finally, Monte-4 has a parallel processing capability with four processors to multiply the performance of vector processing. We have evaluated the effective performance of Monte-4 using production-level Monte Carlo codes such as vectorized KENO-IV and MCNP. In the performance evaluation, nearly ten times speedup ratios have been obtained, compared with scalar processing of the original codes.

The microarchitecture of superscalar processors

Superscalar processing is the latest in along series of innovations aimed at producing ever-faster microprocessors. By exploiting instruction-level parallelism, superscalar processors are capable of executing more than one instruction in a clock cycle. This paper discusses the microarchitecture of superscalar processors. We begin with a discussion of the general problem solved by superscalar processors: converting an ostensibly sequential program into a more parallel one. The principles underlying this process, and the constraints that must be met, are discussed. The paper then provides a description of the specific implementation techniques used in the important phases of superscalar processing. The major phases include: (1) instruction fetching and conditional branch processing, (2) the determination of data dependences involving register values, (3) the initiation, or issuing, of instructions for parallel execution, (4) the communication of data values through memory via loads and stores, and (5) committing the process state in correct order so that precise interrupts can be supported. Examples of recent superscalar microprocessors, the MIPS R10000, the DEC 21164, and the AMD K5 are used to illustrate a variety of superscalar methods.

A 64-b microprocessor with multimedia support

A 167 MHz 64 b VLSI CPU chip is described. The chip executes a 333-MFLOPS (peak) with an estimated system performance of 270SPECint92/380SPECfp92 (@167 MHz, 2 MB E-cache). The 17.7/spl times/17.8 mm die is fabricated with a 0.5 micron CMOS technology with four metal layers and contains 5.2 M transistors. The superscalar processor is capable of sustaining an execution rate of four instructions per cycle even in the presence of conditional branches and cache misses. Four fully pipelined 8/spl times/16 b multipliers and four single-cycle latency 16 b adders combine to speed up image processing, 2-D, 3-D graphics, video compression/decompression by up to an order of magnitude. High clock speed was obtained by the use of delayed reset logic, a new register file design; and novel comparators. Strict design methodology allowed fully functional first silicon which met all speed targets. The power dissipation of the chip is 28 W.

On the complexity of allocation problems in high-level synthesis

In this paper, we study the problem of processor allocation. Given a scheduled flow graph with a constant number of conditional branches, the problem is to find an assignment of the operations in the flow graph to a minimum number of processors. We show that this problem is NP-complete even if the flow graph has at most one conditional branch. Finally, we show that another related problem in high-level synthesis (mentioned as an open problem on the 24th Design Automation Conference), the so-called register allocation problem, is also NP-complete.