Journal of Electronics ManufacturingVol. 02, No. 02, pp. 45-54 (1992) PAPERSNo AccessIssues in the testability of printed wiring boardsPETER O’GRADY, CHONGSU KIM and ROBERT E. YOUNGPETER O’GRADYGroup for Intelligent Systems in Design and Manufacturing, Department of Industrial Engineering, North Carolina State University, Raleigh, NC27695–7906, USA Search for more papers by this author , CHONGSU KIMGroup for Intelligent Systems in Design and Manufacturing, Department of Industrial Engineering, North Carolina State University, Raleigh, NC27695–7906, USA Search for more papers by this author and ROBERT E. YOUNGGroup for Intelligent Systems in Design and Manufacturing, Department of Industrial Engineering, North Carolina State University, Raleigh, NC27695–7906, USA Search for more papers by this author https://doi.org/10.1142/S096031319200008XCited by:4 Next AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractThis paper discusses the issues surrounding the testability of loaded printed wiring boards (PWBs). In-circuit testing (ICT) has been widely used for testing PWBs since it can give superior diagnosis. With the advent of new board manufacturing processes, such as the use of surface mount devices, PWBs are becoming increasingly difficult to test using conventional methods. An alternative, called boundary scan architecture (BSA), has recently been proposed. This approach implements testability features within components, eliminating some of the problems of ICT. However, there are still substantial problems to be overcome before BSA can be regarded as a viable alternative to conventional testing methods. In this paper, each testing approach is reviewed and the advantages and disadvantages of each are indicated. The use of design rules to improve ICT is discussed and the major issues surrounding testability with each approach are identified. The conclusion is reached that the full implementation of BSA is some way off and that in the meantime ICT will provide the main testing method for PWBs. A key question is therefore how to improve the designs of PWBs to make them more suitable for ICT. One promising path is to provide the designer with a system for checking the design of the PWB and advising on improvements that can be made so as to improve its testability.Keywords:Testabilityin-circuit testingboundary scan architectureprinted wiring boardsconcurrent engineering FiguresReferencesRelatedDetailsCited By 4Feature-based design of electronics assembliesP. J. O'GRADY, C. KIM and Y. K M1 May 1996 | International Journal of Production Research, Vol. 34, No. 5A methodology for analysing large-scale concurrent engineering systemsY. KIM and P. J. O'GRADY1 Mar 1996 | International Journal of Production Research, Vol. 34, No. 3A system for design and concurrent engineering under imprecisionKyeongtaek Kim, Denis R. Cormier, Peter J. O'Grady and Robert E. Young1 Feb 1995 | Journal of Intelligent Manufacturing, Vol. 6, No. 1Making Circuits More than Once: The Manufacturing Challenges of Electronics Intensive ProductsD J Williams, P P Conway and D C Whalley9 August 2016 | Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture, Vol. 207, No. 2 Recommended Vol. 02, No. 02 Metrics History Received 1 November 1991 Accepted 1 December 1991 KeywordsTestabilityin-circuit testingboundary scan architectureprinted wiring boardsconcurrent engineeringPDF download
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