Computer Circuit Research Articles

Moisture-Electric Generators Working in Subzero Environments Based on Laser-Engraved Hygroscopic Hydrogel Arrays.

Moisture-electric generators (MEGs) generate power by adsorbing water from the air. However, their performance at low temperatures is hindered due to icing. In the present work, MEG arrays are developed by laser engraving techniques and a modulated low-temperature hydrogel as the absorbent material. LTH effectively captures moisture and maintains ion dissociation and migration even at subzero temperatures. Based on the double electric layer pseudocapacitance model, the oscillating circuit theory is introduced to explain the effects of moisture absorption, evaporation, and ion migration on the output current of the MEG, and the circuit calculations are matched with the experimental results. Molecular dynamics simulations indicate that LTH's low-temperature stability results from preferential hydrogen bonding between glycerol molecules and H2O, which disrupts H2O-H2O hydrogen bonds and slows water crystallization. A single MEG unit (0.25 cm2) can produce up to ∼0.8 V and ∼21.2 μW/cm2 at room temperature, and at -35 °C with 16% RH, it generates ∼0.58 V and ∼14.35 μA. MEG realizes the following applications: MEG successfully drives electronic devices in snow; arrays of 16 MEGs can power portable electronics, and 384 MEGs can achieve up to 210 V; MEG absorbs moisture in water and drives LEDs by blowing up; MEG has a flexible wearable nature; MEG is used for respiratory monitoring and photoelectric sensors.

Harnessing DNA computing and nanopore decoding for practical applications: from informatics to microRNA-targeting diagnostics.

DNA computing represents a subfield of molecular computing with the potential to become a significant area of next-generation computation due to the high programmability inherent in the sequence-dependent molecular behaviour of DNA. Recent studies in DNA computing have extended from mathematical informatics to biomedical applications, with a particular focus on diagnostics that exploit the biocompatibility of DNA molecules. The output of DNA computing devices is encoded in nucleic acid molecules, which must then be decoded into human-recognizable signals for practical applications. Nanopore technology, which utilizes an electrical and label-free decoding approach, provides a unique platform to bridge DNA and electronic computing for practical use. In this tutorial review, we summarise the fundamental knowledge, technologies, and methodologies of DNA computing (logic gates, circuits, neural networks, and non-DNA input circuity). We then focus on nanopore-based decoding, and highlight recent advances in medical diagnostics targeting microRNAs as biomarkers. Finally, we conclude with the potential and challenges for the practical implementation of these techniques. We hope that this tutorial will provide a comprehensive insight and enable the general reader to grasp the fundamental principles and diverse applications of DNA computing and nanopore decoding, and will inspire a wide range of scientists to explore and push the boundaries of these technologies.

Refined design of a DNA logic gate for implementing a DNA-based three-level circuit.

DNA computing circuits are favored by researchers because of their high density, high parallelism, and biocompatibility. However, compared with electronic circuits, current DNA circuits have significant errors in understanding the OFF state and logic "0". Nowadays, DNA circuits only have two input states: logic "0" and logic "1", where logic "0" also means the OFF state. Corresponding to an electronic circuit, it is more like an on-off switch than a logic circuit. To correct this conceptual confusion, we propose a three-level circuit. The circuit divides the input signal into three cases: "none", logic "0" and logic "1". In subsequent experiments, 34 input combinations of the primary AND gate, OR gate as well as secondary AND-OR and OR-AND cascade circuits were successfully implemented to perform the operation, which distinguished the OFF state and logic "0" correctly. Based on this, we successfully implemented a more complex voting operation with only 12 strands. We believe that our redefinition of the OFF state and logic "0" will promote tremendous developments in DNA computing circuits.

High-Speed Sequential DNA Computing Using a Solid-State DNA Origami Register.

DNA computing leverages molecular reactions to achieve diverse information processing functions. Recently developed DNA origami registers, which could be integrated with DNA computing circuits, allow signal transmission between these circuits, enabling DNA circuits to perform complex tasks in a sequential manner, thereby enhancing the programming space and compatibility with various biomolecules of DNA computing. However, these registers support only single-write operations, and the signal transfer involves cumbersome and time-consuming register movements, limiting the speed of sequential computing. Here, we designed a solid-state DNA origami register that compresses output data from a 3D solution to a 2D surface, establishing a rewritable register suitable for solid-state storage. We developed a heterogeneous integration architecture of liquid-state circuits and solid-state registers, reducing the register-mediated signal transfer time between circuits to less than 1 h, thereby achieving fast sequential DNA computing. Furthermore, we designed a trace signal amplifier to read surface-stored signals back into solution. This compact approach not only enhances the speed of sequential DNA computing but also lays the foundation for the visual debugging and automated execution of DNA molecular algorithms.

Design and Application of Programmable Analog Computing Circuit for Kalman Filter Algorithm Based on Memristive Array

Design and Application of Programmable Analog Computing Circuit for Kalman Filter Algorithm Based on Memristive Array

MAxPy: A Framework for Bridging Approximate Computing Circuits to Its Applications

This paper presents MAxPy, a framework for bridging approximate computing (AxC) circuit design to its applications. MAxPy is an application-agnostic framework able to automatically build a cycle-accurate Python model of an approximate hardware design. This model can easily be emulated and integrated as a module in Python-based applications. We are herein proposing this framework aiming to build an AxC toolbox stimulating open research in academia to promote the integration of the existing and future open-source (i) AxC benchmarks, (ii) approximate logic synthesis tools, and (iii) P unit insights. In this paper, we demonstrate the use of MAxPy to explore the AxC design space of a Sobel filter hardware design as a case study exploiting a set of approximate adders combined with the data-driven approximate logic synthesis via probabilistic pruning. Then, we present a Pareto front for circuit area, energy, and delay reduction versus the application-level metrics: edge detection accuracy and structural similarity index (SSIM). The Pareto front results of the multiple AxC techniques herein explored show circuit area savings ranging from 40.4% to 59.1% for a 98.1% to 99.6% accuracy on edge detection application MAxPy code is open source in: github.com/MAxPy-Project

OPTIMIZATION PROBLEM FOR NUMBER OF LOGIC GATES NEEDED TO IMPLEMENT MULTIPLE BOOLEAN FUNCTIONS USING DECODER

Abstract. Background. Computer circuits enable almost every piece of electronics to function. An opportunity for their optimization was found in one of the ways to implement a circuit, which involves a decoder. Decoders are basic circuit components whose behavior makes it easy to implement multiple Boolean functions. Functions are just rules by which informational signals are being processed in the circuit. To implement a function Logic gatEs (LEs) are used. LEs group multiple input signals and process them using binary logic operators like AND or NOR. Purpose. Develop a computer program that, based on provided functions, will find a solution associated with approximately minimal number of logic gates. Relevance. Prevalence of circuits increases the value of small optimizations, since any improvement gets multiplied by millions of circuits produced. Optimization at the logic level is being explored, which will retain value regardless of the physical properties of the circuit. Additionally, the theory of optimizing LE usage for circuits built on decoders is examined, which will alleviate future research. Methods. Development of the theory arose from an understanding that input signals can be grouped using LEs consciously. This way, LE outputs can be used in more than one function, which results in reduction of total number of LEs. It becomes evident that the problem can be restated in terms of sets. Similarity to known NP-hard problems emerges, which prompts usage of existing solution approaches. Among them, the greedy algorithm is chosen for its simplicity in program implementation. The connection between the problem and digital circuitry is weakened by the introduction of special evaluation functions that work with sets. So, the problem is reduced to several mathematical rules, which then are used as the appropriate parts of the greedy algorithm. Development of knowledge necessary to create the target program is thus concluded. Results. The target program is successfully implemented and can be seen in full at https://github.com/Gleb-05/MakeFuncForDC. A test is conducted on 1000 sets of four pseudorandom eight-term functions. It is estimated that the implementations proposed by the program require on average 0.75 of the initial number of LEs. The average running time is estimated at 2 milliseconds. In contrast, brute-force search for the same problem is theorized to run for years. Conclusions. A working program that finds an almost optimal solution is successfully created and tested. Its performance makes it potentially useful in the industrial scale of circuit manufacturing. Since the program essentially offers workload management, its possible applications go beyond the domain of digital electronics. Additionally, the theory of optimizing the use of LEs is presented for the first time. It can be used as the basis for future research on the implementation of multiple Boolean functions using decoder.

Lightweight skin cancer detection IP hardware implementation using cycle expansion and optimal computation arrays methods

Skin cancer is recognized as one of the most perilous diseases globally. In the field of medical image classification, precise identification of early-stage skin lesions is imperative for accurate diagnosis. However, deploying these algorithms on low-cost devices and attaining high-efficiency operation with minimal energy consumption poses a formidable challenge due to their intricate computational demands. This study proposes a lightweight hardware design based on a convolutional neural network (CNN) for real-time processing of skin disease classifiers on portable devices. Our skin cancer recognition processor utilizes an optimally parallel designed processing engine (PE) for global computation, which greatly reduces hardware resource utilization by multiplexing of computational unit circuits. In addition, a design approach that provides loop unrolling effectively reduces the number of data accesses, thereby reducing computational complexity and logic resource requirements. The hardware circuits in this design perform data inference in convolutional, pooling, and fully connected layers based on 16-bit floating-point numbers. Evaluation of the HAM10000 database dataset shows that the architecture achieves an average classification accuracy of 97.8 %. We are the first to implement an all-hardware FPGA-based skin cancer detection platform that offers a 3.5x speedup in recognition compared to existing skin cancer accelerators at 50 MHz while consuming only 0.48 W of power. The implementation of this hardware architecture meets the major constraints of portable devices, featuring low resource utilization, low power consumption, and cost-effectiveness, while still providing efficient classification and high accuracy results.

Compression-based inference of network motif sets.

Physical and functional constraints on biological networks lead to complex topological patterns across multiple scales in their organization. A particular type of higher-order network feature that has received considerable interest is network motifs, defined as statistically regular subgraphs. These may implement fundamental logical and computational circuits and are referred to as "building blocks of complex networks". Their well-defined structures and small sizes also enable the testing of their functions in synthetic and natural biological experiments. Here, we develop a framework for motif mining based on lossless network compression using subgraph contractions. This provides an alternative definition of motif significance which allows us to compare different motifs and select the collectively most significant set of motifs as well as other prominent network features in terms of their combined compression of the network. Our approach inherently accounts for multiple testing and correlations between subgraphs and does not rely on a priori specification of an appropriate null model. It thus overcomes common problems in hypothesis testing-based motif analysis and guarantees robust statistical inference. We validate our methodology on numerical data and then apply it on synaptic-resolution biological neural networks, as a medium for comparative connectomics, by evaluating their respective compressibility and characterize their inferred circuit motifs.

Reduced-order method for nuclear reactor primary circuit calculation

Reduced-order method for nuclear reactor primary circuit calculation

Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework

Augmented Reality and Virtual Reality have emerged as the next frontier of intelligent image sensors and computer systems. In these systems, 3D die stacking stands out as a compelling solution, enabling in situ processing capability of the sensory data for tasks such as image classification and object detection at low power, low latency, and a small form factor. These intelligent 3D CMOS Image Sensor (CIS) systems present a wide design space, encompassing multiple domains (e.g., computer vision algorithms, circuit design, system architecture, and semiconductor technology, including 3D stacking) that have not been explored in-depth so far. This article aims to fill this gap. We first present an analytical evaluation framework, STAR-3DSim, dedicated to rapid pre-RTL evaluation of 3D-CIS systems capturing the entire stack from the pixel layer to the on-sensor processor layer. With STAR-3DSim, we then propose several knobs for PPA (power, performance, area) improvement of the Deep Neural Network (DNN) accelerator that can provide up to 53%, 41%, and 63% reduction in energy, latency, and area, respectively, across a broad set of relevant AR/VR workloads. Last, we present full-system evaluation results by taking image sensing, cross-tier data transfer, and off-sensor communication into consideration.

A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design

The demand for energy-efficient electronic devices has driven significant advancements in low-power Very-Large-Scale Integration (VLSI) design. This paper presents a Extensive review of the recent technologies and trends that have emerged to address the challenges associated with power utilization in VLSI circuits. The review covers a broad spectrum of innovations, including advanced transistor technologies such as FinFETs, Gate-All-Around (GAA) FETs, and Silicon-on-Insulator (SOI), which offer improved power efficiency. It also explores cutting-edge power enhance techniques like Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), highlighting their impact on reducing both dynamic and leakage power. Further, the paper examines energy-efficient architectures, including Near-Threshold Computing (NTC), approximate computing, and asynchronous circuits, which promise substantial power savings. The fusing of machine learning and AI in power optimization and the development of advanced Electronic Design Automation tools are also discussed as emerging trends. Finally, the paper considers future directions, including the potential of 3D Integrated Circuits (3D ICs), quantum and neuromorphic computing, and post-CMOS technologies, to revolutionize low-power VLSI design. This review provides a critical exploration of the actual state of the art and offers comprehensions into the future trajectory of low-power VLSI, making it a valuable resource for researchers and practitioners in the field.

Development of a DSP based collaborative computing platform for power system

Abstract With the advancement of information technology, there has been tremendous progress in data production, processing, and storage technology, especially in data processing technology. With the rapid development of the power grid, its operation has become more intelligent and efficient. Traditional power system simulation and analysis tools have disadvantages, such as slow message transmission and the inability to share data, which cannot meet the requirements of modern power system simulation calculations. DSP was introduced and developed by the Southern Power Grid Research Institute and can perform various simulation calculations such as transient stability calculation, power flow calculation, and short circuit calculation. It is widely used in departments such as power planning and design. However, the data calculated by DSP is input through a data card, which is cumbersome and difficult to manage. In order to meet the new requirements of power system simulation analysis, a power system collaborative computing platform has been developed based on DSP, which makes DSP data maintenance and management more efficient and intuitive. It comprehensively improves the efficiency of power grid planning work. This article provides a detailed analysis of the architecture design and application problems of the power system collaborative computing platform, clarifies the requirements of large-scale interconnected power grids for simulation computing data management, and proposes solutions that can meet the needs of simulation computing data management in China’s power grid from two aspects: key data architecture issues and software architecture technology.

Vibrational and Dissipative Characteristic Measurement of Solid-state Wave Gyroscope Resonators: Algorithms Based on the Identification of Free Oscillation Equations

The article describes the methodological basis for constructing computational circuits of different complexity degrees and different purposes for solving a wide range of industrial and laboratory problems to measure angular irregularity of vibrational-dissipative resonatorcharacteristics of integrating solid-state wave gyroscopes. The main method to solve such problems is the identification of the coefficients of the differential equations of quartz hemispherical resonator state in the mode of its free oscillations. The resonator oscillation equations both in the fixed measuring axes and in the moving axes of standing waves were chosen as the equations of state. After reduction to slow variables, only slowly changing amplitudeequations are left for identification problems. In all the described circuits, it is assumed that the information signals for the solved identification tasks are formed in a measuring device similar to the standard gyroscope device. These algorithms make it possible to measure the vibrational and dissipative characteristics of resonators with different degrees of completeness and directionality for different standard initial requirements to themeasurement accuracy and experimental modes, which makes it possible to reduce the measurement time and labor intensity of the established set of production control operations. Among the tasks to be solved for the free run-down mode of the resonator wave pattern are the following: angular irregularity measurement of the gyroscope resonator dissipative properties under conditions of low and significant residual frequency difference; angular non-uniformity measurement of gyroscope resonator vibrational properties (its different frequency); simultaneous measurement of resonator oscillatory and dissipative characteristics for fixed and special rotating gyroscope modes. The detailed processing of the computational schemes for the implementation of these algorithms is focused on their practical application for various tasks of production operational control. At the same time, the choice of the most suitable computational algorithm from the considered options depends on the conditions, requirements and specifics of measurements.

About One Groupoid Associated with the Composition of Multilayer Feedforward Neural Networks

Abstract. The authors construct a groupoid whose elements are associated with multilayer feedforward neural networks. This groupoid is called the complete groupoid of the composition of neural networks. Multilayer feedforward neural networks (hereinafter referred to as neural networks) are modelled by defining a special type of tuple. Its components define layers of neurons and structural mappings that specify weights of synaptic connections, activation functions and threshold values. Using the artificial neuron model (that of McCulloch-Pitts) for each such tuple it is possible to define a mapping that models the operation of a neural network as a computational circuit. This approach differs from defining a neural network using abstract automata and related constructions. Modeling neural networks using the proposed method makes it possible to describe the architecture of the network (that is, the network graph, the synaptic weights, etc.). The operation in the full neural network composition groupoid models the composition of two neural networks. A network, obtained as the product of a pair of neural networks, operates on input signals by sequentially applying original networks and contains information about their structure. It is proved that the constructed groupoid is a free.

Design and Implementation of 1-bit Full Subtractor Using FinFET

Abstract: A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cout (carry-out). The sum output Sum is derived by XOR-ing the three inputs, while the carry-out Cout is obtained by considering the majority function of the inputs. This means Cout is set when any two or more of the three inputs are high (logical 1). Full subtractors are fundamental components in the construction of arithmetic logic units (ALUs), binary adders, and other computational circuits in digital systems, enabling the handling of multi-bit binary addition by cascading multiple full adders.

An efficient full-size convolutional computing method based on memristor crossbar

Modern artificial intelligence systems based on neural networks need to perform a large number of repeated parallel operations quickly. Without hardware acceleration, they cannot achieve effectiveness and availability. Memristor-based neuromorphic computing systems are one of the promising hardware acceleration strategies. In this paper, we propose a full-size convolution algorithm (FSCA) for the memristor crossbar, which can store both the input matrix and the convolution kernel and map the convolution kernel to the entire input matrix in a full parallel method during the computation. This method dramatically increases the convolutional kernel computations in a single operation, and the number of operations no longer increases with the input matrix size. Then a bidirectional pulse control switch integrated with two extra memristors into CMOS devices is designed to effectively suppress the leakage current problem in the row and column directions of the existing memristor crossbar. The spice circuit simulation system is built to verify that the design convolutional computation algorithm can extract the feature map of the entire input matrix after only a few operations in the memristor crossbar-based computational circuit. System-level simulations based on the MNIST classification task verify that the designed algorithm and circuit can effectively implement Gabor filtering, allowing the multilayer neural network to improve the classification task recognition accuracy to 98.25% with a 26.2% reduction in network parameters. In comparison, the network can even effectively immunize various non-idealities of the memristive synaptic within 30%.

Kerr-effect-based quantum logical gates in decoherence-free subspace

The decoherence effect caused by the coupling between the system and the environment undoubtedly leads to the errors in efficient implementations of two (or three) qubit logical gates in quantum information processing. Fortunately, decoherence-free subspace (DFS) introduced can effectively decrease the influence of decoherence effect. In this paper, we propose some schemes for setting up a family of quantum control gates, including controlled-NOT (CNOT), Toffoli, and Fredkin gates for two or three logical qubits by means of cross-Kerr nonlinearities in DFS. These three logical gates require neither complicated quantum computational circuits nor auxiliary photons (or entangled states). The success probabilities of three logical gates are approximate 1 by performing the corresponding classical feed-forward operations based on the different measuring results of the X-homodyne detectors, and their fidelities are robust against the photon loss with the current technology. The proposed logical gates rely on only simple linear-optics elements, available single-qubit operations, and mature measurement methods, making our proposed gates be feasible and efficient in practical applications.

Research and Design of the RF Cavity for an 11 MeV Superconducting Cyclotron

In contrast to the room temperature cyclotron, the superconducting cyclotron’s high operational magnetic field and small extraction radius lead to a magnet design with a reduced radius. This limits the space available for the RF cavity in the 11 MeV superconducting cyclotron, necessitating a more compact RF cavity design. By using the transmission line theory, the complex structure of the quarter-wavelength coaxial cavity can be represented as a microwave circuit. Through relevant theoretical analytical formulas, equivalent circuit parameters can be derived. The resonant frequency of the RF cavity is then determined using the equivalent circuit method. The optimization of the RF cavity structure was achieved by creating a numerical model and conducting finite element numerical calculations on the high-frequency resonant system. The comparative results between the equivalent circuit and numerical calculations indicate that the frequency error remains within 0.1%, validating the compact RF cavity design. A multiple linear regression analysis facilitates the prediction of resonance frequency across various parameter variables. By analyzing the fitting formula, RF cavity machining error requirements are established, ensuring a prediction error within 1%, thus meeting engineering design criteria.

New 7D and Memristor-Based 8D Chaotic Systems: Computer Modeling and Circuit Implementation

New 7D and Memristor-Based 8D Chaotic Systems: Computer Modeling and Circuit Implementation