Computer Memory Research Articles

0.765-FJ/Bit/Search Content Addressable Memory Using Search Line Pre-Charge-Free (SLPF) Scheme

Content Addressable Memories (CAMs) are high-speed hardware lookup tables that are crucial in routing, packet classification, search, and other fast look-up applications. Despite having the advantage of high speed, they have limitations due to their power hungriness. This paper addresses the limitations of existing CAMs with two novel modifications in the proposed Search Line Pre-Charge-Free Low-Power-Content Addressable Memory (SLPFCAM) structure. The first novelty is their gated evaluation matching circuit and the second is a match line pre-charge controller. The proposed design reduces the energy consumption and improves the speed of the CAM by eliminating the SLprecharge phase in the CAM operation. The pre-charge controller prevents the attempt of match line pre-charge when it is not required. The design has been implemented using Cadence Virtuoso in a 90-nm CMOS technology with 1-V supply, and the post-layout simulation results show that the SLPFCAM makes significant improvements with a minimum of 83% less power consumption, a 91% less search delay, and the average energy consumption being 0.765 fJ/bit/search.

Improved JPEG Lossless Compression for Compression of Intermediate Layers in Neural Networks Based on Compute-In-Memory

With the development of Convolutional Neural Networks (CNNs), there is a growing requirement for their deployment on edge devices. At the same time, Compute-In-Memory (CIM) technology has gained significant attention in edge CNN applications due to its ability to minimize data movement between memory and computing units. However, the deployment of complex deep neural network models on edge devices with restricted hardware resources continues to be challenged by a lack of adequate storage for intermediate layer data. In this article, we propose an optimized JPEG Lossless Compression (JPEG-LS) algorithm that implements serial context parameter updating alongside parallel encoding. This method is designed for the global prediction and efficient compression of intermediate data layers in neural networks employing CIM techniques. The results indicate average compression ratios of 6.44× for VGG16, 3.62× for ResNet34, 1.67× for MobileNetV2, and 2.31× for InceptionV3. Moreover, the implementation achieves a data throughput of 32 bits per cycle at 600 MHz on the TSMC 28 nm, with a hardware cost of 122 K Gate Count.

Robust Electric-Field Control of Colossal Exchange Bias in CrI3 Homotrilayer.

Controlling exchange bias (EB) by electric fields is crucial for next-generation magnetic random access memories and spintronics with ultralow energy consumption and ultrahigh speed. Multiferroic heterostructures have been traditionally used to electrically control EB and interfacial ferromagnetism through weak/indirect coupling between ferromagnetic and ferroelectric films. However, three major bottlenecks (lattice mismatch, interface defects, and weak/indirect coupling in multiferroic heterostructures) remain, resulting in only a few tens of milli-tesla EB field. Here, this study reports a robust electric-field control recipe to dynamically tailor the EB effect in a pure CrI3 homotrilayer on a ferroelectric Y-doped HfO2 (HYO) substrate, and demonstrate a colossal and tunable EB field (HE) from -0.15 to +0.33 T, giving rise to an EB modulation of 0.48 T. The charge doping due to ferroelectric HYO film divides a homo-configuration of CrI3 homotrilayer into one antiferromagnetic (AFM) bilayer CrI3 and one ferromagnetic (FM) monolayer CrI3, favoring direct exchange coupling. The synergies of charge doping and electric field induce a transition of magnetic orders from AFM to FM phase in bilayer CrI3, which is also supported by first-principles calculations, leading to the robust electric control of colossal EB effect. The results therefore open numerous opportunities for exploring 2D spintronics, memories, and braininspired in-memory computing.

Hierarchical Graph Neural Network: A Lightweight Image Matching Model with Enhanced Message Passing of Local and Global Information in Hierarchical Graph Neural Networks

Graph Neural Networks (GNNs) have gained popularity in image matching methods, proving useful for various computer vision tasks like Structure from Motion (SfM) and 3D reconstruction. A well-known example is SuperGlue. Lightweight variants, such as LightGlue, have been developed with a focus on stacking fewer GNN layers compared to SuperGlue. This paper proposes the h-GNN, a lightweight image matching model, with improvements in the two processing modules, the GNN and matching modules. After image features are detected and described as keypoint nodes of a base graph, the GNN module, which primarily aims at increasing the h-GNN’s depth, creates successive hierarchies of compressed-size graphs from the base graph through a clustering technique termed SC+PCA. SC+PCA combines Principal Component Analysis (PCA) with Spectral Clustering (SC) to enrich nodes with local and global information during graph clustering. A dual non-contrastive clustering loss is used to optimize graph clustering. Additionally, four message-passing mechanisms have been proposed to only update node representations within a graph cluster at the same hierarchical level or to update node representations across graph clusters at different hierarchical levels. The matching module performs iterative pairwise matching on the enriched node representations to obtain a scoring matrix. This matrix comprises scores indicating potential correct matches between the image keypoint nodes. The score matrix is refined with a ‘dustbin’ to further suppress unmatched features. There is a reprojection loss used to optimize keypoint match positions. The Sinkhorn algorithm generates a final partial assignment from the refined score matrix. Experimental results demonstrate the performance of the proposed h-GNN against competing state-of-the-art (SOTA) GNN-based methods on several image matching tasks under homography, estimation, indoor and outdoor camera pose estimation, and 3D reconstruction on multiple datasets. Experiments also demonstrate improved computational memory and runtime, approximately 38.1% and 26.14% lower than SuperGlue, and an average of about 6.8% and 7.1% lower than LightGlue. Future research will explore the effects of integrating more recent simplicial message-passing mechanisms, which concurrently update both node and edge representations, into our proposed model.

A Better Sense Amplifier Improves the Resilience in Compute-In-Memory and Row Hammer

As machine learning (ML) workloads continue to scale, the demand for higher-density DRAM (Dynamic Random-Access Memory) and SRAM (Static Random-Access Memory) is intensifying, and also driving interest in compute-in-memory (CIM) architectures as a promising approach to enhancing computational efficiency. However, increasing DRAM cell density introduces significant challenges, particularly in the reliable identification of charge sharing between cells and bit lines. This challenge heightens the susceptibility of DRAM to row hammer attacks, where unintended data corruption occurs due to repeated access to adjacent rows. Furthermore, CIM architectures necessitate more precise sensing of bit lines to ensure accurate computation within memory. In light of these challenges, our study proposes an investigation into the potential benefits of utilizing an offset compensation sense amplifier (OCSA). The OCSA is designed to address the accuracy limitations posed by high-density DRAM in CIM applications. By enhancing the precision of bit line sensing, the OCSA may mitigate the vulnerability to row hammer attacks and improve the overall reliability and performance of CIM architectures. This study will explore the effectiveness of the OCSA in maintaining data integrity and computational accuracy within high-density DRAM environments, offering insights into its applicability for future ML workloads.

A novel secure privacy-preserving data sharing model with deep-based key generation on the blockchain network in the cloud

Cloud computing is currently emerging as a developing technology in which a Cloud Service Provider (CSP) is a third-party organization that provides effective storage of data and facilities to a large client base. Saving information in a cloud offers users the satisfaction of accessing it without the need for direct knowledge of the distribution and management of an infrastructure. The primary objective is to develop a novel, secure, and privacy-preserving data-sharing model that utilizes deep-based key generation on blockchain in the cloud. Data communication is done using multiple entities. The research aims to develop a collaborative data-sharing method in the cloud for the authentication scheme for cloud security on blockchain and smart contracts. Initialization, registration, key generation, authentication of data sharing, and validation are carried out here. The proposed data-sharing model involves a revenue distribution model that depends on Multiple Services (MS) models to improve multiple cloud services. The security parameters namely passwords, hashing functions, key interpolation, and encryption are used for preserving the Data privacy and here the SpinalNet is used for generating keys. Furthermore, the devised SpinalNet_Genkey obtained a value of 45.001 MB, 0.002, and 0.003 sec for memory usage, revenue, and computation cost.

A Variation-Aware Binary Neural Network Framework for Process Resilient In-Memory Computations

Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however, it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of 128×128, our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%.

Quantized kernel recursive q-Rényi-like algorithm

This paper introduces the kernel recursive q-Rényi-like (KRqRL) algorithm, based on the q-Rényi kernel function and the kernel recursive least squares (KRLS) algorithm. To reduce the computational complexity and memory requirements of the KRqRL algorithm, an online vector quantization (VQ) method is employed to quantize the network size to a codebook size, resulting in the quantized KRqRL (QKRqRL) algorithm. This paper provides a detailed analysis of the convergence and computational complexity of the QKRqRL algorithm. In the simulation experiments, the network size of each algorithm is reduced to 25% of its original size. The performance of the QKRqRL algorithm is evaluated in terms of convergence speed, prediction error, and computation time under non-Gaussian noise conditions. Finally, the QKRqRL algorithm is further validated using sunspot data, demonstrating its superior stability and online prediction performance.

Reconfigurable Multilevel Storage and Neuromorphic Computing Based on Multilayer Phase-Change Memory.

In the era of big data, the amount of global data is increasing exponentially, and the storage and processing of massive data put forward higher requirements for memory. To deal with this challenge, high-density memory and neuromorphic computing have been widely investigated. Here, a gradient-doped multilayer phase-change memory with two-level states, four-level states, and linear conductance evolution using different pulse operations is proposed. The mechanism of multilevel states is revealed through high-resolution transmission electron microscopy (HRTEM) and finite-element analysis (FEA), which show that the sequential phase change among different sublayers is realized due to the different physical properties of the sublayers with different doping concentrations. Taking advantage of the devices' linear conductance evolution characteristic, a handwritten digit (28 × 28 pixel) recognition task is implemented with a high learning accuracy of 93.46% by building a simulated artificial neural network made up of this gradient-doped multilayer phase-change memory. It is proved that this gradient-doped multilayer phase-change memory is capable of both binary multilevel digital storage and brain-inspired analog in-memory computing in the same device, enabling reconfigurable applications in the future.

Reconfigurable Five-In-One Carbon Nanotube Optoelectronic Transistor for Intelligent Computing and Communication.

Advances in artificial general intelligence (AGI) necessitate the integration of diverse functionalities to address complex tasks. Carbon nanotubes (CNTs), with their unique physical properties, have broad applications in emerging research fields, providing a foundation for next-generation devices that could overcome the limits of Moore's Law. This work demonstrates a novel intelligent device that integrates five functions─sensors, memory, neuromorphic computing, logic, and communication─using CNT field-effect transistors (CNFETs) compatible with CMOS processes. Through passivation and annealing techniques, we have significantly enhanced the optoelectronic performance of CNFETs, leading to the development of multifunctional optoelectronic synaptic transistors. These optimized CNFETs enable dual-mode weight-tunable synaptic functions, including long-term plasticity and multilevel storage. Additionally, a CNT-based neural network has achieved high recognition accuracy on the MNIST data set, showcasing the potential of in-memory computing. This research also innovates by integrating logic functions with optoelectronic communication capabilities, paving the way for next-generation intelligent computing and communication integrated systems.

Polarization Pruning: Reliability Enhancement of Hafnia-Based Ferroelectric Devices for Memory and Neuromorphic Computing.

Ferroelectric (FE) materials are key to advancing electronic devices owing to their non-volatile properties, rapid state-switching abilities, and low-energy consumption. FE-based devices are used in logic circuits, memory-storage devices, sensors, and in-memory computing. However, the primary challenge in advancing the practical applications of FE-based memory is its reliability. To address this problem, a novel polarization pruning (PP) method is proposed. The PP is designed to eliminate weakly polarized domains by applying an opposite-sign pulse immediately after a program or erase operation. Significant improvements in the reliability of ferroelectric devices are achieved by reducing the depolarization caused by weakly polarized domains and mitigating the fluctuations in the ferroelectric dipole. These enhancements include a 25% improvement in retention, a 50% reduction in read noise, a 45% decrease in threshold voltage variation, and a 72% improvement in linearity. The proposed PP method significantly improves the memory storage efficiency and performance of neuromorphic systems.

CMN: a co-designed neural architecture search for efficient computing-in-memory-based mixture-of-experts

Artificial intelligence (AI) has experienced substantial advancements recently, notably with the advent of large-scale language models (LLMs) employing mixture-of-experts (MoE) techniques, exhibiting human-like cognitive skills. As a promising hardware solution for edge MoE implementations, the computing-in-memory (CIM) architecture collocates memory and computing within a single device, significantly reducing the data movement and the associated energy consumption. However, due to diverse edge application scenarios and constraints, determining the optimal network structures for MoE, such as the expert’s location, quantity, and dimension on CIM systems remains elusive. To this end, we introduce a software-hardware co-designed neural architecture search (NAS) framework, CIM-based MoE NAS (CMN), focusing on identifying a high-performing MoE structure under specific hardware constraints. The results of the NYUD-v2 dataset segmentation on the RRAM (SRAM) CIM system reveal that CMN can discover optimized MoE configurations under energy, latency, and performance constraints, achieving 29.67× (43.10×) energy savings, 175.44×(109.89×) speedup, and 12.24× smaller model size compared to the baseline MoE-enabled Visual Transformer, respectively. This co-design opens up an avenue toward high-performance MoE deployments in edge CIM systems.

Pain assessment from facial expression images utilizing Statistical Frei-Chen Mask (SFCM)-based features and DenseNet

Estimating pain levels is crucial for patients with serious illnesses, those recovering from brain surgery, and those receiving intensive care etc. An automatic pain intensity estimator is proposed in this study that gathers information about pain and intensity from the user’s expressions. The faces in the database are first cropped using a ‘Chehra’ face detector, which performs well even in wildly uncontrolled environments with a wide range of lighting and position fluctuations. The suggested technique extracts the beneficial and distinct patterns from facial expressions using novel Statistical Frei-Chen Mask (SFCM)-based features and DenseNet-based features. As it offers quick as well as accurate pain identification and pain intensity estimation, the Radial Basis Function Based Extreme Learning Machine (RBF-ELM) is employed for pain recognition and pain intensity level estimation using the characteristics. All the data is kept, updated and protected in the cloud because availability and high-performance decision-making are so important for informing physicians and auxiliary IoT nodes (such as wearable sensors). In addition, cloud computing reduces the time complexity of the training phase of Machine Learning algorithms in situations where it is possible to build a complete cloud/edge architecture by allocating additional computational resources and memory in use. The facial expression images from the UNBC-McMaster Shoulder Pain Expression Archive and 2D face dataset are used to test the proposed method. The measurement of pain intensity uses four stages. When compared to the results from the literature, the proposed work attains enhanced performance.

SpEpistasis: A sparse approach for three-way epistasis detection

Epistasis detection is a fundamental application in the areas of bioinformatics and biomedicine, providing important insights regarding the relationship between the human genome and the occurrence of certain diseases. Exhaustive epistasis detection approaches are employed to achieve an accurate and deterministic solution, at the cost of high computational complexity, especially when targeting high-order epistasis. While recent works employ vectorization and cache-blocking techniques to alleviate this burden, these solutions are now limited by the maximum performance of the functional units of computing systems. Thus, to further improve the performance of epistasis detection it is necessary to reduce its number of memory transfers and computations. To tackle this issue, this work proposes SpEpistasis, which performs three-way epistasis detection by relying on sparse features, which by only storing the non-zero elements of the dataset, allows for reducing the number of operations needed for epistasis detection. To achieve this goal, a new hybrid format to represent the input dataset is proposed, which stores a subset of the data in the compressed sparse row format. Moreover, new sparse-aware algorithmic approaches are also proposed in order to leverage both the hybrid format and the vector capabilities of current CPUs from Intel, AMD, and ARM. The experimental results show that SpEpistasis provides a speedup up to 3.7× and average speedups of around 1.8× and 1.33× when compared with other state-of-the-art works.

Adapting magnetoresistive memory devices for accurate and on-chip-training-free in-memory computing.

Memristors have emerged as promising devices for enabling efficient multiply-accumulate (MAC) operations in crossbar arrays, crucial for analog in-memory computing (AiMC). However, variations in memristors and associated circuits can affect the accuracy of analog computing. Typically, this is mitigated by on-chip training, which is challenging for memristors with limited endurance. We present a hardware-software codesign using magnetic tunnel junction (MTJ)-based AiMC off-chip calibration that achieves software accuracy without costly on-chip training. Hardware-wise, MTJ devices exhibit ultralow cycle-to-cycle variations, as experimentally evaluated over 1 million mass-produced devices. Software-wise, leveraging this, we propose an off-chip training method to adjust deep neural network parameters, achieving accurate AiMC inference. We validate this approach with MAC operations, showing improved transfer curve linearity and reduced errors. By emulating large-scale neural network models, our codesigned MTJ-based AiMC closely matches software baseline accuracy and outperforms existing off-chip training methods, highlighting MTJ's potential in AI tasks.

Derivation of analytic formulae for several resonance frequencies of the SparkJet actuator

Building on previous research that emphasized the importance of focusing on resonance frequencies for a fundamental understanding of the thrust and complex internal flow phenomena of the SparkJet actuators, this study theoretically derives analytic formulae for several important resonance frequencies. The research addresses the typical configuration of the SparkJet actuators, which consists of a cylindrical cavity and orifice connected by a conical converging nozzle. While the resonance frequencies of the SparkJet actuators can be obtained by solving the eigenvalue problem presented in previous studies, this eigenvalue problem, despite being a typical boundary value problem in the form of an elliptic partial differential equation, is challenging to solve using conventional numerical methods such as iterative methods, because the eigenvalue is included as an unknown in the operator. Consequently, Boundary Element Method (BEM) or methods using the Green functions have been proposed to obtain numerical solutions, but these still require handling large matrix data, resulting in significant computational costs and memory consumption. To overcome this, the current study first simplifies the eigenvalue problem using the conformal mapping presented in previous research. Then, referencing prior studies that claim that three types of resonance frequencies (Helmholtz resonance frequency and resonance frequencies representing streamwise or radial directional oscillation) significantly affect the thrust of the SparkJet actuators, characteristics of these frequencies are mathematically defined. Using these mathematical characteristics, the study derives the asymptotic and approximate solutions of the simplified eigenvalue problem, from which the resonance frequencies are obtained. The analytic formulae proposed in this study theoretically explain the already known geometric tendencies of the resonance frequencies and reveal new geometric factors influencing resonance frequencies, which were previously unknown. This approach is expected to facilitate obtaining several important resonance frequencies of the SparkJet actuator more promptly and accurately and to provide a deeper understanding of the nature of the complex oscillation phenomena inside the actuator.

MEDANet: More Efficient Dual Attention Network for Scene Segmentation

The dual attention module is a potent semantic segmentation technique renowned for its capabilities, yet it often faces significant computational demands and GPU memory usage. To tackle these challenges, we introduce an advanced dual perception network comprising two modules: A streamlined Multi-scale Efficient Position Attention Module (MEPAM) and an optimized Efficient Channel Attention Module (MECAM). MEPAM incorporates multi-scale global average pooling into the Position Attention Module (PAM), substantially cutting computational overhead and memory consumption without compromising performance. Meanwhile, MECAM integrates compressed convolutions into the Channel Attention Module (CAM), improving segmentation accuracy and inference speed compared to conventional methods like DANet. Our approach underwent comprehensive evaluation on a semantic segmentation benchmark dataset, showcasing superior performance. For instance, on the Cityscapes dataset, our method achieves an IoU of 82.2%. In terms of efficiency gains, MEPAM operates nearly 1.97 times faster than the standard PAM module on GPU, while requiring 7.55 times less memory with a [Formula: see text] input. Similarly, MECAM achieves approximately 2.2 times faster processing than CAM, while cutting GPU memory usage by 7.53 times. This innovative dual perception network not only enhances segmentation accuracy and speed but also addresses the computational challenges associated with traditional dual attention modules.

Low computational demand stray light correction method for hyperspectral imaging spectrometers

Stray light correction in hyperspectral imaging spectrometers has long been restricted by high computational requirements. This paper presents a low computational demand method, based on the matrix operations for spectrometer stray light correction, using an iterative approach to efficiently correct stray light across both spectral and spatial dimensions. The efficacy of this method is demonstrated through its application to simulated and real images, achieving an overall reduction of stray light by over 50%, with significantly reduced computation time and memory usage compared to the method by Zong et al. based on a sparse matrix [Appl. Opt. 45, 1111 (2006)10.1364/AO.45.001111APOPAI2155-3165]. By enabling stray light correction on general-purpose computers, this method enhances affordability and accessibility, promoting broader use and reducing measurement uncertainties in various hyperspectral imaging applications.

L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform

Due to the high complexity of constructing exact k -nearest neighbor graphs, approximate construction has become a popular research topic. The NN-Descent algorithm is one of the representative in-memory algorithms. To effectively handle large datasets, existing state-of-the-art solutions combine the divide-and-conquer approach and the NN-Descent algorithm, where large datasets are divided into multiple partitions, and a subgraph is constructed for each partition before all the subgraphs are merged, reducing the memory pressure significantly. However, such solutions fail to address inefficiencies in large-scale k -nearest neighbor graph construction. In this paper, we propose L-FNNG, a novel solution for accelerating large-scale k -nearest neighbor graph construction on CPU-FPGA heterogeneous platform. The CPU is responsible for dividing data and determining the order of partition processing, while the FPGA executes all construction tasks to utilize the acceleration capability fully. To accelerate the execution of construction tasks, we design an efficient FPGA accelerator, which includes the Block-based Scheduling (BS) and Useless Computation Aborting (UCA) techniques to address the problems of memory access and computation in the NN-Descent algorithm. We also propose an efficient scheduling strategy that includes a KD-tree-based data partitioning method and a hierarchical processing method to address scheduling inefficiency. We evaluate L-FNNG on a Xilinx Alveo U280 board hosted by a 64-core Xeon server. On multiple large-scale datasets, L-FNNG achieves, on average, 2.3× construction speedup over the state-of-the-art GPU-based solution.

Interface modeling analysis using density functional theory in highly reliable Pt/HfO2/TaOx/Ta self-rectifying memristor

The self-rectifying memristor (SRM) is a promising device prototype for high-density three-dimensional (3D) integration and high-efficiency in-memory computing (IMC) by virtue of its ability to effectively suppress sneak current, simple device structure, and low energy consumption. Theoretically understanding the intrinsic mechanisms of SRM is a matter of concern. Here, we fabricated a Ta/TaOx/HfO2/Pt-stacked SRM exhibiting >103 on/off ratio, rectification ratio, and nonlinearity. The SRM can be repeatedly programmed by more than 106 pulses and demonstrates robust retention and high scalability (∼59 Mbit). A reasonable interface model for this SRM is established based on first-principles calculations. Using self-energy corrected density function theory, we calculate the barrier heights at each interface. Detailed I–V curve fitting and energy band analysis are performed and computationally verified to explain the intrinsic reasons for resistive switching, self-rectifying, and nonlinear behaviors. The work may advance the development of SRM prototype to enable energy-efficient 3D IMC.