Computational Units Research Articles

Selective Trimmed Average: A Resilient Federated Learning Algorithm With Deterministic Guarantees on the Optimality Approximation.

The federated learning (FL) paradigm aims to distribute the computational burden of the training process among several computation units, usually called agents or workers, while preserving private local training datasets. This is generally achieved by resorting to a server-worker architecture where agents iteratively update local models and communicate local parameters to a server that aggregates and returns them to the agents. However, the presence of adversarial agents, which may intentionally exchange malicious parameters or may have corrupted local datasets, can jeopardize the FL process. Therefore, we propose selective trimmed average (SETA), which is a resilient algorithm to cope with the undesirable effects of a number of misbehaving agents in the global model. SETA is based on properly filtering and combining the exchanged parameters. We mathematically prove that the proposed algorithm is resilient against data and local model poisoning attacks. Most resilient methods presented so far in the literature assume that a trusted server is in hand. In contrast, our algorithm works both in server-worker and shared memory architectures, where the latter excludes the necessity of a trusted server. The theoretical findings are corroborated through numerical results on MNIST dataset and on multiclass weather dataset (MWD).

BiFSMNv2: Pushing Binary Neural Networks for Keyword Spotting to Real-Network Performance.

Deep neural networks, such as the deep-FSMN, have been widely studied for keyword spotting (KWS) applications while suffering expensive computation and storage. Therefore, network compression technologies such as binarization are studied to deploy KWS models on edge. In this article, we present a strong yet efficient binary neural network for KWS, namely, BiFSMNv2, pushing it to the real-network accuracy performance. First, we present a dual-scale thinnable 1-bit-architecture (DTA) to recover the representation capability of the binarized computation units by dual-scale activation binarization and liberate the speedup potential from an overall architecture perspective. Second, we also construct a frequency-independent distillation (FID) scheme for KWS binarization-aware training, which distills the high- and low-frequency components independently to mitigate the information mismatch between full-precision and binarized representations. Moreover, we propose the learning propagation binarizer (LPB), a general and efficient binarizer that enables the forward and backward propagation of binary KWS networks to be continuously improved through learning. We implement and deploy BiFSMNv2 on ARMv8 real-world hardware with a novel fast bitwise computation kernel (FBCK), which is proposed to fully use registers and increase instruction throughput. Comprehensive experiments show our BiFSMNv2 outperforms the existing binary networks for KWS by convincing margins across different datasets and achieves comparable accuracy with the full-precision networks (only a tiny 1.51% drop on Speech Commands V1-12). We highlight that benefiting from the compact architecture and optimized hardware kernel, BiFSMNv2 can achieve an impressive 25.1× speedup and 20.2× storage-saving on edge hardware.

Development of Power-Delay Product Optimized ASIC-Based Computational Unit for Medical Image Compression

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image.

Design of energy efficient N-bit vedic multiplier for low power hardware architecture

ABSTRACT In this paper, we introduce an advanced design of an N-bit Vedic multiplier using Nikhilam Sutra and Karatsuba algorithms, tailored for low power hardware architectures. Our approach innovatively combines these ancient mathematical techniques to significantly enhance computational efficiency in digital systems. The primary novelty of our method lies in its capability to drastically reduce both power consumption and operational delay. Compared to conventional multipliers, our design demonstrates an average area reduction of 56% and a latency reduction of 45%. Additionally, the integration of the Karatsuba algorithm optimises the structural design of the multiplier, further lowering the requirements for computational units. This dual-sutra approach not only optimises energy efficiency but also enhances overall effectiveness, making it highly suitable for image and signal processing as well as biomedical applications where power efficiency is crucial. By explicitly stating these key advancements, we aim to clearly communicate the significant strides our research has made in the field of energy-efficient hardware design.

Pre-sensor computing with compact multilayer optical neural network.

Moving computation units closer to sensors is becoming a promising approach to addressing bottlenecks in computing speed, power consumption, and data storage. Pre-sensor computing with optical neural networks (ONNs) allows extensive processing. However, the lack of nonlinear activation and dependence on laser input limits the computational capacity, practicality, and scalability. A compact and passive multilayer ONN (MONN) is proposed, which has two convolution layers and an inserted nonlinear layer, performing pre-sensor computations with designed passive masks and a quantum dot film for incoherent light. MONN has an optical length as short as 5 millimeters, two orders of magnitude smaller than state-of-the-art lens-based ONNs. MONN outperforms linear single-layer ONN across various vision tasks, off-loading up to 95% of computationally expensive operations into optics from electronics. Motivated by MONN, a paradigm is emerging for mobile vision, fulfilling the demands for practicality, miniaturization, and low power consumption.

Deployment and Evaluation of ChromeOS

This paper aims to deploy the Google ChromeFlex Operating System and evaluate its efficiency. It uses a deep learning algorithm that analyzes all results from other users with the same browser type and on the same OS. This provides a meaningful evaluation of the computer unit's stressed components, including CPU, GPU, Memory, and Storage. Findings reveal that ChromeFlex OS works efficiently when the computer is connected online. Furthermore, GPU performance in ChromeFlex OS is lower in applications requiring graphics-related work like effects and videos. Using ChromeFlex OS on computer units used for daily tasks using Internet-based applications is recommended. ChromeFlex OS is a new operating system with limited compatibility, and most productivity tools compatible with old operating systems, such as Windows OS, MAC OS, and LINUX, among others, will not run in ChromeFlex OS.

An optimized design of delay-and energy-efficient Booth multiplier

Multipliers are essential computation units in virtually all computing systems, including processors and numerous AI accelerator architectures. This paper presents an optimized architecture for a Booth multiplier, targeting high performance while minimizing energy consumption and area utilization. The design optimization focuses on all three multiplier stages: partial product generation, reduction, and summation. To enhance delay and energy efficiency in the partial product generation stage, we first employed a simplified configuration comprising inverters and a sign selection unit instead of complex binary-to-two's complement circuitry. Next, to achieve further delay and area efficiency at this stage, logic optimization is applied at the partial product's generation circuitry by designing Booth encoders to remove redundant logic in multiplexers circuitry. Moreover, we introduced specialized sign compressors tailored for carry-save compression in the compression stage. Compared to conventional counterparts, these compressors offered lower power consumption and reduced critical path delay with only two XOR logic gates. Finally, in the summation stage, we proposed an optimized design segment for Carry Look-Ahead Adder for the final summation stage, designed to deliver swift throughput with minimal fan-in logic gates, even in the context of high bit-width configurations. This segment is cascaded to make a 13-bit final adder for the summation stage in the proposed design. The proposed architecture undergoes ASIC-targeted synthesis in Cadence Genus employing FreePDK CMOS 45 nm process technology. Synthesized results, along with theoretical design complexity comparison, demonstrate that the proposed design surpasses state-of-the-art 8 × 8 multiplier designs by critical metrics, including delay, power consumption, area utilization, power delay product, and area delay product.

Optimization Research of Heterogeneous 2D-Parallel Lattice Boltzmann Method Based on Deep Computing Unit

Optimization Research of Heterogeneous 2D-Parallel Lattice Boltzmann Method Based on Deep Computing Unit

High‐Speed and Long‐Distance Spin‐Wave Propagation in Spinel γ‐Fe2O3 Epitaxial Thin Films

AbstractIn spin wave (SW) devices, the modulation of SWs for computational units is necessary, imposing extremely high demands on material systems. In this study, high‐quality epitaxial‐grown spinel γ‐Fe2O3 thin films on conductive Nb‐doped SrTiO3 substrates, achieving fast‐speed, high‐frequency, and long‐distance SW propagation in this ferrimagnetic material, are developed. A novel two‐step film growth technique using pulsed laser deposition is proposed and optimized, and the damping constant, exchange stiffness, and anisotropies of γ‐Fe2O3 are determined. Compared to reported semiconductor magnetic materials, these epitaxial‐grown γ‐Fe2O3 thin films exhibit a significantly lower damping constant of 10−2, representing a substantial advancement. Using finite‐difference calculations, SW propagation is simulated, and vital information on transmission distance and dispersion curves is obtained. Experimental results show excellent agreement with these simulations. By applying a voltage to both sides of the conducting substrate, current across the film and SW device, resulting in the frequency shift of the SWs, is generated. These results demonstrate that high‐quality γ‐Fe2O3 films developed through the two‐step growth method can efficiently propagate SWs, offering possibilities for various modulation methods in SW‐based computing devices. This study positions spinel γ‐Fe2O3 as a promising ferrimagnetic candidate for future applications in efficient SW modulation within computational systems.

Flexible multitask computation in recurrent networks utilizes shared dynamical motifs

Flexible computation is a hallmark of intelligent behavior. However, little is known about how neural networks contextually reconfigure for different computations. In the present work, we identified an algorithmic neural substrate for modular computation through the study of multitasking artificial recurrent neural networks. Dynamical systems analyses revealed learned computational strategies mirroring the modular subtask structure of the training task set. Dynamical motifs, which are recurring patterns of neural activity that implement specific computations through dynamics, such as attractors, decision boundaries and rotations, were reused across tasks. For example, tasks requiring memory of a continuous circular variable repurposed the same ring attractor. We showed that dynamical motifs were implemented by clusters of units when the unit activation function was restricted to be positive. Cluster lesions caused modular performance deficits. Motifs were reconfigured for fast transfer learning after an initial phase of learning. This work establishes dynamical motifs as a fundamental unit of compositional computation, intermediate between neuron and network. As whole-brain studies simultaneously record activity from multiple specialized systems, the dynamical motif framework will guide questions about specialization and generalization.

Conditional Information Gain Trellis

Conditional computing processes an input using only part of the neural network’s computational units. Learning to execute parts of a deep convolutional network by routing individual samples has several advantages: This can facilitate the interpretability of the model, reduce the model complexity, and reduce the computational burden during training and inference. Furthermore, if similar classes are routed to the same path, that part of the network learns to discriminate between finer differences and better classification accuracies can be attained with fewer parameters. Recently, several papers have exploited this idea to select a particular child of a node in a tree-shaped network or to skip parts of a network. In this work, we follow a Trellis-based approach for generating specific execution paths in a deep convolutional neural network. We have designed routing mechanisms that use differentiable information gain-based cost functions to determine which subset of features in a convolutional layer will be executed. We call our method Conditional Information Gain Trellis (CIGT). We show that our conditional execution mechanism achieves comparable or better model performance compared to unconditional baselines, using only a fraction of the computational resources. We provide our code and model checkpoints used in the paper at: https://github.com/ufukcbicici/cigt/tree/prl/prl_scripts.

Investigation of Resistance Switching and Synaptic Properties of VO x for Neuromorphic Applications.

The taking run on artificial intelligence in the last decades is based on the von Neumann architecture where memory and computation units are separately located from each other. This configuration causes a large amount of energy and time to be dissipated during data transfer between these two units, in contrast to synapses in biological neurons. A new paradigm has been proposed inspired by biological neurons in human brains, known as neuromorphic computing. Due to the unusual current-voltage characteristic of memristor devices such as pinched hysteresis loops, memristors are considered a key element of neuromorphic architecture. In this study, we report the basic current-voltage characteristic of the memristor devices in the form of Si/SiO2/Pt(30 nm)/VO x (3, 13, 25 nm)/Pt (30 nm) sandwich structure. Synaptic functions such as spike-time-dependent plasticity (STDP), paired-pulse facilitation (PPF), long-term potentiation (LTP), and long-term depression (LTD) of memristor devices were examined in detail. The oxide layer VO x has been grown by using the VO2 target in a pulsed laser deposition (PLD) chamber. The composition and oxidation states of the oxide layer were examined using the X-ray photoelectron spectroscopy (XPS) technique. The status of oxygen vacancies, which play an active role in the operation of the devices, was examined with a photoluminescence (PL) technique. The experimental results showed that the thickness of the oxide layer can significantly influence the synaptic and resistive switching properties of the devices.

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network

Geodesic Basis Function Neural Network.

In the learning of existing radial basis function neural networks-based methods, it is difficult to propagate errors back. This leads to an inconsistency between the learning and recognition task. This article proposes a geodesic basis function neural network with subclass extension learning (GBFNN-ScE). The geodesic basis function (GBF), which is defined here for the first time, uses the geodetic distance in the manifold as a measure to obtain the response of the sample with respect to the local center. To learn network parameters by back-propagating errors for the purpose of correct classification, a specific GBF based on a pruned gamma encoding cosine function is constructed. This function has a concise and explicit expression on the hyperspherical manifold, which is conducive to the realization of error back propagation. In the preprocessing layer, a sample unitization method with no loss of information, nonnegative unit hyperspherical crown (NUHC) mapping, is proposed. The sample can be mapped to the support set of the GBF. To alleviate the problem that one-hot encoding is not effective enough in the differential expression of data labels within a class, a subclass extension (ScE) learning strategy is proposed. The ScE learning strategy can help the learned network be more robust. For the working of GBFNN-ScE, the original sample is projected onto the support set of GBF through the NUHC mapping. Then the mapped samples are sent to the nonlinear computation units composed of GBFs in the hidden layer. Finally, the response obtained in the hidden layer is weighted by the learned weight to obtain the network output. This article theoretically proves that the separability of the data with ScE learning is stronger. The experimental results show that the proposed GBFNN-ScE has a better performance in recognition tasks than existing methods. The ablation experiments show that the ideas of the GBFNN-ScE contribute to the algorithm performance.

3D Intelligent Cloaked Vehicle Equipped with Thousand-Level Reconfigurable Full-Polarization Metasurfaces.

A crucial aspect in shielding a variety of advanced electronic devices from electromagnetic detection involves controlling the flow of electromagnetic waves, akin to invisibility cloaks. Decades ago, the exploration of transformation optics heralded the dawn of modern invisibility cloaks, which has stimulated immense interest across various physical scenarios. However, most prior research is simplified to low-dimensional and stationary hidden objects, limiting their practical applicability in a dynamically changing world. This study develops a 3D large-scale intelligent cloak capable of remaining undetectable even in non-stationary conditions. By employing thousand-level reconfigurable full-polarization metasurfaces, this work has achieved an exceptionally high degree of freedom in sculpting the scattering waves as desired. Serving as the core computational unit, a hybrid inverse design enables the cloaked vehicle to respond in real-time, with a rapid reaction time of just 70ms. These experiments integrate the cloaked vehicle with a perception-decision-control-execution system and evaluate its performance under random static positions and dynamic travelling trajectories, achieving a background scattering matching degree of up to 93.3%. These findings establish a general paradigm for the next generation of intelligent meta-devices in real-world settings, potentially paving the way for an era of "Electromagnetic Internet of Things."

Bioinspired In-Sensor Multimodal Fusion for Enhanced Spatial and Spatiotemporal Association.

Multimodal perception can capture more precise and comprehensive information compared with unimodal approaches. However, current sensory systems typically merge multimodal signals at computing terminals following parallel processing and transmission, which results in the potential loss of spatial association information and requires time stamps to maintain temporal coherence for time-series data. Here we demonstrate bioinspired in-sensor multimodal fusion, which effectively enhances comprehensive perception and reduces the level of data transfer between sensory terminal and computation units. By adopting floating gate phototransistors with reconfigurable photoresponse plasticity, we realize the agile spatial and spatiotemporal fusion under nonvolatile and volatile photoresponse modes. To realize an optimal spatial estimation, we integrate spatial information from visual-tactile signals. For dynamic events, we capture and fuse in real time spatiotemporal information from visual-audio signals, realizing a dance-music synchronization recognition task without a time-stamping process. This in-sensor multimodal fusion approach provides the potential to simplify the multimodal integration system, extending the in-sensor computing paradigm.

MODELING STOCHASTIC ADVERSE EFFECTS OF CBN 2023 REDESIGNED NAIRA NOTES POLICY ON RURAL FARMERS IN NIGERIA

The recent Central Bank of Nigeria (CBN) 2023 redesigned naira notes is of good benefits to strengthen the economy of the country by checking counterfeiting and hoarding of large volume of banknotes by the public. Despite all the efforts made by the CBN for citizens to enjoy the benefits of this implementation, most rural farmers were faced with adverse effects of uncertainties in the production and marketing of their agricultural produce due to lack of redesigned new naira notes in circulation. The adverse effects of these uncertainties are modeled as Advanced Stochastic Time-Delay Differential Equation (ASTDDE). The modeled equation is solved using Extended Second Derivative Block Backward Differentiation Formulae Method (ESDBBDFM) without the use of interpolation techniques in the evaluations of the delay term and noise term. In comparing the numerical results of this method with other existing methods in literature, the newly developed mathematical expressions for the evaluations of the delay term and the noise term in solving ASDDEs with the discrete schemes of ESDBBDFM gives better results for step number than step numbers and 3 by producing Least Minimum Absolute Random Error (LMARE) in a Lower Computational Processing Unit Time (LCPUT) faster than other existing methods that applied interpolation techniques in evaluations of the delay term and the noise term.

A two stage pipeline architecture for hardware implementation of multi-level decomposition of 1-D framelet transform

In this paper a two stage pipeline architecture for computation of multilevel decomposition of framelet transform is proposed. To handle the problem of perfect reconstruction, an area efficient symmetric extension router is used that duplicates the appropriate number of data samples of input signal at the boundary followed by reflection about the symmetry axis. In addition, to reduce the period and number of clock cycles required for computing the framelet transform, the inter-stage and intrastage pipeline of the computational units is maximized. The inter-stage pipelining is obtained by distributing the various levels of decomposition among the computational units of two stages, and a synchronization mechanism is adopted to reduce the total number of clock cycles. Similarly, the intrastage pipelining is achieved by using the pipeline registers such that the clock period is limited to the delay of multiplier and accumulator (MAC) circuit of the finite-impulse response (FIR) filter. To validate the feasibility and functionality of the proposed hardware architecture, the design is implemented on Artix7 XC7A100TCSG324-1 field-programmable gate array (FPGA) for the case of framelet transform with one low-pass and two high-pass filters. The proposed architecture is able to operate at a maximum clock frequency of 112 MHz.

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide–semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS2 field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint.

A GPU based accelerated solver for simulation of heat transfer during metal casting process

The metal casting process, which is one of the key drivers of the manufacturing industry, involves several physical phenomena occurring simultaneously like fluid flow, phase change, and heat transfer which affect the casting yield and quality. Casting process modeling involves numerical modeling of these phenomena on a computer. In recent decades, this has become an inevitable tool for foundry engineers to make defect-free castings. To expedite computational time graphics processing units (GPUs) are being increasingly used in the numerical modeling of heat transfer and fluid flow. Initially, in this work a CPU based implicit solver code is developed for solving the 3D unsteady energy equation including phase change numerically using finite volume method which predicts the thermal profile during solidification in the metal casting process in a completely filled mold. To address the computational bottleneck, which is identified as the linear algebraic solver based on the bi-conjugate gradient stabilized method, a GPU-based code is developed using Compute Unified Device Architecture toolkit and was implemented on the GPU. The CPU and GPU based codes are then validated against a commercial casting simulation code FLOW-3D CAST® for a simple casting part and against in-house experimental results for gravity die casting of a simple geometry. Parallel performance is analyzed for grid sizes ranging from 10 × 10 × 10 to 210 × 210 × 210 and for three time-step sizes. The performance of the GPU code based on occupancy and throughput is also investigated. The GPU code exhibits a maximum speedup of 308× compared to the CPU code for a grid size of 210 × 210 × 210 and a time-step size of 2 s.