Computation Tree Logic Model Research Articles

Business Process Modeled with BPMN and CTL Model Checking

Despite the richness of the BPMN language and its advantages for the specification of business processes, it remains a semi-formal language that does not allow rigorous verification of the specifications produced with it, and does not offer any methodological support to cover the verification phase. Therefore, several works have been proposed with the aim of describing the semantics of the BPMN language by a mathematical formalism. In this paper we address the issue of verifying BPMN models with an approach based on model-checking, where we focus on soundness, fairness, and safety properties. Thus by having a business process modeled by BPMN, a formal semantics for BPMN models based on Kripke structure will be provided for a formal verification of correctness. The properties are expressed with CTL (Computation Tree Logic) formulas. At the end, the model checker NuSMV is used for the verification of the formula.

Parallel computational tree logic model‐checking on pushdown systems

SummaryModel checking and static analysis have been well studied for program verification. Because of the ability to describe the stack, the pushdown system (PDS) has become a perfect model that is able to accurately model procedure calls and mimic the program's stack. Thus, it is not only a good model for sequential programs but for malware detection as well. However, with the increase of the complexity of programs, the size of models becomes huge as well. Thus, the model‐checking problem is expensive to solve. The computational tree logic (CTL) is a widely used logic and its model checking problem of PDSs can be reduced to the emptiness analysis of an alternating Büchi pushdown system (ABPDS) by determining whether there is an accepting run. When the size of a PDS is huge, the computations can be time‐consuming. To overcome this limitation, we propose a parallel solution. We propose a parallel framework based on the Compute Unified Device Architecture and the corresponding parallel algorithms to solve the emptiness problem of ABPDSs. Moreover, in order to effectively utilize the graphics processing unit, we design a new data structure of variables and an algorithm of management of thread scheduling for the parallel model. We implement our algorithms in a tool and compare our tool to a CTL model checker for PDS as a benchmark. The comparison results indicate an encouraging performance speedup.

CTL Model Checking Based on Binary Classification of Machine Learning

In this study, we establish and pioneer an approximate Computational Tree Logic (CTL) Model Checking (MC) technique, in order to avoid the famous State Explosion (SE) problem in the Computational Tree Logic Model Checking (CTLMC). To this end, some Machine Learning (ML) algorithms are introduced and employed. On this basis, CTL model checking is induced to binary classification of machine learning, by mapping all the two different results of CTL model checking into all the two different results of binary classification of machine learning, respectively. The experimental results indicate that the newly proposed approach has a has a maximal accuracy of 100% on our randomly generated data set, compared with the latest algorithm in the classical CTL model checking. Furthermore, the average speed of the new approach is at most 120 thousand times higher than that of the latest algorithm, which appears in the current version of a popular model checker called NuXMV, in the classical CTL model checking. These observations prompt that the new method can get CTL model checking results quickly and accurately, since the SE problem is avoided completely.

Formal system interactive failure analysis method based on systems theoretic process analysis model

Interactive failures are failures caused by two or more components that often occur in complex systems when the system is modified, upgraded, or simply designed inadequately. However, the official guideline provided, namely, common cause analysis, cannot discover these problems. It cannot establish a complex interactive system model, nor can it provide a unified analysis method for all parts of the system. Another method, systems theoretic process analysis, is limited to the control system.To solve this problem, a method called system theoretic formal analysis method (STFAM) is proposed in this paper. STFAM establishes a system-component-interactive model that provides an abundance of interactive information for failure analysis and presents a unified model to support the analysis of multiple components in the system. It is divided into three steps. First, a hierarchical system structure is built and then transformed into a formalized state machine. Next, the interactive failures are determined and converted into a linear temporal logic or computation tree logic model. Finally, NuSMV is used to verify the model and record the results. To evaluate the proposed method, a practical problem that occurred in full-authority digital engine control, in which in some cases, the valve closes for unknown reasons until the system is reset is presented. An analysis of the issue demonstrates the effectiveness of our method.

Performing CTL model checking via DNA computing

The computation using deoxyribonucleic acid (DNA) molecules provides an enormous parallel method that breaks through the limitations of the efficiency of traditional electronic computers. Model checking is a standard formal verification technique, which has been widely used in many fields of computation. It is also a well-known complex problem in computing theory. Until now, there is only one basic formula in the computation tree logic (CTL), for which model checking via DNA computing can be conducted. To this end, Adleman’s model based on DNA computing is used in this paper, based on which a series of DNA-computing-based model-checking algorithms to check the four basic CTL formulas are proposed. As a result, a core of the DNA version of the CTL model-checking problem is solved. The simulated experimental results show that the new algorithms are valid and can be properly implemented in molecular biology.

An Approach of XML Query Evaluation Based Model Checking

Abstract In this paper, we show the process inspired by model checking which integrate temporal logic to the application of semi-structured data query. We investigate the potential ofatechnique based on CTL (Computation Tree Logic) model checking for evaluating queries expressed in (a subset of) XPath. Our research consists of query algebra, constraint understanding and expression mapping. The core of research is mapping the XMLquery algebra to an expression collection of temporal logic. We tryanew kind of query execution strategy to enhance the accuracy of semantic description of the XMLquery. For the purpose of supporting the generation of the formal specifications and reducing the mapping processing, the XMLquery constraint can be converted toaspecification of SPS (Specification Pattern System) through which we get the formula set to evaluate path queries directly on CTLformula.

CTL Model Repair for Inter-organizational Business Processes Modelled as oWFN

Abstract Computation tree logic (CTL) model repair is an approach that extends the model checking technique to obtain new admissible models that can represent the correct design of business processes. Open workflow nets (oWFN) have shown to be adequate to model inter-organizational business processes; this formalism allows performing formal analysis such as model checking. In this work, we adapt a CTL model repair method for bounded and deadlock free Petri nets, to enable it to work with oWFN. The method is illustrated through an example of a placing purchase order process updated by adding a new supplier.

Using Computational Tree Logic Methods to Analyze Reachability in User Documentation

To support navigability, user documentation designers may use a table of contents, cross-References within procedures with page locations for related procedures, and in the case of PDF documentation, hyperlinks. Although standards and guidance exist for supporting navigable user documentation, problems appear across multiple industries including aviation and healthcare. To support user documentation development, we present a reachability analysis approach leveraging computational tree logic (CTL) reachability specifications as usability criteria coupled with a CTL model checker. A case study informed by an entry in an industry database highlights the effectiveness of the approach.

CTL Model Repair for Bounded and Deadlock Free Petri Nets

Abstract: In dependable system design, formal techniques such as model checking are useful to perform property analysis of system models. Computation tree logic (CTL) model repair is an approach that complements model checking for obtaining new admissible models that can represent the correct behaviour of systems. In this paper a CTL model repair method for bounded and deadlock free Petri nets (PN) is presented. First, CTL semantics is defined for dealing with PN and a set of basic PN structure transformation operations are introduced. Then an algorithm to repair PN models for fulfilling CTL formulae is presented. The method is illustrated through an example regarding a system which must hold a safety property.

Supervisor Synthesis to Satisfy Safety and Reachability Requirements in Chemical Process Control

A specification expressed in computation tree logic (CTL) that enforces safety and reachability requirements in discrete event systems is proposed. It is shown that the specification has a unique minimal control strategy that maximizes the set of states that satisfy the specification, and an algorithm is provided to calculate the control strategy. The specification captures the idea that the chemical process should always be able to shut down in a safe manner. The algorithm uses established CTL model checking procedures to perform the intermediate calculations, and can incorporate symbolic model checking. The maximum problem size for which a control strategy can be calculated is similar to that of the corresponding verification problem. A small example demonstrates the application of the algorithm to a problem that includes safety and reachability constraints. Current work aims to use the techniques to solve a real process control problem supplied by industry.

CTL Model Update for System Modifications

Model checking is a promising technology, which has been applied for verification of many hardware and software systems. In this paper, we introduce the concept of model update towards the development of an automatic system modification tool that extends model checking functions. We define primitive update operations on the models of Computation Tree Logic (CTL) and formalize the principle of minimal change for CTL model update. These primitive update operations, together with the underlying minimal change principle, serve as the foundation for CTL model update. Essential semantic and computational characterizations are provided for our CTL model update approach. We then describe a formal algorithm that implements this approach. We also illustrate two case studies of CTL model updates for the well-known microwave oven example and the Andrew File System 1, from which we further propose a method to optimize the update results in complex system modifications.

A verification system for transient response of analog circuits

We present a method for application of formal techniques like model checking and equivalence checking for validation of the transient response of nonlinear analog circuits. We propose a temporal logic called Ana CTL (computational tree logic for analog circuit verification) which is suitable for specifying properties specific to analog circuits. The application of Ana CTL for validation of transient behavior of arbitrarily nonlinear analog circuits is presented. The transient response of a circuit under all possible input waveforms is represented as a finite state machine (FSM), by bounding and discretizing the continuous state space of an analog circuit. We have developed algorithms to run Ana CTL queries on this discretized model using search-based methods which reduce the runtime considerably by avoiding creation of the whole FSM. The application of these methods on several real-life analog circuits is presented and we show that this system is a useful aid for detecting and debugging early design errors. We also present methods for checking the equivalence of transient response of two analog circuits. The behavior of two different analog circuits can rarely be exactly similar. Hence, we introduce a notion of approximate equivalence. A query language for checking different notions of user-definable approximate equivalence is presented which extends the syntax of the Ana CTL model checking language. In its extended form, Ana CTL can be used combining model checking with equivalence checking.