Computational Scaling Research Articles

An Algorithm for Automatic Photo Typesetting Based on Kinship

Photo typesetting belongs to the rectangular packing problems, currently the algorithms of rectangular packing problems can be divided into two categories: heuristic methods and modern intelligent based methods. For both of these methods, the similarity of contents do not be well considered, the packing order of the rectangular pieces are chaos. Therefore, this drawback will cause problems for photo typesetting. In this paper we propose a hybrid algorithm for the photo typesetting problem based on kinship. According to our algorithm, the kinship of difierent photos is calculated by their absolute paths, and then all photos are packed based on the distance of their kinship. Compared with the existing methods, according to the computation of difierent scales of tests, our algorithm shows faster typesetting speed and higher utilization ratios. This algorithm could solve the sort problem caused by chaos typesetting photos of difierent customers after lots of photos were typeset. Our algorithm could greatly improve the practical application of photo typesetting.

Computational technique to overcome the limit of a photomask writer

We present the limit of a conventional photomask writer and new possibilities to meet various requirements of tight specifications for a sub-10 nm device. The issues of a variable shaped beam (VSB) writer and how to overcome the limit by computational techniques are discussed. Because VSB writing can use only one rectangular or triangular beam per shot, the complex design for computational lithography results in the increase of shot number to implement rounded or angled pattern. Based on model-based-fracturing, we have confirmed that the ideal curvilinear pattern can be optimized by using overlapping shots, and that they have the same patterning performance in mask and wafer. On the other hand, the multibeam writer can make ideally any kinds of shapes, even curvilinear design because the combination of small spots writes a design. In a real situation, each spot of multibeam writer is defined at fixed mesh and each beam has discrete dose level, so that there are fidelity errors if the pixel size is large or the dose level is not enough large. Here, we propose a “Buddhist cross” design as the evaluation pattern of digitization error in a multibeam writer. The “fidelity error” smaller than 0.5 nm error requires 5 nm pixel size and the required minimum number for dose level is 7 to implement a smaller error than 0.05 nm at one edge. To realize new technology for mass production, new data flow, model based pattern verification, and required computing power have been presented.

Robust source and mask optimization compensating for mask topography effects in computational lithography.

Mask topography effects need to be taken into consideration for a more accurate solution of source mask optimization (SMO) in advanced optical lithography. However, rigorous 3D mask models generally involve intensive computation and conventional SMO fails to manipulate the mask-induced undesired phase errors that degrade the usable depth of focus (uDOF) and process yield. In this work, an optimization approach incorporating pupil wavefront aberrations into SMO procedure is developed as an alternative to maximize the uDOF. We first design the pupil wavefront function by adding primary and secondary spherical aberrations through the coefficients of the Zernike polynomials, and then apply the conjugate gradient method to achieve an optimal source-mask pair under the condition of aberrated pupil. We also use a statistical model to determine the Zernike coefficients for the phase control and adjustment. Rigorous simulations of thick masks show that this approach provides compensation for mask topography effects by improving the pattern fidelity and increasing uDOF.

Impact of 14-nm photomask uncertainties on computational lithography solutions

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total critical dimension (CD) control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine via simulation the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state-of-the-art mask manufacturing data, and other variable changes are speculated, highlighting the need for improved metrology and communication between mask and optical proxmity correction model experts. The simulations are done by ignoring the wafer photoresist model and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the one-dimensional/two-dimensional representation of the mask, and for three-dimensional, the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.

Inverse e-beam lithography on photomask for computational lithography

Computational lithography, e.g., inverse lithography technique (ILT) and source mask optimization, is considered necessary for the “extremely low k1” lithography process of sub-20 nm device node. The ideal design of a curvilinear mask for computational lithography requires many changes during photomask fabrication. These range from preparation of the mask data to measurement and inspection. The manufacturability of a photomask for computational lithography is linked to predictable and manageable quality of patterning. Here, we have proposed the use of “inverse e-beam lithography” on photomask for computational lithography, which overcomes the patterning accuracy limits of conventional e-beam lithography. Furthermore, the preferred target design for ILT, a new verification method, and the accuracy required for the mask model are also discussed; with consideration of acceptable writing time (<24 h ) and computing power.

Kafai Lai: Exploring technology solutions with computational lithography

Kafai Lai: Exploring technology solutions with computational lithography

(Invited) Efficient Mask Synthesis with Augmented Lagrangian Methods in Computational Lithography

A fast approach based on augmented Lagrangian methods (ALMs) is proposed to solve the inverse imaging problem in optical lithography, known as inverse lithography technology. We develop a constrained optimization framework where the objective function includes a data- fidelity term and a binary equality constraint. We show how optimal solutions are reached with less execution time by applying the quasi-Newton method to the sub-problem. The proposed scheme also includes a tentative penalty parameter schedule for adjustment and control. Simulation results are compared with existing source-mask optimization (SMO) to illustrate the performance improvement in terms of pattern fidelity, convergence rate and process window size.

(Invited) Advanced Modeling for Full-Chip Low-k1 Lithography Simulations

Full-chip computational lithography is an important technology that enables low-k1 patterning. Examples of its applications include optical proximity correction (OPC), source-mask optimization (SMO) and verifications. In these applications, lithography models are required to predict the printed patterns on the wafer. Therefore the model accuracy has a direct impact to the quality of the final result. Rigorous physical models are accurate but computationally expensive. Therefore simple approximate models are generally used in full-chip applications. As the k1-factor continues to shrink, the errors produced by these simple models become unacceptable. Advanced models with improved accuracy and reasonable speed are required for low-k1 applications. In this work we will discuss the issues with the existing full-chip models and the development of advanced models.

Review of computational lithography modeling: focusing on extending optical lithography and design-technology co-optimization

Abstract Advances in computational lithography over the last 10 years have been instrumental to the continued scaling of semiconductor devices. Competitive scaling requires two types of complementary models: fast predictive empirical models that can be used for pattern correction and verification; rigorous physical models that can be used to identify key physical effects that must be considered to ensure pattern fidelity, but are too resource intensive to use for full chip applications. Today, all computational lithography efforts such as the optical proximity correction (OPC) and the optical rules check (ORC) depend on the ability to predictively model the lithography and metrology processes. We discuss some of the current modeling practices in optics, mask, resist and etching, leading to the “Holy Grail” of predictively modeling entire patterning process which we call “virtual fab”. Extreme ultraviolet (EUV) modeling is discussed due to its potential to extend optical lithography scaling for future nodes. Modeling of novel technologies such as Diblock Copolymer patterning is also discussed to demonstrate new opportunities for continued scaling. Complexity of the “virtual fab” approach is extremely high as there are multiple dimensions in this approach. The need to overcome this complexity, by reducing the number of dimensions of the problem, is evident. Lastly, the ability to leverage lithography modeling in design co-optimization is an important element of semiconductor device scaling.

Computational lithography: Exhausting the resolution limits of 193-nm projection lithography systems

In the recent past, scaling of semiconductor fabrication systems has been dominated by wavelength and numerical aperture modifications. This is now no longer the case for 193-nm immersion projection lithography (193i) systems as there are no technical paths for continued benefit from the in these areas. Instead, a range of techniques including patterning processes and system optimization are being used to push the limits of the system. This paper will review the elements that are now driving scaling for a system of fixed wavelength and numerical aperture.

Optimal 3D phase-shifting masks in partially coherent illumination

Gradient-based phase-shifting mask (PSM) optimization methods have emerged as an important tool in computational lithography to solve for the inverse lithography problem under the thin-mask assumption, where the mask is considered a thin two-dimensional object. As the critical dimension printed on the wafer shrinks into the subwavelength regime, thick-mask effects become prevalent and thus these effects must be taken into account in PSM optimization methods. Thick-mask effects are particularly aggravated and pronounced in etching profiles with abrupt discontinuities and trench depths. PSM methods derived under the thin-mask assumption have inherent limitations and perform poorly in the subwavelength scenario. This paper focuses on developing three-dimensional PSM optimization methods that can overcome the thick-mask effects in lithography systems with partially coherent illumination. The boundary layer model is exploited to simplify and characterize the thick-mask effects, leading to a gradient-based PSM optimization method. Several illustrative simulations are presented.

Exposed Pattern Interaction of Litho-cure-litho-etch Process in Computational Lithography

Exposed Pattern Interaction of Litho-cure-litho-etch Process in Computational Lithography

Using FlexRay in Computational Lithography

Using FlexRay in Computational Lithography

Using FlexRay in Computational Lithography

FlexRay programmable illumination and LithoTuner software is combined in several use cases. The first use case is source mask optimization (SMO) in which the process window is maximized for a static random access memory (SRAM) design. In a 55 nm half-pitch contact hole array (k1 = 0.38, NA= 1.35, λ= 193 nm), the process window (PW) with FlexRay programmable illumination is twice as large as the PW with cQuad illumination defined through completely refractive illumination. The second use case is optical proximity error (OPE) minimization in which the large PW from SMO is realized on every scanner in the fab. The OPE error is reduced by 17% with LithoTuner and FlexRay. The third use case is matching two ArF scanners, a 1950i with FlexRay to a 1700i with diffractive optical element (DOE) illumination. With LithoTuner and FlexRay, the root means squared (rms) critical dimension (CD) error is reduced by 29% in this third use case. The last use case, intrafield dose optimization with DoseMapper is combined with FlexRay programmable source optimization to reduce the CD error on a wafer from a mean-to-target critical dimension (CD) error in the mask manufacturing process. This combination was optimized with LithoTuner to reduce the root mean square (rms) wafer CD error by 30%.

From Computational Lithography to Computational Inspection: Inverse Lithography Technology (ILT) and Inverse Inspection Technology (IIT)

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.

Nebulous hotspot and algorithm variability in computation lithography

Computation lithography relies on algorithms. However, these algorithms exhibit variability that can be as much as 5% one stan- dard deviation of the critical dimension for the 65-nm technology. Using hotspot analysis and fixing as an example, we argue that such variability can be addressed on the algorithm level via controlling and eliminating its root causes, and on the application level by setting specifications that are commensurate with both the limitations of the algorithms and the goals of the application. © 2010 Society of Photo-Optical Instrumentation Engineers.

Numerical Age and Residence-Time Mapping for a Small Tidal Creek: Case Study

A numerical modeling study, using an Eulerian tracer and Lagrangian particle-tracking methods, was carried out to map the age of water and residence-time distribution in the tide-dominated East Scott Creek Estuary, South Carolina. A coupled hydrodynamic, solute-transport, and particle-transport model was developed. The flow and solute-transport models were based on depth-integrated conservation equations and the particle-transport model was quasi-three-dimensional. The equations were discretized using the total variation diminishing finite-volume method. The numerical model predictions were verified against a set of field-measured hydrodynamic data, with the model-predicted water elevations and velocities in good agreement with the field measurements. Different methods of computing the age of water and the residence time that are applicable to tide-dominated estuaries and suitable for high-resolution flow and transport numerical modeling setup were investigated. An Eulerian method, based on the tracer-age theory, and a Lagrangian particle-tracking method were each used to map the age and the residence-time distribution throughout the main channel of East Scott Creek. The performance of the two methods in the given tide-dominated environment was investigated through a series of numerical experiments. The effects of the particle and tracer release time and tidal amplitude in the computation of tidal exchange-time scales were also investigated. The residence time computed by the Eulerian method scaled well with that of the Lagrangian method and produces a relatively smooth monotonic profile of the residence time in space. The Lagrangian method, unlike the Eulerian method, consistently showed a more detailed distribution of significant and varying nonmonotonic profile of residence times; yet, the two methods produce, in the tidally averaged sense, reasonably comparable residence-time distributions. The residence time computed by the Lagrangian method is very sensitive to the phase of the tidal forcing at the beginning of the computation.

On the flow field generated by a gradually varying flow through an orifice

The motion of a vortex ring generated by gradually varied flows through a thin-edged orifice has been investigated experimentally using particle image velocimetry. This flow reproduces the primary characteristics of many biological flows, such as cardiac flows through valves or jellyfish and squid propulsion. Even though vortex ring formation has been extensively studied, there is still interest in gradually varying inflows, i.e. the ones that are mostly found in previous conditions. The main purpose of this paper is to extend the time scaling already proposed in the literature to the entire cycle of vortex ring formation, pinch-off and free motion. To this end, eight inflow time laws have been tested, with different acceleration and deceleration phases. They have been selected in relation to practical applications by their resemblance to the main characteristics of cardiovascular and pulsed locomotion flows. Analysis of measured velocity and vorticity fields suggested a general criterion to establish the instant of vortex pinch-off directly from the imposed velocity program. This allows the proper scaling of the entire time evolution of the vortex ring for all tested inflows. Since it is quite easy to identify this instant experimentally, these results give a simple, practical rule for the computation of scales in vortex ring formation and development in the case of gradual inflows. The “slug model” has been used to test the proposed scaling and to obtain predictions for the vortex position, circulation and vorticity which are in agreement with experimental data.

Accelerated A Posteriori Error Estimation for the Reduced Basis Method with Application to 3D Electromagnetic Scattering Problems

We propose a new method for fast estimation of error bounds for outputs of interest in the reduced basis context, efficiently applicable to real world 3D problems. Geometric parameterizations of complicated 2D, or even simple 3D, structures easily leads to affine expansions consisting of a high number of terms ($\propto100-1000$). Application of state-of-the-art techniques for computation of error bounds becomes practically impossible. As a way out we propose a new error estimator, inspired by the subdomain residuum method, which leads to substantial savings (orders of magnitude) regarding online and offline computational times and memory consumption. We apply certified reduced basis techniques with the newly developed error estimator to 3D electromagnetic scattering problems on unbounded domains. A numerical example from computational lithography demonstrates the good performance and effectivity of the proposed estimator.

What is double patterning lithography and its impact on nanometer design?

Deep sub-wavelength lithography, i.e., using the 193nm lithography to print feature sizes/densities (e.g., for 45nm, 32nm, 22nm nodes) much smaller than the wavelength (193nm), is one of the most fundamental challenges for the nanometer CMOS scaling. Many intriguing techniques have been developed to push the limit of the 193nm lithography, from immersion lithography to computational lithography. However, even with these exotic techniques, the single patterning 193nm lithography is approaching its ultimate limit around the 22nm node. On the other hand, the so-called next generation lithography (NGL), including extreme ultraviolet (EUV) lithography, nano- imprint lithography (NIL), multiple e-beam direct-write (MEBDW) is still "next-generation" (i.e., not ready for primetime in 22nm or perhaps even the 16nm node) due to many technology challenges (not to mention the economical barriers to adopt them).