Tree Compression Research Articles

Short-term air quality prediction using point and interval deep learning systems coupled with multi-factor decomposition and data-driven tree compression

Clean air, as a symbol of high-quality air quality, is the most basic requirement for people to maintain health. Moreover, in keeping humans fit, accurate short-term air quality prediction is vital. The decomposition algorithm can better capture the local features and temporal changes of the data. However, it increases the computation time, resource consumption, and complexity of the model. On the other hand, existing forecasting systems overlook instability and uncertainty. To solve the above problems, a deterministic and uncertainty AOA-DBGRU-MDN deep learning systems is proposed, which combines arithmetic optimization algorithm (AOA), double-layer bi-directional GRUs (DBGRU), and mixture density network (MDN). The above systems consider meteorological factors and air pollutants comprehensively. It involves feature selection using maximum information coefficient (MIC), decomposition using complete ensemble empirical mode decomposition with adaptive noise (CEEMDAN) algorithm, classification, and compression of decomposed components using entropy-Huffman tree compression. Firstly, the information measurement process reduces the number of components significantly. Following the incorporation of multi-factor data, the optimal DBGRU model is then obtained using AOA. Finally, the training errors are fitted using MDN to obtain interval prediction results. The experiments demonstrate that (1) Using the CEEMDAN algorithm can improve the prediction accuracy; (2) Classifying and reconstructing the data based on entropy-Huffman tree compression can not only decrease the model's training volume and improve training efficiency but also boost the model's prediction accuracy; (3) The AOA-DBGRU-MDN system performs probabilistic prediction to obtain an effective and intuitive prediction interval to improve the point prediction of air quality prediction.

Wasserstein Auto-Encoders of Merge Trees (and Persistence Diagrams).

This article presents a computational framework for the Wasserstein auto-encoding of merge trees (MT-WAE), a novel extension of the classical auto-encoder neural network architecture to the Wasserstein metric space of merge trees. In contrast to traditional auto-encoders which operate on vectorized data, our formulation explicitly manipulates merge trees on their associated metric space at each layer of the network, resulting in superior accuracy and interpretability. Our novel neural network approach can be interpreted as a non-linear generalization of previous linear attempts (Pont et al. 2023) at merge tree encoding. It also trivially extends to persistence diagrams. Extensive experiments on public ensembles demonstrate the efficiency of our algorithms, with MT-WAE computations in the orders of minutes on average. We show the utility of our contributions in two applications adapted from previous work on merge tree encoding (Pont et al. 2023). First, we apply MT-WAE to merge tree compression, by concisely representing them with their coordinates in the final layer of our auto-encoder. Second, we document an application to dimensionality reduction, by exploiting the latent space of our auto-encoder, for the visual analysis of ensemble data. We illustrate the versatility of our framework by introducing two penalty terms, to help preserve in the latent space both the Wasserstein distances between merge trees, as well as their clusters. In both applications, quantitative experiments assess the relevance of our framework. Finally, we provide a C++ implementation that can be used for reproducibility.

Slowing down top trees for better worst-case compression

We consider the top tree compression scheme introduced by Bille et al. [ICALP 2013] and construct an infinite family of trees on n nodes labeled from an alphabet of size σ, for which the size of the top DAG is Θ(nlogσ⁡nlog⁡logσ⁡n). Our construction matches a previously known upper bound and exhibits a weakness of this scheme, as the information-theoretic lower bound is Ω(nlogσ⁡n). Lohrey et al. [IPL 2019] designed a more involved version of the original algorithm achieving the lower bound. We show that this can be also guaranteed by a very minor modification of the original scheme: informally, one only needs to ensure that different parts of the tree are not compressed too quickly. Arguably, our version is more uniform, and in particular, the compression procedure is oblivious to the value of σ.

Phylo2Vec: a vector representation for binary trees

Abstract Binary phylogenetic trees inferred from biological data are central to understanding the shared history among evolutionary units. However, inferring the placement of latent nodes in a tree is computationally expensive. State-of-the-art methods rely on carefully designed heuristics for tree search, using different data structures for easy manipulation (e.g., classes in object-oriented programming languages) and readable representation of trees (e.g., Newick-format strings). Here, we present Phylo2Vec, a parsimonious encoding for phylogenetic trees that serves as a unified approach for both manipulating and representing phylogenetic trees. Phylo2Vec maps any binary tree with n leaves to a unique integer vector of length n − 1. The advantages of Phylo2Vec are fourfold: i) fast tree sampling, (ii) compressed tree representation compared to a Newick string, iii) quick and unambiguous verification if two binary trees are identical topologically, and iv) systematic ability to traverse tree space in very large or small jumps. As a proof of concept, we use Phylo2Vec for maximum likelihood inference on five real-world datasets and show that a simple hill-climbing-based optimisation scheme can efficiently traverse the vastness of tree space from a random to an optimal tree.

High-efficiency Compressor Trees for Latest AMD FPGAs

High-fan-in dot product computations are ubiquitous in highly relevant application domains, such as signal processing and machine learning. Particularly, the diverse set of data formats used in machine learning poses a challenge for flexible efficient design solutions. Ideally, a dot product summation is composed from a carry-free compressor tree followed by a terminal carry-propagate addition. On FPGA, these compressor trees are constructed from generalized parallel counters whose architecture is closely tied to the underlying reconfigurable fabric. This work reviews known counter designs and proposes new ones in the context of the new AMD Versal™ fabric. On this basis, we develop a compressor generator featuring variable-sized counters, novel counter composition heuristics, explicit clustering strategies, and case-specific optimizations like logic gate absorption. In comparison to the Vivado™ default implementation, the combination of such a compressor with a novel, highly efficient quaternary adder reduces the LUT footprint across different bit matrix input shapes by 45% for a plain summation and by 46% for a terminal accumulation at a slight cost in critical path delay still allowing an operation well above 500 MHz. We demonstrate the aptness of our solution at examples of low-precision integer dot product accumulation units.

Dual image based secured reversible data hiding scheme exploiting huffman compression tree combining bit-reversal permutation technique

Dual image based secured reversible data hiding scheme exploiting huffman compression tree combining bit-reversal permutation technique

The fast and the capacious: memory-efficient multi-GPU accelerated explicit state space exploration with GPUexplore 3.0

The GPU acceleration of explicit state space exploration, for explicit-state model checking, has been the subject of previous research, but to date, the tools have been limited in their applicability and in their practical use. Considering this research, to our knowledge, we are the first to use a novel tree database for GPUs. This novel tree database allows high-performant, memory-efficient storage of states in the form of binary trees. Besides the tree compression this enables, we also propose two new hashing schemes, compact-cuckoo and compact multiple-functions. These schemes enable the use of Cleary compression to compactly store tree roots. Besides an in-depth discussion of the tree database algorithms, the input language and workflow of our tool, called GPUexplore 3.0, are presented. Finally, we explain how the algorithms can be extended to exploit multiple GPUs that reside on the same machine. Experiments show single-GPU processing speeds of up to 144 million states per second compared to 20 million states achieved by 32-core LTSmin. In the multi-GPU setting, workload and storage distributions are optimal, and, frequently, performance is even positively impacted when the number of GPUs is increased. Overall, a logarithmic acceleration up to 1.9× was achieved with four GPUs, compared to what was achieved with one and two GPUs. We believe that a linear speedup can be easily accomplished with faster P2P communications between the GPUs.

A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree

In a multitude of computational and signal processing scenarios, the multiplier functions as a fundamental arithmetic component. Given the complex hardware arrangement of multipliers and their usual positioning within the crucial pathway of digital systems, their significance is substantial. Therefore, approximations of multipliers can greatly optimize system performance. This essay examines the fundamental ideas behind the Wallace tree, the Carry ahead adder, and the Radix-4 Booth algorithm. Additionally, instead of the more common 3-2 compressors, a Wallace tree structure with 4-2 compressors is used to compact these products for the manufacture of partial products. This reduction in compression stages to three significantly curtails delays along critical paths, thereby substantially improving overall performance. The compressed outcomes from the Wallace tree undergo processing via a 64 bit carry ahead adder, effectively addressing delays stemming from mutual carry propagation among sequentially connected regular full adders. Leveraging these principles and processes, a 32-bit signed multiplier is designed. Building upon this foundation, an approximate Booth multiplier is developed, enhancing both computational speed and reducing critical path delays. The functionality of the multiplier was validated using Vivado simulation, demonstrating its correctness. Additionally, the RTL-level circuitry of different segments of the multiplier was showcased.

Characterizing the assembly of dark matter haloes with protohalo size histories: I. Redshift evolution, relation to descendant haloes, and halo assembly bias

ABSTRACT We propose a novel method to quantify the assembly histories of dark matter haloes with the redshift evolution of the mass-weighted spatial variance of their progenitor haloes, that is, the protohalo size history. We find that the protohalo size history for each individual halo at z ∼ 0 can be described by a double power-law function. The amplitude of the fitting function strongly correlates to the central-to-total stellar mass ratios of descendant haloes. The variation of the amplitude of the protohalo size history can induce a strong halo assembly bias effect for massive haloes. This effect is detectable in observation using the central-to-total stellar mass ratio as a proxy of the protohalo size. The correlation to the descendant central-to-total stellar mass ratio and the halo assembly bias effect seen in the protohalo size are much stronger than that seen in the commonly adopted half-mass formation time derived from the mass accretion history. This indicates that the information loss caused by the compression of halo merger trees to mass accretion histories can be captured by the protohalo size history. Protohalo size thus provides a useful quantity to connect protoclusters across cosmic time and to link protoclusters with their descendant clusters in observations.

An Empirical Selection of Wavelet for Near-Lossless Medical Image Compression.

Wavelets are defined as mathematical functions that segment the data into different frequency levels. We can easily capture the fine and coarse details of an image or signal referred to as a subband. And it also helps in subband thresholding to achieve good compression performance. In recent days in telemedicine services, the handling of medical images is prominently increasing and it leads to the demand for medical image compression. While compressing the medical images, we have to concentrate on the data that holds important information, and at the same time, it must retain the image quality. Near-Lossless compression plays an essential role to achieve a better compression ratio than lossy compression and provides better quality than lossless compression. In this paper, we analyzed the sub-banding of Discrete Wavelet Transform (DWT) using different types of wavelets and made an optimal selection of wavelets for subband thresholding to attain a good compression performance with an application to medical images. We used Set Partitioning In Hierarchical Trees (SPIHT) compression scheme to test the compression performance of different wavelets. The Peak Signal to Noise Ratio (PSNR), Bits Per Pixel (BPP), Compression Ratio, and percentage of number of zeros are used as metrics to assess the performance of all the selected wavelets. And to find out its efficiency in possessing the essential information of medical images, the subband of the selected wavelets is further utilized to devise the near-lossless compression scheme for medical images.

Performance analysis of wireless transmission of compressed images using DCT‐OFDMA system with different compression schemes

AbstractTransmitting images over an Orthogonal Frequency Division Multiplexing Access (OFDMA) system poses a significant challenge. The process entails sending a substantial amount of data, which consumes a significant amount of bandwidth. Consequently, compressing the transmitted image becomes essential to reduce the required bandwidth. The aim of this paper is to examine and analyse the wireless transmission of a compressed image via Discrete Cosine Transform (DCT‐OFDMA). A comparison is made with Discrete Fourier Transform (DFT‐OFDMA), across various subcarrier mapping schemes (localized and inter‐leaved), and different modulation schemes (16 Quadrature Amplitude Modulation (16QAM) and Quadrature Phase Shift Keying (QPSK)) using vehicular A, Stanford University Interim (SUI3), and uniform channel models. To evaluate the performance of the system, the minimum Signal‐to‐Noise Ratio (SNR) necessary to recover the transmitted compressed image is calculated. This work considers nine standard compression techniques. The results are carried out using the MATLAB simulator. According to the simulation results, the minimum SNR required to recover the transmitted compressed image was found to be 19 dB. This result was achieved when using Discrete Cosine Transform‐Loaclized‐Orthogonal Frequency Division Multiplexing Access (DCT‐LOFDMA) with QPSK modulation and set partitioning in hierarchical trees (SPIHT) compression method over the SUI3 channel model. Moreover, it was observed that the DCT‐LOFDMA and DFT‐IOFDMA systems attained equal SNR while utilizing the SPIHT_3D compression technique and QPSK modulation on the SUI3 channel model. Overall, the results suggest that the performance of DCT‐based localized OFDMA is somewhat superior to DFT‐based localized OFDMA, particularly when utilizing the SUI3 channel model and the QPSK modulation scheme. Therefore, it is feasible to transmit and receive a compressed image effectively over an OFDMA system with DCT.

Towards Globally Optimal Design of Multipliers for FPGAs

The design of a multiplier typically consists of three steps: (1) partial product generation, (2) compressor tree design and (3) the selection of the final adder. Conventionally, these three steps are performed consecutively. However, when targeting FPGAs, there are many possibilities in all three design steps that heavily influence each other. This proposal presents for the first time a holistic optimization, combining all three optimization steps yielding a minimum amount of look-up-tables (LUTs) while it can also guarantee the minimal number of (pipeline) stages. An ILP-formulation for the determination of a combined, globally optimal solution for the multiplier tiling, compressor tree generation and final adder selection is proposed. With globally optimal we mean that the best solution is found for a given set of sub-multipliers for partial product generation, compressors and final adder.This allows to improve the quality and evaluate the limitations of existing heuristic 3-step approaches. It is shown experimentally for the example of Xilinx FPGAs, that globally optimal solutions can be obtained for multiplier sizes of practical relevance, leading to significant LUT reductions. Additional packing density experiments show that a significantly larger number of multiplier instances can be mapped to the same device.

Massive Ultrasonic Data Compression Using Wavelet Packet Transformation Optimized by Convolutional Autoencoders.

Ultrasonic signal acquisition platforms generate considerable amounts of data to be stored and processed, especially when multichannel scanning or beamforming is employed. Reducing the mass storage and allowing high-speed data transmissions necessitate the compression of ultrasonic data into a representation with fewer bits. High compression accuracy is crucial in many applications, such as ultrasonic medical imaging and nondestructive testing (NDT). In this study, we present learning models for massive ultrasonic data compression on the order of megabytes. A common and highly efficient compression method for ultrasonic data is signal decomposition and subband elimination using wavelet packet transformation (WPT). We designed an algorithm for finding the wavelet kernel that provides maximum energy compaction and the optimal subband decomposition tree structure for a given ultrasonic signal. Furthermore, the WPT convolutional autoencoder (WPTCAE) compression algorithm is proposed based on the WPT compression tree structure and the use of machine learning for estimating the optimal kernel. To further improve the compression accuracy, an autoencoder (AE) is incorporated into the WPTCAE model to build a hybrid model. The performance of the WPTCAE compression model is examined and benchmarked against other compression algorithms using ultrasonic radio frequency (RF) datasets acquired in NDT and medical imaging applications. The experimental results clearly show that the WPTCAE compression model provides improved compression ratios while maintaining high signal fidelity. The proposed learning models can achieve a compression accuracy of 98% by using only 6% of the original data.

A Super-Resolution Data Processing for Automatic Modulation Classification Based on Tree Compression Networks

Automatic modulation classification (AMC) algorithms play a vital role in modern non-cooperative communication systems and are widely used for malicious attack analysis and reliable communication. Our research confirms that reducing the negative impact of few-shot learning and computational complexity is key to implementing the AMC algorithm on edge intelligence devices. This paper proposes a novel super-resolution (SR) data processing method, which is based on a tree compression network (TCNet), aiming to improve the accuracy and reduce the complexity of the few-shot learning AMC algorithm. Firstly, the SR data processing method is used for data augmentation where the number of examples is insufficient. Additionally, the TCNet is proposed to process SR data based on the compression network and the tree classification strategy. The compression network is employed to reduce model complexity, and the tree classification strategy improves classification accuracy. Lastly, the implementation of lightweight TCNet subnet will facilitate deployment on edge devices with limited computing power. The simulation results show that the proposed TCNet achieved a maximum accuracy of more than 91.98%. It is shown by processing fewer dataset examples on two well-known datasets, that TCNet outperforms previous approaches by offering improved classification accuracy and less complexity.

Hardware Implementation Of ECG Signal Compression Using SPIHT

Cardiovascular disorder is a primary cause of mortality throughout the world in both developed and underdeveloped countries. Continuous cardiac monitoring enables clinicians to identify arrhythmias and other heart conditions. Tele-cardiology introduces remote monitoring devices for tracking the cardiac activity of the patients. The large volume of Electrocardiogram (ECG) data needs to be stored, processed and transmitted by these portable health care devices. The implementation of ECG compression in hardware platform is crucial for continuous health monitoring applications. The aim of this work is to implement field programmable gate array based set partitioning in hierarchical trees-based electrocardiogram compression. Discrete wavelet transform method is employed to break up the signal into sub bands. The transformed coefficients after discrete wavelet transform are passed through dead zone quantization which rejects low magnitude values of transformed coefficients lying around zero. These quantized coefficients are then encoded by lossless set partitioning used in hierarchical trees compression approach. The introduction of dead zone quantization in the proposed technique is found to be effective and yields an increased compression ratio of 10.33 with decreased distortion value of 1.04 percent for ECG record 117 of MIT-BIH arrhythmia database.

A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree

Binarized neural networks (BNNs) and batch normalization (BN) have already become typical techniques in artificial intelligence today. Unfortunately, the massive accumulation and multiplication in BNN models bring challenges to field-programmable gate array (FPGA) implementations, because complex arithmetics in BN consume too much computing resources. To relax FPGA resource limitations and speed up the computing process, we propose a BNN accelerator architecture based on consolidation compressed tree scheme by combining both XNOR and accumulation operation of the low bit into a systematic one. During the compression process, we adopt 0-padding (not ±1) to achieve no-accuracy-loss from software modeling to hardware implementation. Moreover, we introduce shift-addition-BN free binarization technique to shorten the delay path and optimize on-chip storage. To sum up, we drastically cut down the hardware consumption while maintaining great speed performance with the same model complexity as the previous design. We evaluate our accelerator on MNIST and CIFAR-10 dataset and implement the whole system on the ARTIX-7 100T FPGA with speed performance of 2052.65 GOP/s and area efficiency of 70.15 GOPS/KLUT.

Parallel Frequent Subtrees Mining Method by an Effective Edge Division Strategy

Most data with a complicated structure can be represented by a tree structure. Parallel processing is essential to mining frequent subtrees from massive data in a timely manner. However, only a few algorithms could be transplanted to a parallel framework. A new parallel algorithm is proposed to mine frequent subtrees by grouping strategy (GS) and edge division strategy (EDS). The main idea of GS is dividing edges according to different intervals and then dividing subtrees consisting of the edges in different intervals to their corresponding groups. Besides, the compression stage in mining is optimized by avoiding all candidate subtrees of a compression tree, which reduces the mining time on the nodes. Load balancing can improve the performance of parallel computing. An effective EDS is proposed to achieve load balancing. EDS divides the edges with different frequencies into different intervals reasonably, which directly affects the task amount in each computing node. Experiments demonstrate that the proposed algorithm can implement parallel mining, and it outperforms other compared methods on load balancing and speedup.

A Low Power High Speed Accuracy Controllable Approximate Multiplier Design

Abstract: For energy effective and high performance design, the low power VLSI circuit is used. Multiplier is an essential part of low power VLSI design, since the effectiveness of the digital signal processor depends upon the multiplier. In multiplier circuit, utmost of the power is dissipated across in full adder circuits. Multiplication is one of the important process in microprocessor and there will be a lot of delay because of array multiplier, which can be compressed with the help of the column compressor approach. It uses a selection of half adders, full adders and compressors to sum the partial products in stages until two numbers are left. An 8 * 8 and 16 * 16 bit multiplier design is executed by assigning the adder and compressor. Partial product totality is the speed limiting operation in multiplication due to the propagation detention in adder networks. In order to reduce the propagation detention, compressors are introduced. Compressors calculate the sum and carry at each position concurrently. The attendant carry is added with a advanced significant sum bit in the coming stage. This is continued until the final product is generated. The partial product tree of the multiplier is estimated by the proposed tree compressor ( High Speed Compressor, Dual Stage Compressor, Exact Compressor). Keywords: Partial Products, Half Adder, Full Adder, High Speed Compressor, Dual Stage Compressor, Exact Compressor.

Lossless Compression of Semi-Ordered Trees

In this paper, authors are interested in the problem of lossless compression of unlabeled semi-ordered trees. Semi-ordered trees are a class of trees that present an order between some sibling while some other sibling are unordered. They offer a wide possibility of applications especially for the representation of plants architecture. Authors show that these trees present remarkable compression properties covering those of ordered and unordered trees. To illustrate this approach, authors apply these notions to a particular class of semi-ordered trees which is the most studied branching structure particularly for a botanical motivation, namely axial trees.

A single‐phase algorithm for mining high utility itemsets using compressed tree structures

Mining high utility itemsets (HUIs) from transaction databases considers such factors as the unit profit and quantity of purchased items. Two-phase tree-based algorithms transform a database into compressed tree structures and generate candidate patterns through a recursive pattern-growth procedure. This procedure requires a lot of memory and time to construct conditional pattern trees. To address this issue, this study employs two compressed tree structures, namely, Utility Count Tree and String Utility Tree, to enumerate valid patterns and thus promote fast utility computation. Furthermore, the study presents an algorithm called single-phase utility computation (SPUC) that leverages these two tree structures to mine HUIs in a single phase by incorporating novel pruning strategies. Experiments conducted on both real and synthetic datasets demonstrate the superior performance of SPUC compared with IHUP, UP-Growth, and UP-Growth+ algorithms.