Compressive Contact Etch Stop Layer Research Articles

Layout Study of Strained Ge-Based pMOSFETs Integrated With S/D GeSn Alloy and CESL by Using Process-Oriented Stress Simulations

The stress distributions and induced mobility gain in germanium (Ge)-based p-type MOSFETs (pMOSFETs) with an extended channel width are estimated in this paper. Several tin (Sn) concentrations of group-IV semiconductor GeSn alloys integrated with a compressive contact etching stop layer (CESL) are logically analyzed to evaluate the stress impact that results from the high lattice mismatch of embedded GeSn alloys on narrow device channels. Analytic results show that the stress intensity and corresponding mobility gain are enhanced by increasing the Sn concentration in the embedded source/drain GeSn stressors. By contrast, the performance variation of the short-channel Ge-based pMOSFET is strongly dominated by the extended width when the CESL covers the entire device. A mobility gain of up to ~124.07% is achieved for the 22-nm pMOSFET when a 100-nm extended width is considered. Moreover, the entire stress responses of high- ${k}$ /metal gate-last procedure combined with the following CESL deposition are investigated. Analytic results reveal that the stress relaxation along the channel height direction occurs after the poly gate etch process. Consequently, the adoption of a stressed CESL is demonstrated to be an effective approach to remedy the device mobility gain by stress improvement on the channel height direction.

Succeeded Foundation Effect of Stretched Gate and SiGe Array Diffusion Zones on Film-Type Strained Silicon pMOSFETs

AbstractIt has demonstrated to exploit various layout effects of advanced strained engineering to enhanced the performance of nano-scaled transistors. In actual fabrications, the gate framework usually protrudes out to the channel area even over the spuriously diffused active region, over the soft shallow trench isolation region. The foregoing device feature is interesting and critical when enhancing and managing mobility gain are taken into account by used mechanics and induced strained silicon technology in narrow scale channel widths devices. Thus, a silicon-based 22 nm p-type MOSFET combined stressors of a source/drain Si75Ge25 alloy and a -2 GPa compressive contact etch stop layer with different protrudent gate widths to investigate this issue. The fabricated oriented stress simulation extracted stress component within the device channel to estimate and analyze the performance of mobility gain and stress contours for the concerned nanoscale device.

Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET using trench-based structure

A stress modulation technology using a trench-based structure for strained NMOSFET is reported in this paper. With this technology, NMOSFET can be improved by a compressive contact etch stop layer (CESL), whereas the traditional CESL-strained NMOSFET requires a tensile one. To confirm this idea, a 95-nm-gate device with a −2.5 GPa strained CESL is simulated to investigate the effects of the trench-based structure on channel stress. It is demonstrated that the average longitudinal channel stress is transformed from −333 into 256 MPa, which leads to a significant improvement of the device's I–V performance. For strained CMOS, this approach provides a potential alternative besides dual stress liner technology.

Effects of extended poly gate on the performance of strained P-type metal-oxide-semiconductor field-effect transistors with a narrow channel width

The layout patterns of nano-scale devices have significant impacts on device performance when an increase in operating velocity is considered. Thus, advanced strain engineering of metal-oxide-semiconductor field-effect transistors (MOSFETs) is necessary when highly scaled gate lengths are employed. The foregoing mechanical effects are observable when a device with a narrow channel width is utilized. However, when a device integrated with an extended poly gate is scaled down to several hundreds of nanometers, the induced stress contours of the channel region and corresponding mobility gain become troublesome and must be resolved.This study investigates the mechanical impacts of extended gate widths on the mobility gains of p-type MOSFETs. The selected MOSFET has a SiGe stressor embedded in its source and drain regions, as well as a compressive contact etch stop layer. Three-dimensional finite element simulation is performed to emulate the stress contour within the Si channel and estimate the related mobility gain. Sensitivity analyses of the simulation results using factorial designs and response surface methodology indicate that stresses within the Si channel are induced by a bending force determined by the extension of the poly width. A significant enhancement in mobility gain is found when an extended poly width combined with proper arrangements of the device geometry is applied.

Impact of stress induced by stressors on hot carrier reliability of strained nMOSFETs

In this study, the nMOSFETs with contact-etch-stop-layer (CESL) stressor and SiGe channel have been fabricated with a modified 90 nm technology. The performance of nMOSFETs has been measured. And the hot carrier reliability of the SiGe-channeled nMOSFETs with various CESL nitride layers has also been extensively studied. In addition, the impact of stress induced by CESL stressor and SiGe-channel on hot-carrier reliability of the strained nMOSFETs has been analysed through experimental investigation. The shift in threshold voltage (Δ V th ) vs. stress time ( t ) under different stress temperatures was measured. Furthermore, according to the reliability results, both the interface states ( N it ) and oxide trapped charges ( N ot ) increased after hot-carrier stress. With regard to the hot-carrier reliability, for all stress conditions the degradation of strained nMOSFETs with compressive CESL stressor is more serious than the degradation of those with tensile CESL stressors. The nMOSFET devices with tensile CESL have better performance and hot-carrier reliability than those with compressive CESL. Moreover, it is suggested that the CESL-induced damages ( N it ) located at the interface between gate dielectric and underlying channel be responsible for the hot-carrier reliability.

Strain Engineering of Nanoscale Si P-Type Metal-Oxide-Semiconductor Field-Effect Transistor Devices with SiGe Alloy Integrated with Contact-Etch-Stop Layer Stressors

Strained-silicon (Si) has been incorporated into a leading nanoscale logic technology. By means of silicon-germanium (SiGe) alloy stressor embedded in source and drain (S/D) region, the performance of P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) is effectively enhanced. However, when a compressive contact-etch-stop layer (CESL) is combined, the stress interaction and relative impacts of SiGe stressor integrated with CESL on mobility enhancement has been little reported. Therefore, the research performs a three dimensional (3D) stress simulation evaluation based on finite element method (FEM) for PMOSFETs with S/D SiGe stressor and compressive CESL. The proposed simulation methodology is validated as compared with other technological literatures. In additions, the gate width dependency is systematically discussed to explore the stress effects on devices. The analysis results indicate that a -2.6 GPa CESL would continue boosting the stress magnitude on Si channel region except for a gate width smaller than 50 nm. The results are useful for nanoscale transistor while selecting a proper CESL in the manufacturing processes of advanced logic technologies.

Impact of Highly Compressive Interlayer-Dielectric-$ \hbox{SiN}_{x}$ Stressing Layer on $\hbox{1}/f$ Noise and Reliability of SiGe-Channel pMOSFETs

The 1/f noise and reliability of SiGe-channel pMOSFETs with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , stressing layer have been studied in this letter. The SiGe-channel devices with a highly compressive CESL layer have higher drain current and lower 1/f noise than the conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the highly compressive CESL layer. By examining the effective oxide-trap densities under hot-carrier instability stress, we find that the incorporated hydrogen in gate oxide during CESL layer deposition may play an important role on the 1/f noise and device reliability.

External Stresses on Tensile and Compressive Contact Etching Stop Layer SOI MOSFETs

A n-/p-SOI MOSFET capped with a standard 380 Å tensile contact etching stop layer (CESL) and a 700 Å compressive CESL and with SOI thicknesses of 500/700/900 Å were measured in this paper. Additionally, external uniaxial compressive stresses with both longitudinal and transverse directions up to 45.7 MPa were applied on the devices sitting on cut silicon bars. Temperature-induced threshold voltage shifts and input-referred voltage noise showed bigger depletion zones and higher noise in the device with compressive CESL. The measurement suggests that both SOI thickness and CESL type are critical for mobility enhancement or degradation of devices. The capped compressive CESL for n-/p-SOI MOSFETs demonstrated higher piezoresistive coefficient compared with tensile CESL under external uniaxial compressive stresses for both longitudinal and transverse configurations.

PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD- $\hbox{SiN}_{x}$ Stressing Layer

In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been successfully fabricated. The performance improvements of devices with a gate length (Lg )of down to 40 nm were studied. For long-channel SiGe-channel PMOS, the mobility is at least 50% higher than that of the conventional bulk-Si PMOS. Moreover, compared to the conventional short-channel SiGe-channel devices, the highly compressive CESL stressor shows 32% current gain for Lg = 40 nm PMOS with the thinnest 9 A Si-cap. Therefore, integrating the stressed CESL technique into the SiGe-channel structure is an efficient method for improving PMOS device performance.

New Negative-Bias-Temperature-Instability Improvement Using Buffer Layer under Highly Compressive Contact Etch Stop Layer for 45-nm-Node Complementary Metal–Oxide–Semiconductor and Beyond

A remarkable 50% drive current enhancement for p-type metal–oxide–semiconductor field-effect-transistors (pMOSFETs) using a highly compressive SiN contact etch stop layer (CESL) has been successfully demonstrated. In this study, we also first proposed that applying a modulated buffer layer prior to the highly compressive CESL could significantly improving negative-bias-temperature-instability (NBTI) and time-dependent-dielectric-breakdown (TDDB) degradation of pMOSFETs using compressive CESL. Without adversely impact the significant drive current enhancement of pMOSFETs, this thin modulated buffer layer can improve the NBTI lifetime of core pMOSFETs by over two orders of magnitude. Instead of the complex and high-costly SiGe refill scheme, this highly compressive CESL layer with a thin modulated buffer layer successfully demonstrates a better candidate for pMOSFETs drive current enhancement of 45-nm-node CMOS and beyond.

Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior

In this letter, we investigate the effects of process-induced strain on negative bias temperature instability (NBTI) by performing a comparative study of devices with and without process-induced strain for poly-Si/SiON gate stacks. Devices with SiGe source/drain with different processing sequences and devices with a combination of SiGe S/D and compressive contact etch stop layer (CESL) were studied and compared to reference devices. We decouple the effect of processing conditions in order to ensure a correct interpretation of the results. In contrast with the previous reports, which did not consider the impact of processing conditions, this letter demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with a process-induced strain. In addition, we performed an Arrhenius study showing similar activation energies for devices with and without process-induced strain, suggesting similar degradation mechanism. The results indicate that process-induced strain does not create favorable conditions for additional interface state creation

NBTI Study on PMOS Devices with TiN/HfO2 Gate Stack and Process Induced Strain

We investigate the effect of process induced strain on Negative Bias Temperature Instability (NBTI) for devices with TiN/HfO2 gate stacks. Devices with compressive Contact Etch Stop Layer (CESL), SiGe Source/Drain, and devices with a combination of both SiGe and CESL were studied and compared to reference devices. We decouple the effect of processing conditions in order to assure correct interpretation of the results. Our study demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with process induced strain. In addition, we performed an Arrhenius study showing that Si-H bonds under strain exhibit similar activation energies as Si-H bonds without strain, indicating that no favorable conditions for interface states generation are created by the strain.

PMOSFET with 200% mobility enhancement induced by multiple stressors

Recessed Si/sub 0.8/Ge/sub 0.2/ source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported process-induced hole mobility enhancement to the authors' knowledge. This letter demonstrates that a drive-current improvement from recessed Si/sub 0.8/Ge/sub 0.2/ plus the compressive nitride layer are in fact additive. Furthermore, it shows that the mobility enhancement is a superlinear function of stress, leading to larger than additive gains in the drive current when combining several stress sources.