Jitter Components Research Articles

Modeling CMOS Ring Oscillator Performance<newline/> as a Randomness Source

<?Pub Dtl=""?> In order to maximize randomness of CMOS Ring Oscillators (RO) used in Random Number Generators (RNG), possibility of weak inversion operation of CMOS transistors is investigated. To predict weak inversion noise performance of RO, phase noise and jitter models of a CMOS RO in weak inversion operating region are obtained. Differential Ring Oscillator (DRO) and Inverter-based Ring Oscillator (IbRO) cases are both investigated. For each case, the model covers the flicker and the white noise component of phase noise and jitter. The derived models are verified by measurement results. 0.25 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu$</tex></formula> m standard CMOS process has been used with a supply voltage of 0.7 V for DRO and 0.5 V for IbRO. Furthermore, phase noise and jitter behavior of a CMOS RO in strong and weak inversion region are compared through analytical models, simulations, and measurements. Even though white noise component of phase noise uses two different models for weak and strong inversion regions of operation, these two models exhibit continuity. Flicker noise component in weak inversion is much lower than the one in strong inversion, which also reduces the corner frequency. For a fair comparison of randomness performances, a randomness parameter is defined and randomness equations are derived for each case.

Clock jitter generator with picoseconds resolution

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220 MHz, a jitter with 4 ps resolution can be injected.

Aero-optical jitter estimation using higher-order wavefronts

Wavefront measurements from wind tunnel or flight testing of an optical system are affected by jitter sources due to the measurement platform, system vibrations, or aero-mechanical buffeting. Depending on the nature of the testing, the wavefront jitter will be a composite of several effects, one of which is the aero-optical jitter; i.e., the wavefront tilt due to random air density fluctuations. To isolate the aero-optical jitter component from recent testing, we have developed an estimation technique that uses only higher-order wavefront measurements to determine the jitter. By analogy with work done previously with free-stream turbulence, we have developed a minimum mean-square error estimator using higher-order wavefront modes to compute the current-frame tilt components through a linear operation. The estimator is determined from computational fluid dynamics evaluation of aero-optical disturbances, but does not depend on the strength of such disturbances. Applying this technique to turret flight test data, we found aero-optical jitter to be 7.7±0.8 μrad and to scale with (ρ/ρ SL )M 2 (∼1 μrad in the actual test cases examined). The half-power point of the aero-optical jitter variance was found to be ∼2u ∞ /D t and to roll off in temporal frequency with a power law between f −11/3 and f −10/3 .

Note: Optical trigger device with sub-picosecond timing jitter and stability

We are presenting the design, construction, and overall performance of the optical trigger device. This device generates an electrical signal synchronously to the detected ultra-short optical pulse. The device was designed for application in satellite laser ranging and laser time transfer experiments, time correlated photon counting and similar experiments, where picosecond timing resolution and detection delay stability are required. It consists of the ultrafast optical detector, signal discriminator, output pulse forming circuit, and output driver circuits. It was constructed as a single compact device to optimize their matching and maintain stability. The detector consists of an avalanche photodiode--both silicon and germanium types may be used to cover the wavelength range of 350-1550 nm. The analogue signal of this photodiode is sensed by the ultrafast comparator with 8 GHz bandwidth. The ps clock distribution circuit is used to generate the fast rise/fall time output pulses of pre-set length. The trigger device timing performance is excellent: the random component of the timing jitter is typically 880 fs, the temperature dependence of the detection delay was measured to be 370 fs/K. The systematic error contribution depends on the laser used and its stability. The sub-ps values have been obtained for various laser sources.

Programmable jitter generator

As CMOS technology has scaled, supply voltage have dropped, chip power consumption has increased, and clock frequency/data rates increase effects of jitter become critical and jitter budget get tighter. Knowing how to inject/isolate jitter components with time–convolution/correlation will enhance designer ability to determine and locate the root causes. Jitter can be decomposed into several subcomponents, each having specific sets of characteristics and root causes. This paper begins with a short review of jitter fundamentals. The jitter injection technique gives test engineers an insight into how jitter components interact. In the rest of the paper a global hardware structure of a jitter generator, which uses digital techniques, based on a voltage controlled delay line is described. A Xilinx xc3s500e–5fg320 FPGA chip is used to validate this design. The programmable jitter generator can be used in jitter tolerance test for computer system and jitter transfer function measurement in communication systems.

Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits

Accurate measurement of aperture jitter for high-speed data converters is a difficult problem, since aperture jitter should be precisely separated from other jitter components as well as additive noise. This problem results in low test accuracy and high-yield loss. This paper presents a novel methodology for accurately predicting aperture jitter using a cost-effective loopback methodology. By using an efficient spectral loopback scheme, aperture jitter is precisely separated from input jitter and clock jitter as well as additive noise present in the DUT. Hardware measurement results show that this approach can be effectively used to predict the aperture jitter of a DUT, with an 89% reduction in the prediction error compared with previous approaches.

Analysis of jitter influence in fast frequency measurements

This paper presents a theoretical analysis of possible jitter impact in application of numeric criterion for fast measurement of frequency by coincidence principle. The primary goal is the generation of a signal containing a known amount of each jitter components. This signal was used for testing signals with regular pulse trains. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining different kinds of jitter are modeled, simulated and evaluated. Jitter model simulation in Matlab is utilized to show the independence of frequency measurement results on the total jitter present in the reference and desired pulse trains independently. A good agreement between previously introduced theory of fast measurement of frequency and simulation in jitter presence is verified; these results allows to engineers use the numeric criterion for fast measurement of frequency in spite to interactions among jitter components in various applications for frequency domain sensors.

Binaural Stimulation In Neural Auditory Prostheses Or Hearing Aids

The present invention discloses of binaural stimulation in a neural auditory prosthesis. Binaural acoustic signals are generated that represent sound associated with a user's left and right ears respectively. Based on the binaural acoustic signals, corresponding binaural stimulation signals are generated for electrical stimulation of auditory nerve tissue of the user, wherein the binaural stimulation signals each include a fine structure component with periodic characteristics and interaural time difference (ITD) information. A phase jitter component is added to the binaural stimulation signals to reduce the periodic characteristics of the fine structure component while preserving the interaural time difference (ITD) information.

Accurate and Efficient BER Calculation by Statistical Simulation Based on Physical Transmit Jitter Model

Statistical analysis provides an efficient alternative to the traditional Monte Carlo simulation for extremely low BER calculation in high speed serial link designs. Transmitter (TX) jitter posts a huge challenge in statistical simulation due to its pattern- and time-dependent nature and the resulting computational complexity. This paper presents a fast yet rigorous approach to calculate TX jitter in statistical simulation based on physical models of various jitter components. The approach accurately captures effects of uncorrelated random jitters, jitter amplification by channel dispersion, frequency dependency of periodic jitter and data duty-cycle-distortion.

A spread-spectrum clock generator for 6-Gbps Serial ATA transceiver

A transmitter-side spread-spectrum clock generator (TX-SSCG) with a second-order ΔΣ modulator is proposed for a 6-Gbps Serial ATA. Mixed-mode simulations show that a second-order ΔΣ modulator in TX-SSCG reduces the random jitter component of the receiver-side tracking skew through quantization noise shaping. Deterministic jitter is reduced with the loop bandwidth of RXPLL. A 0.13-µm CMOS prototype chip shows that the transceiver operates at 6Gbps over an 8-m SATA cable in TX-SSCG on and off. With TX-SSCG on, the spectrum is down-spread with 11.7-dB peak reduction and 5000-ppm spread amount.

A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control

By using the data timing control at transmitter (TX) side, the crosstalk-induced jitter (CIJ) is compensated in a 4 Gbps single-ended transmitter with 3-bit parallel data. CIJ is induced by the propagation velocity difference between the signal modes of parallel transmission lines. This velocity difference was compensated for by sending data early or late at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 mum CMOS process. The parallel transmission lines used in the measurements are 4-inch long, have the minimum-allowed spacing between transmission lines to maximize CIJ. CIJ was measured to be reduced by about 50% from 53 ps to 27 ps at 4 Gbps excluding the random jitter component of 72 ps added at the TX side. The scheme used in this work can be expanded to more than three transmission lines.

A Better Method than Tail-fitting Algorithm for Jitter Separation Based on Gaussian Mixture Model

Jitter is roughly defined as the timing shaking of the square waveforms output from phase locked loops. It consists of two parts: deterministic jitter and random jitter. Separating and identifying each jitter component are important in understanding the root cause of jitter and further in improving on phase locked loop design. A popular method for jitter separation is so-called Tail-fitting Algorithm. A better method than Tail-fitting Algorithm for separating deterministic jitter (DJ) and random jitter (RJ) from total jitter (TJ) is presented in this Letter. The new method targets directly on the original total jitter series, instead of the histogram. Histogram is dependent on bin number and is uncertain, but is inappropriately selected as the starting point of Tail-Fitting algorithm. Our method is based on Gaussian mixture model (GMM). The mathematical relationship between this model and the quantities of DJ and RJ is established. The concept of kurtosis is used to determine the order of GMM, thereby rendering our method fully automatic, highly efficient. Our method circumvents the most cumbersome difficulty in tail identification of Tail-Fitting Algorithm, because tails and peaks of the histogram, even after being filtered, are fundamentally ambiguously defined, both theoretically and practically. Our method also bypasses the problem of initial value selection.

A Clock-Less Jitter Spectral Analysis Technique

In this paper, we propose a method for extracting the spectral information of a multigigahertz jittery signal without using an ideal reference clock. This method utilizes existing on-chip single-shot period measurement techniques to measure single periods of a multigigahertz signal for analysis. Utilizing the same sampling and measuring principle, we propose another less computationally intensive method, based on the derivative principle, to extract only the random jitter component of the signal. To perform analysis on higher frequency signals, both methods are extended to measures multiple signal periods, instead of a single period, at each sampling. These methods do not require an ideal sampling clock, nor any additional measurement beyond existing techniques. Experimental results based on simulation show that these methods can accurately estimate the sinusoidal and random jitters of a multigigahertz signal. Extracted values can be used for estimating the bit-error rate of serial communication systems.

Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels

This paper presents a novel modeling analysis of jitter as applicable to testing of serial data channels. Jitter is analyzed by considering separate and combined components. The primary goal is the generation of a signal containing a known amount of each jitter component. This signal can then be used for testing high speed serial data channels. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining them are modeled, simulated and evaluated. Model simulation using Matlab is utilized to show the unique features of the components when they are combined into different injection sequences for producing the total jitter. Sequence dependency is investigated in depth and the validity of superposition of jitter components for typical values is confirmed. A good agreement between theory and simulation is verified; these results allow test engineers to have an insight into the interactions among jitter components in serial data channels.

Bandpass filtering of high-speed forwarded clocks

Bandpass channel filtering is shown to attenuate both random and determinstic jitter components in high frequency clock signals. A fully differential, tunable LC bandpass filter is developed and employed to reduce Gaussian and sinusoidal distributed jitter and duty cycle distortion.

Double-frequency jitter figures in master–slave PLL networks

The main strategy used for distributing clock information in synchronous telecommunication networks is the master–slave. A particular node (master) provides the precise clock signals that are sent to the other nodes (slaves), which recover phase and frequency information by using phase-locked loops (PLLs). In spite of PLLs being equipped with low-pass filters, the recovered clock signals always contain second harmonic components that appear as a deterministic component of the whole phase jitter. Here, we study how the amplitude of this double-frequency jitter depends on the PLL parameters and delays. Chain and star topologies are considered with slave PLLs equipped with the most usual types of first-order low-pass filter. For both topologies, numerical simulations show that this kind of jitter depends on the position of the node in the chain or star being slightly dependent on the number of nodes.

Modeling and analysis of inter-symbol interference (ISI) jitter

This paper presents a novel modeling and analysis of inter-symbol interference (ISI)jitter in serial data channels either between chips or on chip. The simulation results show that ISI jitter is dependent on pole location, settling time, and damping ratio of the data serial channel. Based on the proposed ISI jitter model, the effect of the ISI jitter on other jitter components is illustrated along with realistic simulation results.

Low-complexity adaptive equalization for high-speed chip-to-chip communication paths by zero-forcing of jitter components

In this letter, we show how a prefilter can be automatically adapted to open the data eye in a nonreturn to zero transmission system using only two binary samples per bit. Although the equalizer primarily aims to minimize timing jitter with a zero-forcing criterion, this equalization method also results in nearly optimum vertical eye opening, thereby causing very little overhead in complexity and power consumption. The target application is low-power high-speed serial links to transfer data between chips over a printed circuit board

Jitter Analysis for Land/Groove Phase Change Disk

A 22 GB optical video recording system with an objective lens of high numerical aperture (NA), a blue laser and a thin cover layer is proposed. We classify the jitter which increased by aberrations into three components for this system. We analyze the dependence of jitter components on the groove depth in detail. Furthermore, we confirm advantages of the limit equalizer (Limit-EQ) and the two-dimensional adaptive equalizer for the land/groove (L/G) phase change disk.

KALP: a Kalman filter-based adaptive clock method with low-pass prefiltering for packet networks use

We consider the issue of source clock frequency recovery in packet networks and propose a new adaptive clock method based on the Kalman filter (KF) with low-pass prefiltering-KALP (Kalman filter-based Adaptive clock method with Low-pass Prefiltering) in short. Noting that because of the difficulty in modeling as well as the nonwhite Gaussian nature of the packet jitter most existing adaptive clock methods could not successfully adopt the Kalman filter, we take a new approach to packet jitter modeling for the KALP. We model the packet jitter not directly but after shaping its characteristics by low-pass prefiltering. This low-pass prefiltering is an important arrangement as it helps to convert the packet jitter into a low-pass signal regardless of its original characteristics, thus enabling to model the prefiltered packet jitter using a simple first-order autoregressive [AR(1)] process. The low-pass prefilter should be carefully selected not to lose the timing information while prefiltering, and the moving averager employed in this paper satisfies this requirement. The AR(1)-modeled jitter component is amenable to the KF-based processing, which in this case becomes an optimal estimator. The design parameters including the initial conditions of the KF and AR(1) parameters can be determined based on the service clock specification and packet interarrival times during the delay smoothing process. We carry out various simulations to compare the performance of the KALP with the existing buffer-based adaptive clock method and demonstrate that the KALP can significantly reduce the fluctuation in the level of receiving buffer as well as the time to recover the source clock frequency.