Complex Arithmetic Operations Research Articles

Complex-valued multi-frequency electrical impedance tomography based on deep neural networks

The utilization of multi-frequency electrical impedance tomography (mfEIT), a non-invasive imaging technique, allows for the visualization of the conductivity distribution in biological tissues across different frequencies. However, the analysis of phase angle information within complex impedance remains a challenge, as most existing deep learning-based mfEIT algorithms are limited to real number processing. To mitigate this limitation, this study proposes a comlex reconstruction method which is inspired by the idea of combining deep learning with traditional reconstruction algorithm. It uses a spare Bayesian learning algorithm in the preprocessing stage that can perform complex arithmetic operations, and fully learns and makes use of the correlation between the real and imaginary parts to reconstruc the distribution of complex-valued conductivity in the measurement area. After that, an altered UNet network is used to further optimize the pre-reconstruction outcomes. The experimental outcomes validate the efficacy of the proposed algorithm in accurately reconstructing the complex-valued conductivity distributions of diverse biological tissues, such as potato and pig kidney, across different frequencies. Furthermore, the algorithm exhibits exceptional performance in mitigating the presence of image artifacts during the reconstruction process.

FPGA Based Accelerator for Implementation of Large Integer Polynomials

A 13-bit multiplier is implemented on the Artix- 7 100T FPGA using a divide-and-conquer algorithm. The designis coded in SystemVerilog, leveraging its powerful features for hardware description and synthesis. The divide-and-conquer approach breaks down the multiplication task into smaller sub- tasks, enhancing efficiency and reducing complexity. The FPGA’s high- performance capabilities, particularly on the Artix-7 100T board, make it well-suited for accelerating the computations involved. Additionally, Area Delay Product (ADP) tools are employed to evaluate the algorithm’s efficiency. This project aims to showcase the synergy between algorithmic design, hardware implementation, and FPGA capabilities, emphasizing the versa- tility of the Artix-7 100T FPGA in handling complex arithmetic operations.

Low-Rank Methods for Solving Discrete-Time Projected Lyapunov Equations

In this paper, we consider the numerical solution of large-scale discrete-time projected Lyapunov equations. We provide some reasonable extensions of the most frequently used low-rank iterative methods for linear matrix equations, such as the low-rank Smith method and the low-rank alternating-direction implicit (ADI) method. We also consider how to reduce complex arithmetic operations and storage when shift parameters are complex and propose a partially real version of the low-rank ADI method. Through two standard numerical examples from discrete-time descriptor systems, we will show that the proposed low-rank alternating-direction implicit method is efficient.

The date/delay effect in intertemporal choice: A combined fMRI and eye-tracking study.

Temporal discounting, the tendency to devalue future rewards as a function of delay until receipt, is influenced by time framing. Specifically, discount rates are shallower when the time at which the reward is received is presented as a date (date condition; e.g., June 8, 2023) rather than in delay units (delay condition; e.g., 30 days), which is commonly referred to as the date/delay effect. However, the cognitive and neural mechanisms of this effect are not well understood. Here, we examined the date/delay effect by analysing combined fMRI and eye-tracking data of N = 31 participants completing a temporal discounting task in both a delay and a date condition. The results confirmed the date/delay effect and revealed that the date condition led to higher fixation durations on time attributes and to higher activity in precuneus/PCC and angular gyrus, that is, areas previously associated with episodic thinking. Additionally, participants made more comparative eye movements in the date compared to the delay condition. A lower date/delay effect was associated with higher prefrontal activity in the date > delay contrast, suggesting that higher control or arithmetic operations may reduce the date/delay effect. Our findings are in line with hypotheses positing that the date condition is associated with differential time estimation and the use of more comparative as opposed to integrative choice strategies. Specifically, higher activity in memory-related brain areas suggests that the date condition leads to higher perceived proximity of delayed rewards, while higher frontal activity (middle/superior frontal gyrus, posterior medial frontal cortex, cingulate) in participants with a lower date/delay effect suggests that the effect is particularly pronounced in participants avoiding complex arithmetic operations in the date condition.

Design & Implementation of Approximate 7:2 Compressor Based 16-bit Dadda Multiplier using Verilog

Now a days the technology is growing day by day with faster rate. Particularly the usage of electronics is increasing in wide range of ways depending on their intended purpose and preferences. In this regard multipliers are playing a vital role because they allow us to perform complex arithmetic operations involving large numbers more efficiently. Instead of performing a series of addition or subtraction operations, a multiplier allows us to perform the operation in a single step within no time that is the challenge of today’s world. So in addition to being more efficient, multipliers also have practical applications in fields such as engineering, computer science, and cryptography also used , for example, in the design of digital circuits and in the encryption and decryption of data. Overall, multipliers playing an important role in mathematics and its applications and are essential tools for performing complex computations efficiently. Compressors play a vital role in realizing the high speed multipliers. In error resilient applications such as Image processing, Multimedia and Matrix multiplication the approximate computing is used, which provides meaningful results faster with lower power consumption. In previous work the compressors are designed using the full adders which provides accurate results. The 4:2 and 5:2 approximate compressors are then introduced with 18% delay reduction and ADP reduction up to 52%. Now the further work concentrated on the implementation of 7:2 Approximate Compressor based multiplier, to further enhance the performance of multipliers. The proposed design will be expected to provide maximum extent of reduction in area, delay or power consumption and achieves improvement in terms of speed as compared to the 4:2 and 5:2 compressor based approximate multiplier.

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory

This work presents BP-SCIM: a reconfigurable 8T static random access memory (SRAM) macro for bit-parallel searching and computing in-memory (CIM). The decoupled read/write ports of the employed 8T SRAM bit-cell eliminate read disturbance during search and CIM operations. BP-SCIM can support both in-memory Boolean logic and arithmetic operations. Novel CIM-friendly algorithms and peripheral circuits are proposed to reduce the latency of complex arithmetic operations such as multiplication and division. In addition, BP-SCIM can be configured as either a binary content-addressable memory (CAM) or a ternary CAM for fast searching. A 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 64 BP-SCIM test chip was implemented in 65-nm CMOS technology. The 8-bit addition and 8-bit multiplication operations can achieve the maximum energy efficiency of 3.11 TOPS/W and 0.17 TOPS/W, respectively at 0.7 V supply. For the binary CAM search operation, BP-SCIM can achieve the minimum energy consumption of 0.91 fJ/bit/search at 87 MHz and 0.8 V supply.

On the Practicality of the Analytical Solutions for all Third- and Fourth-Degree Algebraic Equations with Real Coefficients

In order to propose a deeper analysis of the general quartic equation with real coefficients, the analytical solutions for all cubic and quartic equations were reviewed here; then, it was found that there can only be one form of the resolvent cubic that satisfies the following two conditions at the same time: (1) Its discriminant is identical to the discriminant of the general quartic equation. (2) It has at least one positive real root whenever the general quartic equation is non-biquadratic. This unique special form of the resolvent cubic is defined here as the “Standard Form of the Resolvent Cubic”, which becomes relevant since it allows us to reveal the relationship between the nature of the roots of the general quartic equation and the nature of the roots of all the forms of the resolvent cubic. Finally, this new analysis is the basis for designing and programming efficient algorithms that analytically solve all algebraic equations of the fourth and lower degree with real coefficients, always avoiding the application of complex arithmetic operations, even when these equations have non-real complex roots.

Designing pair of nonlinear components of a block cipher over quaternion integers

&lt;abstract&gt; &lt;p&gt;In the field of cryptography, block ciphers are widely used to provide confidentiality and integrity of data. One of the key components of a block cipher is its nonlinear substitution function. In this paper, we propose a new design methodology for the nonlinear substitution function of a block cipher, based on the use of Quaternion integers (QI). Quaternions are an extension of complex numbers that allow for more complex arithmetic operations, which can enhance the security of the cipher. We demonstrate the effectiveness of our proposed design by implementing it in a block cipher and conducting extensive security analysis. Quaternion integers give pair of substitution boxes (S-boxes) after fixing parameters but other structures give only one S-box after fixing parameters. Our results show that the proposed design provides superior security compared to existing designs, two making on a promising approach for future cryptographic applications.&lt;/p&gt; &lt;/abstract&gt;

Simplifying Capacitive Sensor Readout Using a New Direct Interface Circuit

Direct interface circuits (DICs) are efficient for reading resistive, capacitive, or inductive sensors in a digital format. The simplest DICs consist of just a few passive elements that connect a digital processor (DP) to a sensor. When reading capacitive sensors, one or several calibration capacitors and/or several charging and discharging cycles are needed to make the estimation, and the result usually requires complex arithmetic operations. This article presents a new type of capacitive DIC that is simple in terms of hardware, needing only two resistors of known value and the DP in order to make the capacitance estimation. In addition, the reading method requires a single sensor charging and discharging cycle, which reduces acquisition time and power consumption. Two time measurements are taken during the discharge, which, through a linear transformation of their subtraction (using two constants stored in the DP), give the value of the capacitance. These arithmetic operations are easily implemented on any DP and consume fewer resources than the divisions required on other capacitive DICs. The design has been tested for a wide range of capacitances (from 100 pF to 561 nF), including the value of several capacitive sensors. The average relative error for the entire range is 0.41%, the linearity errors are below 0.3%, and the minimum signal-to-noise ratio (SNR) value is 64 dB.

A Complete Review of the General Quartic Equation with Real Coefficients and Multiple Roots

This paper presents a general analysis of all the quartic equations with real coefficients and multiple roots; this analysis revealed some unknown formulae to solve each kind of these equations and some precisions about the relation between these ones and the Resolvent Cubic; for example, it is well-known that any quartic equation has multiple roots whenever its Resolvent Cubic also has multiple roots; however, this analysis reveals that any non-biquadratic quartic equation and its Resolvent Cubic always have the same number of multiple roots; additionally, the four roots of any quartic equation with multiple roots are real whenever some specific forms of its Resolvent Cubic have three non-negative real roots. This analysis also proves that any method to solve third-degree equations is unnecessary to solve quartic equations with multiple roots, despite the existence of the Resolvent Cubic; finally, here is developed a generalized variation of the Ferrari Method and the Descartes Method, which help to avoid complex arithmetic operations during the resolution of any quartic equation with real coefficients, even though this equation has non-real roots; and a new, more simplified form of the discriminant of the quartic equations is also featured here.

High‐accuracy mean circuits design by manipulating correlation for stochastic computing

AbstractStochastic computing (SC) encodes numerical values into probabilistic binary bitstreams to enable complex arithmetic operations to be transformed into simple bit operations. Different operations can be performed through the same SC element by adjusting the correlation between bitstreams. In this work, two stochastic mean circuits (MCs) are proposed by manipulating positively and negatively correlated bitstreams, respectively named PCMC and NCMC, to improve computing accuracy, lower area, and power consumption. Furthermore, a general structure for MCs, denoted as GMC, is also proposed to generalize their design approach. Compared with the existing multiplexer (MUX)‐based stochastic MCs, the proposed circuits have approximately 50%, 59%, 61%, and 64% reduction in area, and 100×, 10×, 151×, and 12 × improvement in MSE, for 2‐, 3‐, 4‐, and 5‐input situations, respectively. With applications to edge detection and mean filtering, the proposed designs are superior to the existing counterparts in terms of accuracy and hardware cost.

Design and Implementation of Digital Beam Former Architecture for Phased Array Radar

This paper deals with the design and implementation of a digital beam former architecture which is developed for 4/8/12/16 element phased array radar. This technique employs a very high performance FPGA to handle large no of parallel complex arithmetic operations including digital down conversion and filtering. A 3MHz echo signal riding on an IF carrier of 60 MHz is under sampled at 50 MHz and down converted digitally to bring the spectrum to echo signal baseband. After suitable decimation filtering, the I and Q channels are multiplied with Recursive Least Squares based optimized complex weights to form partial beams. The prototype architecture employs techniques of pipelining and parallelism to generate multiple beams simultaneously from a 16 element array within 1 μsec. This can be extended to several number of arrays. The critical components employed in this design are eight 16 bit 125 MS/s ADCs and a very high performance state of the art Xilinx FPGA device Virtex-5 FX 130T having several on-chip resources and 150 MHz clock generators.

Peak and Valley Current Control for Cuk PFC Converter to Reduce Capacitance

Traditional power factor correction (PFC) converters usually employ a large electrolytic capacitor to ensure a stiff output voltage. However, the electrolytic capacitor is not expected in terms of the reliability and the size of the system. This article proposes a peak and valley current control for Cuk PFC converter to remove the bulky electrolytic capacitor. The proposed control is realized by a combination of analog and digital circuits. The analog circuits are used to accomplish the real-time comparison between the actual currents and their reference values. And the digital circuits are employed to deal with simple logical judgement. Different from the existing full digital control technique, which needs a high-quality digital signal processor (DSP) to process complex arithmetic operation, the proposed control concept even can only require a low performance microcontroller unit. Besides, the control delay is avoided. This article first analyzes the operation stages of the Cuk PFC converter. Then, design considerations of main circuit and control circuit are introduced. Finally, the experimental results from 200W Cuk PFC converter are presented to verify the effectiveness of the proposed control.

Solitary Wave Solutions of the (3+1)-dimensional Khokhlov–Zabolotskaya–Kuznetsov Equation by using the (G'/G,1/G)-Expansion Method

In this study, the (3+1)-dimensional Khokhlov-Zabolotskaya-Kuznetsov (KZK) equation, which is a mathematical model of non-absorption and dispersion in the non-linear medium, which sheds light on the sound beam phenomenon, which has a physically important place, is examined. In order to find the exact solution of this equation, an effective and reliable method, (G^'/G,1/G)-expansion method, is used among analytical methods. The purpose of this method is to obtain more than one traveling wave solution classes depending on the conditions of the λ parameter. These classes are categorized into hyperbolic, trigonometric, complex trigonometric and rational forms. The graphics of the solitary waves represented by these successfully obtained solution classes are presented as 2-dimensional, 3-dimensional and contours. This article makes use of ready-made package programs for complex arithmetic operations and graphic drawings.

A low‐error, memory‐based fast binary antilogarithmic converter

SummaryThe ever‐increasing need for high‐performance signal processing blocks in avionics, machine learning (ML), IoT, neural networks, etc., has made the logarithmic arithmetic's as the front runner in advanced processors. The complex arithmetic operations such as multiplication and division can be easily performed in the logarithmic domain as they become addition and subtraction operations, respectively. However, the challenge is to perform the logarithmic and anti‐logarithmic conversions and to optimize the trade‐off between hardware complexity and accuracy. In this work, we propose a 32‐bit antilogarithmic converter, for/using Mitchell's algorithm. The obtained results are corrected using the weighted average method. The correction terms are stored and selected using 32 × 8 ROM to decreases the computational speed and hardware complexity of the antilogarithmic converter. The proposed antilogarithmic converter has a maximum error percentage of 1.199%, which is 6.147% for Mitchell's algorithm while maintaining the hardware metrics close to Mitchell's algorithm.

Non-probabilistic uncertainty quantification for dynamic characterization functions using complex ratio interval arithmetic operation of multidimensional parallelepiped model

Uncertainty quantification for the experimental estimations of dynamic characterization functions, including frequency response functions (FRFs) and transmissibility functions (TFs), is of practical importance in improving the robustness of the real applications of these functions for system identification and structural health monitoring. Interval analysis is an appealing tool for dealing with the uncertainties of engineering problems in which only the bounds of uncertain parameters are available. FRFs and TFs are complex-valued random variables. However, due to the negligence of the dependencies of complex-valued variables, the existing complex ratio interval arithmetic operation can be overly conservative. In this study, the polar representation of complex ratio numbers was extended to complex ratio polar intervals and a multidimensional parallelepiped (MP) interval model was introduced to accommodate the dependence between the numerator and the denominator. Based on the explicit expressions of the MP model through a dependence matrix, two new global extrema searching schemes with and without the regularization of the uncertainty domain of the MP model were proposed in order to derive the explicit formulas of the upper and lower bounds of the magnitudes and phases of the FRFs and TFs. The new schemes were then applied to the uncertainty propagation for a numerically simulated beam and a bridge subjected to a single excitation. The results showed that the interval overestimation problem could be significantly alleviated by using the new complex-valued ratio interval arithmetic operation of the parallelepiped model.

Optimized reversible quantum circuits for $${\mathbb {F}}_{2^8}$$ multiplication

Quantum computers represent a serious threat to the safety of modern encryption standards. Within symmetric cryptography, Advanced Encryption Standard (AES) is believed to be quantum resistant if the key sizes are large enough. Arithmetic operations in AES are performed over the binary field \({\mathbb {F}}_{2^m}\) generated by an irreducible pentanomial of degree \(m = 8\) using polynomial basis (PB) representation. Multiplication over \({\mathbb {F}}_{2^m}\) is the most complex and important arithmetic operation, so efficient implementations are highly desired. A number of quantum circuits realizing \({\mathbb {F}}_{2^m}\) multiplication have been proposed, where the number of qubits, the number of quantum gates and the depth of the circuit are mainly considered as optimization objectives. In this work, optimized reversible quantum circuits for \({\mathbb {F}}_{2^8}\) multiplication using PB generated by two irreducible pentanomials are presented. The proposed reversible multipliers require the minimum number of qubits and CNOT gates, and the minimum depth among similar \({\mathbb {F}}_{2^8}\) multipliers found in the literature.

Accelerating Fully Homomorphic Encryption Through Architecture-Centric Analysis and Optimization

Homomorphic Encryption (HE) draws a significant attention as a privacy-preserving way for cloud computing because it allows computation on encrypted messages called ciphertexts. Among numerous HE schemes proposed, HE for Arithmetic of Approximate Numbers (HEAAN) is rapidly gaining popularity across a wide range of applications because it supports messages that can tolerate approximate computation with no limit on the number of arithmetic operations applicable to the corresponding ciphertexts. A critical shortcoming of HE is the high computation complexity of ciphertext arithmetic; especially, HE multiplication (HE Mul) is more than 10,000 times slower than the corresponding multiplication between unencrypted messages. This leads to a large body of HE acceleration studies, including ones exploiting FPGAs; however, those did not conduct a rigorous analysis of computational complexity and data access patterns of HE Mul. Moreover, the proposals mostly focused on designs with small parameter sizes, making it difficult to accurately estimate their performance in conducting a series of complex arithmetic operations. In this paper, we first describe how HE Mul of HEAAN is performed in a manner friendly to computer architects. Then we conduct a disciplined analysis on its computational and memory access characteristics, through which we (1) extract parallelism in the key functions composing HE Mul and (2) demonstrate how to effectively map the parallelism to the popular parallel processing platforms, multicore CPUs and GPUs, by applying a series of optimization techniques such as transposing matrices and pinning data to threads. This leads to the performance improvement of HE Mul on a CPU and a GPU by 42.9x and 134.1x, respectively, over the single-thread reference HEAAN running on a CPU. The conducted analysis and optimization would set a new foundation for future HE acceleration research.

High-Accuracy Multiply-Accumulate (MAC) Technique for Unary Stochastic Computing

Multiply-accumulate (MAC) operations are common in data processing and machine learning but costly in terms of hardware usage. Stochastic Computing (SC) is a promising approach for low-cost hardware design of complex arithmetic operations such as multiplication. Computing with deterministic unary bit-streams (defined as bit-streams with all 1s grouped together at the beginning or end of a bit-stream) has been recently suggested to improve the accuracy of SC. Conventionally, SC designs use multiplexer (MUX) units or OR gates to accumulate data in the stochastic domain. MUX-based addition suffers from scaling of data and OR-based addition from inaccuracy. This work proposes a novel technique for MAC operation on unary bit-streams that allows exact, non-scaled addition of multiplication results. By introducing a relative delay between the products, we control correlation between bit-streams and eliminate OR-based addition error. We evaluate the accuracy of the proposed technique compared to the state-of-the-art MAC designs. After quantization, the proposed technique demonstrates at least 37% and up to 100% decrease of the mean absolute error for uniformly distributed random input values, compared to traditional OR-based MAC designs. Further, we demonstrate that the proposed technique is practical and evaluate area, power and energy of three possible implementations.

Classification of Moduli Sets for Residue Number System With Special Diagonal Functions

The paper presents algorithms for the generation of Residue Number System (RNS) triples with $SQ=2^{k}-1$ and quadruples with $SQ=2^{k}$ for some k. Triples and quadruples allow us to design efficient hardware implementations of non-modular operations in RNS such as division, sign detection, comparison of numbers, reverse conversion with using of a diagonal function from requiring division with the remainder by the diagonal module SQ. Division with a remainder in the general case is the most complex arithmetic operation in computer technology. However, the consideration of special cases can significantly simplify this operation and increase the efficiency of hardware implementation. We show that there are 5573 good RNS triples (2301 even and 2372 odd) with elements less than 10 000, as the values of SQ vary from $2^{5}-1$ to $2^{27}-1$ . In contrast, RNS quadruples with $SQ=2^{k}$ seem to be quite rare. Restricting our search to sums of the elements in a quadruple less than 4000 we find that exactly 31 such quadruples exist. Their values of SQ vary between 220 and 230 with always even exponent. We suggest the measure of RNS balance and find perfectly balanced RNS among triples according to this measure. We demonstrate the advantages of more balanced quadruples by means of hardware implementation.