Hardware Implementation Complexity Research Articles

A discrete-time dynamic K-winners-take-all neural circuit

A discrete-time mathematical model of K-winners-take-all (KWTA) neural circuit that can quickly identify the K-winning from N neurons, where 1 ⩽ K < N , whose input signals are larger than that of remaining N− K neurons, is given and analyzed. A functional block scheme of the circuit is presented. For N competitors, such circuit is composed of N feedforward and one feedback hard-limiting neurons that are used to determine the dynamic shift of input signals. The circuit has low computational and hardware implementation complexity, high speed of signal processing, can process signals of any finite range, possesses signal order preserving property and does not require resetting and corresponding supervisory circuit that additionally increases a speed of signal processing.

Fast real-time onboard processing of hyperspectral imagery for detection and classification

Remotely sensed hyperspectral imagery has many important applications since its high-spectral resolution enables more accurate object detection and classification. To support immediate decision-making in critical circumstances, real-time onboard implementation is greatly desired. This paper investigates real-time implementation of several popular detection and classification algorithms for image data with different formats. An effective approach to speeding up real-time implementation is proposed by using a small portion of pixels in the evaluation of data statistics. An empirical rule of an appropriate percentage of pixels to be used is investigated, which results in reduced computational complexity and simplified hardware implementation. An overall system architecture is also provided.

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

This paper deals with the process of Transformation and Quantization that is carried out on each inter-predicted residual block in a video encoding process and their reduced complexity hardware implementation. H.264/AVC utilizes 4?×?4 integer transform, which is derived from the 4?×?4 DCT. We propose, a reduced complexity algorithm and a pipelined structure for the Core forward integer transform module. A multiplier-less architecture is realized with less number of shifts and adds compared to existing works. The corresponding inverse transform is exactly reversible. Each of the transformed coefficients is quantized by a scalar quantizer. The quantization step size can be varied from macroblock to macroblock. The proposed unified pipelined architecture outperforms many recent implementations in terms of gate count and is capable of processing a 4?×?4 residual block in 4 clock cycles.

Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms

In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy, according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under good channel condition. The synthesis result in 0.18 μm CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.1 1n) protocol achieves 810 [Mbps] throughput with 283 [mW] power consumption.

FIR Variable Digital Filter With Signed Power-of-Two Coefficients

Variable digital filters (VDFs) are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied online. In this paper, we investigate the design of VDFs with discrete coefficients as a means of achieving low complexity and efficient hardware implementation. The filter coefficients are expressed as the sum of signed power-of-two terms with a restriction on the total number of power-of-two for the filter coefficients. An efficient design procedure is proposed that includes an improved method for handling the quantization of the VDF coefficients for both the min-max and the least-square criteria leading to an optimum quantized solution. For the least-square criterion, a reduced search region around the optimum quantized solution is further constructed and the branch and bound method in conjunction with an efficient branch cutting scheme is presented to search for an optimum solution in this reduced region.

Performance analysis of modified prime-hop codes for OCDMA systems with multiuser detectors

This article presents the performance analysis of modified prime-hop codes (MPHCs) proposed by Wen et al. for optical code division multiple access (OCDMA) systems with multiuser detectors. MPHCs have many advantages over prime-hop codes (PHCs), including low complexity of hardware implementation, low power loss and better performance. The systems using MPHCs would benefit from these advantages under a heavy traffic load. To enhance the performances of MPHCs, the multiuser detectors are utilized to mitigate the negative effect of multiple access interference (MAI) in this study. With a combinatorial approach, the performances of the systems using MPHCs and PHCs are analyzed and compared with one another. The factors to be considered in degrading the system performance include MAI, additive optical intensity noise, and the Poisson characteristics of the optical direct detection process. The numeric results indicate that the systems using MPHCs perform much better than those using PHCs, especially with multiuser detectors.

Haar wavelet based processor scheme for image coding with low circuit complexity

A hardware-oriented image coding processing scheme based on the Haar wavelet transform is presented. The procedure computes a variant of the Haar wavelet transform that uses only addition and subtraction operations, after that, an optimized methodology performs the selection and coding of the coefficients, tailored for it with the main aim of attaining the lowest circuit complexity hardware implementation. A selection strategy, which does not require the previous ordering of coefficients, has been used. A non-conventional coding methodology, which uses an optimized combination of techniques adapted to the various groups of coefficients, has been devised for the coding of the selected coefficients leading to a compressed representation of the image and reducing the coding problems inherent in threshold selection. The compression level reached for images of 512 × 512 pixels with 256 grey levels is just over 22:1, (0.4 bits/pixel) with a normalized mean square error, nrmse, of 2–3%, with subjective qualities which can be classified as good. The whole compression circuitry has been described and simulated at HDL level for up to 4 consecutive images, obtaining consistent results. The complete processor (excluding memory) for images of 256 × 256 pixels has been implemented using only one general-purpose low-cost FPGA chip, thus proving the design reliability and its relative simplicity.

Tradeoffs in transactional memory virtualization

For transactional memory (TM) to achieve widespread acceptance, transactions should not be limited to the physical resources of any specific hardware implementation. TM systems should guarantee correct execution even when transactions exceed scheduling quanta, overflow the capacity of hardware caches and physical memory, or include more independent nesting levels than what is supported in hardware. Existing proposals for TM virtualization are either incomplete or rely on complex hardware implementations, which are an overkill if virtualization is invoked infrequently in the common case.We present eXtended Transactional Memory (XTM), the first TM virtualization system that virtualizes all aspects of transactional execution (time, space, and nesting depth). XTM is implemented in software using virtual memory support. It operates at page granularity, using private copies of overflowed pages to buffer memory updates until the transaction commits and snapshots of pages to detect interference between transactions. We also describe two enhancements to XTM that use limited hardware support to address key performance bottlenecks.We compare XTM to hardwarebased virtualization using both real applications and synthetic microbenchmarks. We show that despite being software-based, XTM and its enhancements are competitive with hardware-based alternatives. Overall, we demonstrate that XTM provides a complete, flexible, and low-cost mechanism for practical TM virtualization.

Tradeoffs in transactional memory virtualization

For transactional memory (TM) to achieve widespread acceptance, transactions should not be limited to the physical resources of any specific hardware implementation. TM systems should guarantee correct execution even when transactions exceed scheduling quanta, overflow the capacity of hardware caches and physical memory, or include more independent nesting levels than what is supported in hardware. Existing proposals for TM virtualization are either incomplete or rely on complex hardware implementations, which are an overkill if virtualization is invoked infrequently in the common case.We present eXtended Transactional Memory (XTM), the first TM virtualization system that virtualizes all aspects of transactional execution (time, space, and nesting depth). XTM is implemented in software using virtual memory support. It operates at page granularity, using private copies of overflowed pages to buffer memory updates until the transaction commits and snapshots of pages to detect interference between transactions. We also describe two enhancements to XTM that use limited hardware support to address key performance bottlenecks.We compare XTM to hardwarebased virtualization using both real applications and synthetic microbenchmarks. We show that despite being software-based, XTM and its enhancements are competitive with hardware-based alternatives. Overall, we demonstrate that XTM provides a complete, flexible, and low-cost mechanism for practical TM virtualization.

Tradeoffs in transactional memory virtualization

For transactional memory (TM) to achieve widespread acceptance, transactions should not be limited to the physical resources of any specific hardware implementation. TM systems should guarantee correct execution even when transactions exceed scheduling quanta, overflow the capacity of hardware caches and physical memory, or include more independent nesting levels than what is supported in hardware. Existing proposals for TM virtualization are either incomplete or rely on complex hardware implementations, which are an overkill if virtualization is invoked infrequently in the common case.We present eXtended Transactional Memory (XTM), the first TM virtualization system that virtualizes all aspects of transactional execution (time, space, and nesting depth). XTM is implemented in software using virtual memory support. It operates at page granularity, using private copies of overflowed pages to buffer memory updates until the transaction commits and snapshots of pages to detect interference between transactions. We also describe two enhancements to XTM that use limited hardware support to address key performance bottlenecks.We compare XTM to hardwarebased virtualization using both real applications and synthetic microbenchmarks. We show that despite being software-based, XTM and its enhancements are competitive with hardware-based alternatives. Overall, we demonstrate that XTM provides a complete, flexible, and low-cost mechanism for practical TM virtualization.

A Parallel-Based Lifting Algorithm and VLSI architecture for DWT

A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Tα) to Tm + 4Tα, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

An observer-based decentralized tracker for sampled-data systems: an evolutionary programming approach

Decentralized control is a practical control methodology for large-scale multivariable systems. This paper presents a LQR design methodology to design a state-feedback decentralized high-gain analog controller, which gives the desired decentralized performance of the controlled analog system. Then, a prediction-based decentralized low-gain digital controller is developed from the decentralized high-gain analog controller for the hybrid controlled system. As a result, the complexity and cost of hardware implementation of the controller can be significantly reduced. In order to improve the performance of the decentralized hybrid system, the evolutionary programming (EP) is employed to tune the observer-based decentralized tracker. Some examples are presented to illustrate the developed design methodology.

Efficient robust adaptive decision feedback equalizer for large delay sparse channel

In this paper, an efficient decision feedback equalizer (DFE) is presented for sparse channels with large delay echoes, which are encountered in many high-speed wireless communication applications. Unlike the conventional DFE, this proposed equalizer considers that the channel is sparse and large number of DFE taps lead to noise accumulation problem. The new method can achieve efficient equalization by setting the active group for equalization taps and clearing the abandoned taps mechanism. As a result, it can both reduce hardware implementation complexity effectively and improve the performance compared to the conventional DFE. Brief analysis about noise accumulation effects in large-scale equalizer and working mechanism description of this effective algorithm exhibits us where the performance gain lies. Simulation results show that this modified DFE exhibits considerable computational savings, faster convergence, and better performance and improved tracking capabilities than the conventional ones. It is quite fit for applications in high-speed systems, such as high definition television (HDTV) and broadband mobile communication.

Implementation and Performance Evaluation of Simple SDM-COFDM Prototype Using Propagation Coefficient Matrix Tracking for Fast Fading MIMO Channels

This paper describes implementation and performance evaluation of simple SDM-COFDM (Space Division Multiplexed-Coded Orthogonal Frequency Division Multiplexing) prototype over fading MIMO (Multi-Input Multi-Output) channel in order to achieve higher frequency utilization efficiency. It employs ZF (Zero Forcing) type detection scheme for SDM transmission to reduce hardware implementation complexity, where ZF type detection scheme needs to only multiply the received data by the estimated inverse propagation coefficient matrix at each OFDM subcarrier. Moreover, in order to improve the performance degradation due to the increase of the transmitted data length per frame in fast fading environments, the inverse matrix tracking using STC (Space-Time Coded) pilot is proposed and implemented in the prototype. Experimental results show that the prototype with 2 × 2 antennas achieves about 90% increase of the frequency utilization efficiency compared to the SISO (Single-Input Single-Output) transmission.

A Table-based Color Matching Approach to Improve Color Calibration for Color Output Devices

The color transformation module is important in Color Hard Copy system. The objective of the module is to get the minimum of the color difference between the color signals represented in input devices and output devices. In the proposed method, the color transformation module is implemented in order to reduce the developing time and has the flexibility to modify the module's components. The module performs gamma correction and color matching algorithm whose data is fed and outputted with look-up tables. The table-based color matching approach is to decrease complexity and cost in hardware implementation. In fact, Most of color devices are given linear input signals, but the output color signals are not linear corresponding to the input, even they are centered on some regions within the gamut of the output device. The relationship between the input and output color signals is approximately a gamma curve in the proposed experiments, so the problem can be resolved roughly by the one-dimension gamma correction. The three-dimension color matching algorithm is performed in the uniform color spaces (CIE Lab, CIE Luv) whose color difference is more closely correlated with the perceptual difference. In general, color calibration must be run in such color spaces that the color difference can be quantized to referable values corresponding to the perceptual difference. The Gray Component Replacement theory will be used in processing color separation. The proposed color transformation module can efficiently improve color calibration from the average color difference about 58 down to about 4 for color output devices in the proposed experiments.

The faster higher-order cellular automaton for hyper-parallel undistorted data compression

This paper defines second-order and third-order permutation global functions and presents the corresponding higher-order cellular automaton approach to the hyper-parallel undistorted data compression. The genetic algorithm is successfully devoted to finding out all the correct local compression rules for the higher-order cellular automaton. The correctness of the higher-order compression rules, the time complexity, and the systolic hardware implementation issue are discussed. In comparison with the first-order automaton method reported, the proposed higher-order approach has much faster compression speed with almost the same degree of cellular structure complexity for hardware implementation.

A learning algorithm for oscillatory cellular neural networks

We present a cellular type oscillatory neural network for temporal segregation of stationary input patterns. The model comprises an array of locally connected neural oscillators with connections limited to a 4-connected neighborhood. The architecture is reminiscent of the well-known cellular neural network that consists of local connection for feature extraction. By means of a novel learning rule and an initialization scheme, global synchronization can be accomplished without incurring any erroneous synchrony among uncorrelated objects. Each oscillator comprises two mutually coupled neurons, and neurons share a piecewise-linear activation function characteristic. The dynamics of traditional oscillatory models is simplified by using only one plastic synapse, and the overall complexity for hardware implementation is reduced. Based on the connectedness of image segments, it is shown that global synchronization and desynchronization can be achieved by means of locally connected synapses, and this opens up a tremendous application potential for the proposed architecture. Furthermore, by using special grouping synapses it is demonstrated that temporal segregation of overlapping gray-level and color segments can also be achieved. Finally, simulation results show that the learning rule proposed circumvents the problem of component mismatches, and hence facilitates a large-scale integration.

Design of smart power synchronous rectifier

In low-output-voltage DC/DC power converters, power losses due to the conduction of rectifying devices are significant. Using synchronous rectifiers instead of the conventional fast recovery diodes or Schottky diodes is an effective solution to this problem in most topologies. However, for synchronous rectifiers to perform effectively, this requires an external gate drive with proper sensing and timing control circuits. This can increase the complexity and cost in power converter hardware implementation. For the first time, a smart power synchronous rectifier (SPSR), which is a two-terminal MOS rectifier, is designed to overcome this difficulty. The SPSR integrates a simple control unit with a power MOSFET into a smart module to form a self-controlled synchronous rectifier. It has great advantages over the conventional discrete circuit composition, such as integrated gate control, precise timing switching and fast transient response, which are suitable for applications in high-frequency pulsewidth modulation (PWM) power converter circuits.

Sequential design of hysteresis current controller for three-phase inverter

In this paper, a novel multivariable hysteresis current controller for three-phase inverters is presented. Hysteresis controllers are intrinsically robust to system parameters, exhibit very high dynamics, and are suitable for simple implementation. The main drawback of the hysteresis controller is a limited control on transistors' switching frequency. Very high switching frequency may result if three independent controllers are used. Multivariable solutions were proposed in the literature to solve the problem. In this paper, it is shown how the use of a sequential design for the multivariable controller can further contribute to transistors' switching frequency reduction, with no significant increase in the hardware implementation complexity. The proposed controller is illustrated and compared with other hysteresis controllers presented in the literature. It ensures a significant reduction of transistors' switching frequency with respect to the other tested controllers, under the same operating conditions. A prototype controller is also presented. The effects of noise captured by current sensors (especially Hall-effect type) on the performance of industrial hysteresis controllers are discussed. It is shown how the sequential design of the controller can also help in solving this critical problem. Experimental results are reported to confirm the quality of the proposed controller. The system stability condition is derived in an appendix.

Architectures for MPEG compressed bitstream scaling

The idea of moving picture expert group (MPEG) bitstream scaling relates to altering or scaling the amount of data in a previously compressed MPEG bitstream. The new scaled bitstream conforms to constraints that are not known nor considered when the original preceded bitstream was constructed. Numerous applications for video transmission and storage are being developed based on the MPEG video coding standard. Applications such as video on demand, trick-play track on digital video tape recorders (VTR's) and extended-play recording on VTR's motivate the idea of bitstream scaling. In this paper, we present several bitstream scaling methods for the purpose of reducing the rate of constant bit rate (CBR) encoded bitstreams. The different methods have varying hardware implementation complexity and associated trade-offs in resulting image quality. Simulation results on MPEG test sequences demonstrate the typical performance trade-offs of the methods.