Hardware Implementation Complexity Research Articles

A cascaded bit-weighted distribution matching for LDPC-coded PS-64QAM DMT in a high-speed Unamplified IM-DD system

We experimentally demonstrate the generation and transmission of probabilistic shaping (PS) 64-ary quadrature amplitude modulation (64-QAM) discrete multi-tone (DMT) signal with low-density parity-check (LDPC)-coded modulation based on two-stage bit-weighted distribution matching (TS-BWDM) in a high-speed unamplified intensity modulation and direct detection system. The TS-BWDM scheme is based on a two-stage bit-weighted inversion algorithm, which has the advantages of no complex multiplication and division operations and low hardware implementation complexity. As the key content of TS-BWDM, before FEC coding, the bit-weighted intervention operation is used to change the bit probability of a specific sequence in the parallel binary sequence. The two-stage bit-weighted inversion operation and one-stage weight-labeling bit insertion is performed for achieving the target symbol probability distribution. As a result, it does not add a significant amount of extra redundant bits. Additionally, the high-accuracy training symbols-based sampling frequency offset (SFO) estimation method and digital interpolation are used to compensate SFO. In our experiments, the TS-BWDM-based PS-64QAM DMT signals with a net rate of 157.3-Gb/s transmission over 10-km non-zero dispersion- shifted fiber can be achieved. The system performance is investigated under two LDPC code rates (3/4 and 9/10) and three PS parameter values (k = 3, 5 and 9). The experimental results show that the receiver power sensitivity and the system fiber nonlinear effect tolerance can be significantly improved compared with uniformly-distributed signals.

A novel design algorithm for low complexity sparse 2‐D FIR filters

SummaryThe hardware implementation complexity of traditional two‐dimensional (2‐D) finite impulse response (FIR) filters with high order is very high. In this paper, a novel sparse 2‐D FIR filter design algorithm has been proposed by combining the common subexpression elimination technique and sparse filter design algorithms to reduce hardware implementation complexity. First, an initial 2‐D FIR filter with sparse coefficients that meets frequency‐domain specifications is obtained by the sparse filter design algorithm. Then, each filter coefficient is quantized in canonical signed digit, and the sensitivities of all weight‐two subexpressions and isolated non‐zero bits are calculated. Finally, the filter coefficients with low implementation cost are reconstructed via iteratively choosing subexpressions and isolated non‐zero bits in terms of their sensitivities. Simulation results show that the proposed algorithm saves about of adders compared with other low complexity filter design method, which reduces effectively the implementation cost.

Toward Optimized In‐Memory Reinforcement Learning: Leveraging 1/f Noise of Synaptic Ferroelectric Field‐Effect‐Transistors for Efficient Exploration

Reinforcement learning (RL), exhibiting outstanding performance in various fields, requires large amounts of data for high performance. While exploration techniques address this requirement, conventional exploration methods have limitations: complexity of hardware implementation and significant hardware burden. Herein, in‐memory RL systems leveraging intrinsic 1/f noise of synaptic ferroelectric field‐effect‐transistors (FeFETs) for efficient exploration are proposed. The electrical characteristics of fabricated FeFETs with low‐power operation capability verify their suitability for neuromorphic systems. The proposed system achieves comparable performance to the conventional exploration method without additional circuits. The intrinsic 1/f noise of the FeFETs facilitates efficient exploration and offers significant advantages: efficiency in hardware implementation and simplicity in adjusting the 1/f noise level for optimal performance. This approach effectively addresses the challenges of conventional exploration methods. The operation mechanism of the exploration method utilizing the 1/f noise is systematically analyzed. The proposed in‐memory RL system demonstrates robustness and reliability to the device‐to‐device variation and the initial conductance distribution. This work provides further insights into the exploration methods of RL, paving the way for advanced in‐memory RL systems.

Enhancing multiplication efficiency: Harnessing Booth algorithm and Wallace tree synergy for 32-bit signed multipliers

This paper focuses on exploring performance optimization strategies for 32-bit signed multipliers in the realm of digital computation. The ingenious combination of the Booth algorithm and the Wallace tree takes center stage as the core of this research. Through a thorough analysis of this combined technique, the paper unveils its multifaceted advantages in multiplication operations. The unique contribution of the Booth algorithm is elaborately discussed, which involves streamlining the multiplication process by reducing the number of addition operations. Subsequently, the exceptional performance of the Wallace tree in accelerating the merging of partial products is highlighted. Through the synergistic interplay of these two techniques, the efficiency of multiplication operations is significantly enhanced, particularly suited for domains necessitating high-speed arithmetic computations, such as graphics processing and digital signal processing. The paper delves further into the significance of optimizing resource utilization, particularly in the field of integrated circuit design. By minimizing addition operations and optimizing parallel processing, the complexity of hardware implementation is reduced, leading to a notable decrease in resource requirements. This advantage proves invaluable in modern integrated circuit design, aiding designers in striking an optimal balance between spatial efficiency and power consumption.

Modification of Intertwining Logistic Map and a Novel Pseudo Random Number Generator

Chaotic maps have been widely studied in the field of cryptography for their complex dynamics. However, chaos-based cryptosystems have not been widely used in practice. One important reason is that the following requirements of practical engineering applications are not taken into account: computational complexity and difficulty of hardware implementation. In this paper, based on the demand for information security applications, we modify the local structure of the three-dimensional Intertwining Logistic chaotic map to improve the efficiency of software calculation and reduce the cost of hardware implementation while maintaining the complex dynamic behavior of the original map. To achieve the goal by reducing the number of floating point operations, we design a mechanism that can be decomposed into two processes. One process is that the input parameters value of the original system is fixed to 2k by Scale index analysis. The other process is that the transcendental function of the original system is replaced by a nonlinear polynomial. We named the new map as “Simple intertwining logistic”. The basic chaotic dynamic behavior of the new system for controlling parameter is qualitatively analyzed by bifurcation diagram and Lyapunov exponent; the non-periodicity of the sequence generated by the new system is quantitatively evaluated by using Scale index technique based on continuous wavelet change. Fuzzy entropy (FuzzyEn) is used to evaluate the randomness of the new system in different finite precision digital systems. The analysis and evaluation results show that the optimized map could achieve the designed target. Then, a novel scheme for generating pseudo-random numbers is proposed based on new map. To ensure its usability in cryptographic applications, a series of analysis are carried out. They mainly include key space analysis, recurrence plots analysis, correlation analysis, information entropy, statistical complexity measure, and performance speed. The statistical properties of the proposed pseudo random number generator (PRNG) are tested with NIST SP800-22 and DIEHARD. The obtained results of analyzing and statistical software testing shows that, the proposed PRNG passed all these tests and have good randomness. In particular, the speed of generating random numbers is extremely rapid compared with existing chaotic PRNGs. Compared to the original chaotic map (using the same scheme of random number generation), the speed is increased by 1.5 times. Thus, the proposed PRNG can be used in the information security.

Abakus: Accelerating k -mer Counting with Storage Technology

This work seeks to leverage Processing-with-storage-technology (PWST) to accelerate a key bioinformatics kernel called k -mer counting, which involves processing large files of sequence data on the disk to build a histogram of fixed-size genome sequence substrings and thereby entails prohibitively high I/O overhead. In particular, this work proposes a set of accelerator designs called Abakus that offer varying degrees of tradeoffs in terms of performance, efficiency, and hardware implementation complexity. The key to these designs is a set of domain-specific hardware extensions to accelerate the key operations for k -mer counting at various levels of the SSD hierarchy, with the goal of enhancing the limited computing capabilities of conventional SSDs, while exploiting the parallelism of the multi-channel, multi-way SSDs. Our evaluation suggests that Abakus can achieve 8.42×, 6.91×, and 2.32× speedup over the CPU-, GPU-, and near-data processing solutions.

Hybrid Wideband Beamforming for Sum Spectral Efficiency Maximization in Millimeter-Wave Relay-Assisted Multiuser MIMO Cognitive Radio Networks

Relay-assisted hybrid beamforming plays an inevitable role in enhancing network coverage, transmission range, and spectral efficiency while simultaneously reducing hardware cost, power consumption, and hardware implementation complexity. This study investigates a cognitive radio network (CRN)-based hybrid wideband transceiver for millimeter-wave (mm-wave) decode-and-forward (DF) relay-assisted multiuser (MU) multiple-input multiple-output (MIMO) systems. It is worth mentioning that the underlying problem has not been addressed so far, which is a real motivation behind the proposed algorithm. The joint optimization of hybrid processing components and the constant amplitude constraints imposed by the analog beamforming solution make this problem non-convex and NP-hard. Furthermore, the analog beamformer common to all sub-carriers is another challenging aspect of the underlying problem. To derive the frequency-flat analog processing component in the radio frequency (RF) domain and frequency-dependent baseband processing matrices in the baseband domain, the original complicated problem is reformulated as two single-hop sum-rate maximization sub-problems. Taking advantage of this decomposition, the sum spectral efficiency is maximized through RF precoding and combining. On the other hand, the impact of interference among transmitted data streams and inter-user interference (IUI) is minimized via baseband processing matrices. Finally, computer simulations are conducted by changing system parameters, considering both perfect and imperfect channel state information (CSI). Simulation results demonstrate that the proposed algorithm achieves performance close to full-complexity precoding and outperforms other well-known hybrid beamforming techniques. Specifically, more than 95% efficiency is achieved with perfect CSI, and more than 90% efficiency is attained under the assumption of 30% error in the estimated channels.

Fuzzy super twisting mode control of a rigid-flexible robotic arm based on approximate inertial manifold dimensionality reduction.

The control of infinite-dimensional rigid-flexible robotic arms presents significant challenges, with direct truncation of first-order modal models resulting in poor control quality and second-order models leading to complex hardware implementations. To address these issues, we propose a fuzzy super twisting mode control method based on approximate inertial manifold dimensionality reduction for the robotic arm. This innovative approach features an adjustable exponential non-singular sliding surface and a stable continuous super twisting algorithm. A novel fuzzy strategy dynamically optimizes the sliding surface coefficient in real-time, simplifying the control mechanism. Our findings, supported by various simulations and experiments, indicate that the proposed method outperforms directly truncated first-order and second-order modal models. It demonstrates effective tracking performance under bounded external disturbances and robustness to system variability. The method's finite-time convergence, facilitated by the modification of the nonlinear homogeneous sliding surface, along with the system's stability, confirmed via Lyapunov theory, marks a significant improvement in control quality and simplification of hardware implementation for rigid-flexible robotic arms.

A Simple Chaotic Model With Complex Chaotic Behaviors and Its Hardware Implementation

Recently, due to the initial sensitivity, ergodicity, boundedness, and unpredictability of chaos, it has been widely used in the fields of secure communication, signal processing, chaotic synchronization, etc. Moreover, due to the low complexity of hardware implementation, widespread attention to one-dimensional (1D) chaotic maps has been paid from researchers. However, some existing 1D maps have simple chaotic behaviors and discrete chaotic intervals, which have significantly affected the practical application. To address these shortcomings, this paper proposes a 1D chaotic model based on the absolute value function and the cosine function called the cosine-coupled chaotic model (CCCM). It can use existing 1D chaotic maps as seed maps to construct a series of 1D chaotic maps with continuous chaotic intervals and complex chaotic behaviors. To verify the effectiveness of the CCCM, we first generate three new chaotic maps using the CCCM, and then their chaotic properties are analyzed by using various measures including Lyapunov exponent (LE), sample entropy (SE), correlation dimension (CD), 0-1 test and sensitivity. The experimental results confirm that the new chaotic maps have wider chaotic intervals and more complex chaotic behaviors than the corresponding seed maps and some other advanced chaotic maps. Then we use a field programmable gate array (FPGA) as the hardware platform for simple hardware implementations of the new chaotic maps. And a new pseudo-random number generator (PRNG) is introduced to verify practical applications of the new maps. Finally, experimental results show that the new chaotic maps can be implemented on FPGA and the proposed PRNG has strong random properties.

Scalable Single-Input Behavioral Modeling Architecture for MIMO Systems With Crosstalk

The inherent nonlinear behavior exhibited by power amplifiers (PAs) in saturation mode is a major impediment in wireless systems to achieve higher power efficiency, and higher spectral efficiency. Although PA behavioral modeling and digital predistortion (DPD) techniques are widely utilized at transmitter to characterize and linearize such distorted nonlinear output of PAs, the nonlinear distortions with memory effects have become more severe due to simultaneous strong crosstalk between multiple PA branches in multiple-input multiple-output (MIMO) arrays. Furthermore, current multi-input behavioral models suffer from a sharp increase in number of coefficients as the number of transmitter path increases in MIMO. In overcoming these challenges, we propose a decomposed cross-correlation based single-input-single-output (CC-SISO) behavioral modeling architecture. The proposed solution utilizes a low-cost, novel cross-correlation based method to estimate and cancel the simultaneous nonlinear and reverse crosstalk from multiple PA branches. Once the crosstalk is mitigated, the MIMO DPD can be implemented with single-input DPD blocks which significantly reduces the complexity. Furthermore, CC-SISO DPD eliminates the requirement for signal feedback paths before and after the PA, and thus reduces overall hardware implementation complexity. Through simulations, we demonstrate that the proposed CC-SISO architecture can reduce the overall complexity of state-of-art multi-input DPD models for MIMO systems.

Complex Dynamics, Hardware Implementation and Image Encryption Application of Multiscroll Memeristive Hopfield Neural Network With a Novel Local Active Memeristor

Because of the nonlinearity and memory, memristors are the most suitable electrical component for simulating synapses. A novel local active and nonvolatile memristor is designed. By circuit experiments, its memristive properties are verified. By introducing this memristor, this brief constructs a 4D memristive Hopfield neural network (MHNN) which can perform complex dynamics, such as controllable double-scrolls attractors and controllable initial offset boosting coexistence. Compared with other multiscroll chaotic systems, the autonomy equation of the system is smooth for discarding the sign function. In addition, this MHNN performs well in image encryption applications for the significant complexity of multiscroll. Through safety analysis, the information entropy of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$512 \times 512$ </tex-math></inline-formula> Lena graph is 7.9993, which is very close to the ideal value of 8. Besides, the number of pixels changing rates (NPCR) and the unified averaged changed intensity (UACI) are 99.6097% and 33.4621%, which are almost equal ideal values. Finally, this brief designs the digital circuit of the multiscroll MHNN signal generator and verifies the function with the help of a field programmable gate array (FPGA) and oscilloscope. Besides, by designing a pseudo-random number generation circuit, FPGA can directly encrypt the image and transmit it to the input and output devices.

An Optimal SNR Symbol Decomposition With Serial Transmission Scheme for O-OFDM-Based VLC System

This letter introduces an optimal signal-to-noise ratio symbol decomposition with serial transmission (OSNR-SDST) scheme for optical orthogonal frequency division multiplexing (O-OFDM)-based visible light communication systems with the capability against non-linear clipping distortion. The time-domain O-OFDM symbol is repeatedly clipped based on the optimal times of symbol decomposition determined by the optimal SNR judgment. Optimal SNR judgment is the process of comparing the SNR values of multiple successive symbol decomposition times and choosing the preferred times with the highest SNR as the optimal times of symbol decomposition. The decomposed symbols are sequentially serialized to form a frame for individual LED transmit. Simulations show that the proposed OSNR-SDST exhibits superior transmission performance, especially in bit error rate performance, optical transmit power, and communication rate, over the conventional iterative signal clipping (ISC) and adaptive symbol decomposition with serial transmission (ASDST) schemes. Moreover, the proposed OSNR-SDST is also superior in reducing the complexity of frame synchronization and hardware implementation.

Active Junction Temperature Control for SiC MOSFETs Based on a Resistor-Less Gate Driver

Junction temperature fluctuation is the main cause of failure of power devices including silicon carbide (SiC) MOSFETs, and active junction temperature control is an effective way to improve their reliability. Most existing methods of active junction temperature control rarely consider the system efficiency and the complexity of hardware implementation, which limits their applications. This article proposes an active junction temperature control method for SiC MOSFETs based on a resistor-less gate driver, which consists of two auxiliary MOSFETs with adjustable gate–source voltages. Hence, the switching loss of the SiC MOSFET can be continuously and accurately adjusted to mitigate the efficiency suffer with the junction temperature control. The power loss model of SiC MOSFETs with the proposed gate driver was established. The design principle of the junction temperature controller is introduced. The experimental results show that the junction temperature fluctuation is reduced by 24.1%, and that the lifetime of the SiC MOSFET is prolonged by 3.92 times via using the proposed junction temperature control method. The energy loss of the prototypical inverter is decreased by 4.15% over the whole testing period. The experiment was conducted with SiC MOSFETs, and the proposed method is also suitable for other Si-based semiconductor devices.

Hybrid Precoding Based on a Switching Network in Millimeter Wave MIMO Systems

Aiming at the algorithm difficult optimization of the fully-connected hybrid precoding structure and the complex hardware implementation in millimeter wave multiple-input multiple-output (MIMO) systems, this paper proposes a novel hybrid precoding structure based on a switching network (SNHBP). The structure enables the dynamic grouping of the sub-arrays in three ways by switching the network, which can greatly reduce the hardware complexity, simplify the optimization algorithm, and avoid the performance degradation defect caused by a partially-connected structure. Through simulation of different antenna sizes and different numbers of RF chains, experimental results show that SNHBP can approach the performance of the full digital precoder. Under the condition of more than 2 RF chains, the difference between the unit structure and the full digital precoding is less than 0.13 dB. The spectral efficiency of the low-precision phase optimization algorithm is better than that of the partially-connected structure when the quantization bit of the phase shifter is 3. The feasibility of the three dynamic grouping schemes is verified, which is more beneficial to engineering implementation than the fully-connected structure.

Fixed-Point Analysis and FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

Adeep neural network based equalizer is proposed to mitigate the intersymbol interference observed in next generation high speed passive optical network (PON) links. The DNN based equalizer is shown to outperform the best known conventional equalizer, the maximum likelihood sequence estimator (MLSE) both in back-back and through fiber experiments. To reduce the hardware complexity of DNN based equalizer for PON systems, we investigate the use of embedded parallelization within a DNN structure having multiple symbol outputs from one DNN. We further investigate using a classification output stage with cross entropy cost to perform joint decision on multiple symbol outputs and demonstrated that the sensitivity gain of such scheme over regression output. To understand the complexity of hardware implementation, the fixed-point DNN based equalizers are developed and implemented in FPGA. The impact of fixed-point resolution on the receiver sensitivity and hardware resource utilization in FPGA implementation is analyzed and reported in detail. We show that a reduction of over 40% in LUTs (look up table) utilization is possible by reducing the DNN's weight resolution from 8-bit to 4-bit while incurring a small penalty in receiver sensitivity.

Training threshold neural networks by extreme learning machine and adaptive stochastic resonance

Threshold neural networks are highly useful in engineering applications due to their ease of hardware implementation and low computational complexity. However, such threshold networks have non-differentiable activation functions and therefore cannot be trained by standard gradient-based algorithms. To circumvent this limitation, here we propose a hybrid training algorithm for threshold neural networks. The proposed hybrid training algorithm has two distinguishing features: the structural transformation of the hidden layer enables threshold networks to benefit from a noise-boosted learning capability via adaptive stochastic resonance (ASR), and by using the fast learning algorithm of the extreme learning machine (ELM) suitable generalization performance ensues for the threshold networks. Experimental results on regression and on multiclass classification demonstrate the realizability and practical efficiency of the proposed hybrid training algorithm, thereby demonstrating the beneficial role of artificial noise injection in threshold neural networks.

A Novel Method for Scalable VLSI Implementation of Hyperbolic Tangent Function

Hyperbolic tangent and Sigmoid functions are used as non-linear activation units in the artificial and deep neural networks. Since, these networks are computationally expensive, customized accelerators are designed for achieving the required performance at lower cost and power. The activation function and MAC units are the key building blocks of these neural networks. A low complexity and accurate hardware implementation of the activation function is required to meet the performance and area targets of such neural network accelerators. Moreover, a scalable implementation is required as the recent studies show that the DNNs may use different precision in different layers. This paper presents a novel method based on trigonometric expansion properties of the hyperbolic function for hardware implementation which can be easily tuned for different accuracy and precision requirements.

High-speed PON downstream transmission based on pre-configured KK scheme with CD pre-compensation and direct detection

In this paper, the pre-configured Kramers–Kronig (Pre-KK) scheme combined with the chromatic dispersion pre-compensation (CDPC) has been proposed and studied to reduce the complexity of DSP and hardware implementation at the optical network unit (ONU) side for passive optical network (PON), avoiding the use of KK receiver. For further analysis and verification, 100 Gb/s/λ PON downstream transmissions with 4-level pulse amplitude modulation (PAM-4) signal based on the Pre-KK scheme and KK receiver have been implemented and compared on a unified optical system platform. The results show that the Pre-KK requires 1-bit resolution lower than KK receiver for ADC, and achieves a power budget of 29 dB after 20 km fiber transmission at the strong FEC threshold of 1 × 10−2. By increasing the launch power, the maximum power budget of 33.2 dB can be achieved due to the fiber nonlinearity. The effectiveness of CDPC in Pre-KK scheme has also been investigated and demonstrated over 20 and 50 km transmission. Besides, the computational complexities of two schemes are analyzed and discussed in detail. Hence, the Pre-KK scheme joint with CDPC can be a promising solution for the high-speed PON downstream transmission.

Optimized Continuous Wavelet Transform Algorithm Architecture and Implementation on FPGA for Motion Artifact Rejection in Radar-Based Vital Signs Monitoring

The continuous wavelet transform (CWT) has been used in radar-based vital signs detection to identify and to remove the motion artifacts from the received radar signals. Since the CWT algorithm is computationally heavy, the processing of this algorithm typically results in long processing time and complex hardware implementation. The algorithm in its standard form typically uses software processing tools and is unable to support high-performance data processing. The aim of this research is to design an optimized CWT algorithm architecture to implement it on Field Programmable Gate Array (FPGA) in order to identify the unwanted movement introduced in the retrieved vital signs signals. The optimization approaches in the new implementation structure are based on utilizing the frequency domain processing, optimizing the required number of operations and implementing parallel processing of independent operations. Our design achieves significant processing speed and logic utilization optimization. It is found that processing the algorithm using our proposed hardware architecture is 48 times faster than processing it usingMATLAB. It also achieves an improvement of 58% in speed performance compared to alternative solutions reported in literature. Moreover, efficient resources utilization is achieved and reported. This advanced performance of the proposed design is due to consciously implementing comprehensive approaches of multiple optimization techniques that results in multidimensional improvements. As a result, our achieved design is suitable for utilization in high-performance data processing applications.

Cooperative Detection Method for Distracted and Fatigued Driving Behaviors With Readily Embedded System Implementation

To mitigate risks caused by distracted and fatigued driving, timely and accurate detection of these behaviors is significant for safety concern. Among the state of the art of detection methods based on in-car image analysis, the interaction of multiple distracted and fatigued driving behaviors could make the certain behavior-targeted detection ineffective and unreliable, while the complicated neural-network-based detection methods could be poor in interpretability and feasibility of hardware implementation. This article proposes a novel cooperative detection method for distracted and fatigued driving behaviors, with overall consideration of method performance, operation complexity, and practical hardware implementation. The vital points for detection of hand-held calling, looking left/right continuously, yawning, eye closure, and the cooperative relation among different behaviors are investigated. Experiment cases on the established dataset which involves indoor driving simulation images and actual cockpit driving scenario images of different drivers under various illuminations and background settings are conducted. On the established Di_Fa_C_Tes dataset, the proposed method achieves above 98% detection precision and 37 frames/s processing speed for the tested behaviors by support vector machine (SVM) on a PC platform. Additionally, the article provides a hardware evaluation of the proposed method on i.MX 8QuadMax platform and reaches above 96.8% precision and 16 frames/s processing speed. The experimental results indicate the effectiveness of the proposed method in accurate and fast detection of distracted and fatigued driving behaviors and the promising embedded system application.