Complex Programmable Logic Device Research Articles

A grid-connected eleven-level power conversion interface

ABSTRACT This paper proposes a grid-connected eleven-level power conversion interface (GCELPCI) for renewable power systems. The proposed GCELPCI is composed of a four-port DC-DC power converter (FPDDPC) and an eleven-level inverter (ELI). The FPDDPC combines a boost power converter and a transformer with a turn ratio of 2:1 to generate multiple combinations of the output voltages for the DC bus voltage of the ELI. The ELI integrates an asymmetric voltage technique on a T-type inverter to further convert the DC output voltages of FPDDPC into eleven-level AC voltage. A sinusoidal current is generated by the proposed GCELPCI through the filter inductor and injected into the power grid. Only nine power electronic switches are used in the ELI to generate an eleven-level AC voltage, the number of power electronic switches is reduced to simplify the power circuit. In addition, the capacity of the filter inductor is reduced. A digital signal processor (DSP) and a complex programmable logic device (CPLD) chip are used as the digital controller to complete a hardware prototype to verify the performance of the proposed GCELI.

Implementation of EnDat Interface Master Using Configurable Logic Block in MCU

In this study, we propose an implementation method of the Encoder Data (EnDat) interface master for slave encoders using only a configurable logic block (CLB) and a serial peripheral interface (SPI) integrated into microcontroller units. By programming the CLB device to execute logic functions and finite state machines designed for the EnDat interface master operation, we realize the EnDat and SPI clocks that are required for the EnDat interface master operation. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are unnecessary for the master implementation. We build a one-axis feed drive system that is powered by an AC motor and equipped with an EnDat linear encoder for measuring table speed and position. By performing various experiments for table position and speed control based on the built feed drive system, we verify the performance and practical usefulness of the implemented EnDat interface master. The maximum EnDat clock frequency without the propagation delay compensation is achieved by 2 MHz, which can cope with 16 kHz control cycle frequency. The usefulness is demonstrated by showing the table speed and position control performance that are acceptable in real applications.

Charge Couple Device (CCD) Photoelectric Signal Data Acquisition and Its Application in the Machine Vision of Artificial Intelligence

The development of Charge Couple Device (CCD) technology is particularly rapid in the fields of image sensors and non-contact measurement. In this study, a data acquisition device applied to CCD photoelectric detection system is designed. Among them, the design of the Differential Amplification (DA) module, Analog-to-Digital Converter (ADC) module, First In First Out (FIFO) cache module, and Complex Programmable Logic Device (CPLD) module in this device are emphasized. The ADC circuit in the ADC module converts two 4 MHz analog photoelectric signals generated by the CCD sensor at a frequency of 8 MHz, and then outputs 12-bit digital signals. The collected photoelectric signal is used to detect the damage to the surface of ancient buildings with the machine vision technology of artificial intelligence (AI). In the test, the DA circuit can adjust the voltage range of two photoelectric analog signals output by CCD to a predetermined range (1.5 V∼2.0 V). In the ADC circuit test, there is no data in the FIFO when there is no input conversion, and the converted data will be stored in the internal FIFO during the conversion clock period. Based on machine vision technology, surface damage types of ancient buildings are defined, namely spalling, cracks, and disruption, and surface image samples are generated from collected signals. The samples are trained using the convolutional neural network, and the classifier is generated. The test reveals that the designed photoelectric signal acquisition device and AI machine vision technology can accurately classify the surface damage of ancient buildings.

CLB-Based Development of BiSS-C Interface Master for Motor Encoders

Encoder interfaces should be operated in real time with high precision and fast processing for industrial motor control systems. The continuous bidirectional serial synchronous (BiSS-C) interface is an open-source serial communication protocol designed for motor encoders and is suitable for industrial purposes because of its fast serial communication speed. In this study, we propose a method for developing a BiSS-C interface master for a motor encoder slave, using only the configurable logic block (CLB) peripheral integrated into TI microcontroller units. By analyzing the detailed operation protocol of the BiSS-C interface, we create the truth and state tables for logic circuits and finite state machines, which are required for the BiSS-C interface master. Then, by programming the CLB based on the created truth and state tables, we implement the master clock, serial peripheral interface (SPI) clock, and operational process for the master. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are not required for the master implementations. The developed method can be immediately applied to developing the masters for other BiSS-C encoders with different specifications, which is certainly necessary for a motor drive development and test. By building an AC motor control system with the developed master and performing various experiments, we verify the performance and practical usefulness of the developed BiSS-C interface master. The maximum master clock frequency without any CRC errors is achieved by 6.25 MHz, which can cope with more than 20 kHz motor control cycle frequency. The usefulness is demonstrated by showing the motor speed and position control performance that are acceptable in real applications.

Switching Frequency Limited Hysteresis Based Voltage Mode Control of Single-Phase Voltage Source Inverters

This paper proposes a new control strategy for single-phase voltage source inverters that does not rely on switching based on Pulse Width Modulation. The technique is similar to conventional current hysteresis control, but instead of the output current, the low-pass-filtered inverter output voltage is utilised as the feedback signal. Nevertheless, the switching instants are not determined by a predefined band, but rather by a low-cost Complex Programmable Logic Device (CPLD)-based control logic, which ensures a nearly constant switching frequency. Similar to hysteresis-based control methods, the proposed method ensures a rapid dynamic response. Notable characteristics of the proposed method include a quick dynamic response, a well-defined harmonic spectrum, and an improved total harmonic distortion (THD), particularly during load current and source voltage changes. The proposed method is implemented on a 1 kW, 230 V, 50 Hz prototype. Simulation and experimental results are presented to validate the proposed concept, which demonstrates a superior dynamic response and enhanced THD during load and source voltage variations.

Hysteresis Based Quasi Fixed Frequency Current Control of Single Phase Full Bridge Grid Integrated Voltage Source Inverter

The traditional Fixed Band Hysteresis Current Control (FB-HCC) though being widely used for the current control of grid integrated voltage source inverter (GI-VSI), has the drawback of variable switching frequency. To overcome this drawback, Complex Programmable Logic Device (CPLD) based switching scheme is proposed in this paper. The proposed method calls for a single reference wave and the control concept is to terminate the rising and falling inductor current (iL) either by the comparator or by the CPLD, based on the nature of its slope. Termination of the iL with steeper slope by the comparator ensures lower current ripple, whereas the CPLD ensures constant switching frequency (fsw). However, the iL obtained with the proposed logic has a DC offset, which is corrected by modifying the reference. The basic concept, switching logic, and reference correction are thoroughly detailed. MATLAB/Simulink results are included to verify the proposed concept. The constant frequency operation of the proposed method is also validated in a 2 kW, 230 V, 50 Hz GI-VSI prototype.

Scalable and Configurable Electrical Interface Board for Bus System Development of Different CubeSat Platforms

A flight-proven electrical bus system for the 1U CubeSat platform was designed in the BIRDS satellite program at the Kyushu Institute of Technology. The bus utilizes a backplane board as the mechanical and electrical interface between the subsystems and the payloads. The electrical routes on the backplane are configured by software using a complex programmable logic device (CPLD). It allows for reusability in multiple CubeSat projects while lowering costs and development time; as a result, resources can be directed toward developing the mission payloads. Lastly, it provides more time for integration and system-level verification, which are critical for a reliable and successful mission. The current trend of CubeSat launches is focused on 3U and 6U platforms due to their capability to accommodate multiple and complex payloads. Hence, a demonstration of the electrical bus system to adapt to larger platforms is necessary. This study demonstrates the configurable electrical interface board’s scalability in two cases: the capability to accommodate (1) multiple missions and (2) complex payload requirements. In the first case, a 3U-size configurable backplane prototype was designed to handle 13 mission payloads. Four CPLDs were used to manage the limited number of digital interfaces between the existing bus system and the mission payloads. The measured transmission delay was up to 20 ns, which is acceptable for simple serial communications such as UART and SPI. Furthermore, the measured energy consumption of the backplane per ISS orbit was only 28 mWh. Lastly, the designed backplane was proven to be highly reliable as no bit errors were detected throughout the functionality tests. In the second case, a configurable backplane was implemented in a 6U CubeSat with complex payload requirements compared to the 1U CubeSat platform. The CubeSat was deployed in ISS orbit, and the initial on-orbit results indicated that the designed backplane supported missions without issues.

Multi-channel Detector Module for Multi-energy Gamma Ray Computed Tomography

In this paper an enhanced signal processing electronics for an existing multi-channel detector module for gamma ray computed tomography is presented. The detector electronics is able to evaluate gamma photon energies by measuring pulse duration times, which makes it perfectly suitable for attenuation measurements with multi-energy and/or multiple isotopic sources. The duration time of each voltage pulse generated by a gamma photon within the radiation detector is measured using a complex programmable logic device. A sophisticated logic circuit for eight detector channels is designed to acquire the pulse duration time spectra in a total of 256 channels per detector channel in parallel. This paper introduces the basic concept, describes the general and a specific CPLD design, provides an analysis of the accuracy and presents measured pulse duration time spectra.

Исследование декомпозиции нейронной сети в системе схемотехнического моделирования Proteus

The division of a monolithic neural network into blocks with their implementation on programmable logic within the framework of the Fog computing concept is considered. It is assumed that considering possible reconfiguration the implementation of blocks is performed on programmable logic: field-programmable gate array, FPGA (complex programmable logic device, CPLD), System-on-a-Chip, SoC or System-in-Package, SiP. The article explores such an implementation in the Proteus Design Suite based on ATMega32 microcontrollers. Modeling confirms the efficiency of the developed decomposition method. The research was carried out under the RFBR grant 20-37-90036 (Method of synthesizing neural network recognition devices for implementing the Fog computing mode).

A Decoder – Look up Tables for FPGAs

The FPGA (Field-Programmable Gate Array) has recently become the popular hardware and so-called LUTs (Look up Tables) are the basic of the FPGAs logic. For example, n-LUT is the MOS pass transistors multiplexer 2n-1 which input data receive SRAM cells logic function configuration (user’s projects Truth Table). Address inputs of the LUT are the variables. Therefore, we get one n-arguments logic function for the actual FPGA configuration. To get m functions (even with the same n-arguments) we should take m LUT. Authors propose a novel Decoder n-LUT (n-DC LUT), which makes possible to get m functions with the same n-arguments, like in Program Logic Array (PLA) CPLD (Complex Programmable Logic Device). DC LUT activates one of the 2n product terms outputs. Combined with OR product terms we can get m functions with the same n-arguments. To do this option we can use, for example, FPGAs typical connections units. The restriction of Meade-Conway for the FPGAs allows n=3 in one tree. Two 3-LUTs with one 1-LUTs form 4-LUT. Modern Adaptive Logic Modules (ALM) have n=8, but not all possible functions are implemented. The article deals with the design and investigation of some variants 3-DC LUT: with pull up output resistors, with orthogonal output circuits, with orthogonal transistors for each pass transistor. Simulation confirms the feasibility of the proposed method and shows that DC LUT with orthogonal output circuits is better variant of the systems realization in terms of current consumption and time delay at large n. A further development of the ALM concept may be the introduction of adaptive DC LUT, which, by tuning, can calculate single LUT function or 2n decoder functions. The proposed elements allow to increase the functionality of the FPGAs.

Implementation Study Of Field Programmable Gate Array (FPGA) And Complex Programmable Logic Device (CPLD) In Collision Avoidance System Using Vhsic Hardware Description Language (VHDL)

A collision avoidance system, also known as a pre-crash system, forward collision warning system, or collision mitigation system, is a sophisticated driver-assistance system that aims to avoid or mitigate the severity of a collision. For this research, collision avoidance system will be fabricating to show that this system can detect avoidance range before apply the braking action to prevent collision. The ultrasonic sensor will be used in this system to detect the avoidance range. In this collision avoidance system, there will be uses of Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD). This research will observe how to implement FPGA and CPLD in the collision avoidance system using VHSIC Hardware Description Language (VHDL). The VHDL will be done in Quartus II 15.0 Software. In this research, Terasic DE-10 Standard board has been used. It contains FPGA microcontroller model Cyclone V SoC 5CSXFC6D6F31C6N. Max II board is used because it contains CPLD microcontroller model EPM240T100C5.

Design and Implementation of the Turbo Encoder by using Magnitude Comparator in IVS Chip

This research studies the concept and application of the Turbo_encoder to be an integrated module in the In-Vehicle Device (IVS) embedded module by using the magnitude comparator. To create the Turbo_encoder Module, the complex PLDS are used. The variants of series and parallel Turbo_encoders are discussed. It is shown that proportional to chip size processing time also increased in the Turbo_encoder parallel computing variant system. The magnitude comparator with parallel computing variant system is implemented in this project. The usage of proposed logic resulted in efficient area and power usage. The architecture construction using Verilog HDL and implementation and simulation are executed in the Xilinx-ise tool. To incorporate the built module, Xilinx Vertex Low Power is used. The Turbo_encoder module on a single programmable computer is planned to be part of the IVS chip.

Finite State Machine-Based Realization of Sparse Matrix Converter

Matrix converters (MCs), compared to traditional back-to-back converters, offer a series of advantages for ac-ac power conversion. However, increased realization complexity and cost have restricted the proliferation of MCs to a limited number of commercially available solutions. In this article, an efficient sparse matrix converter realization is presented as a step toward the development of simpler, lower-cost, and reliable realization architectures. In contrast to common practices that utilize a flexible logic fabric, such as a field programmable gate array or a complex programmable logic device, and a digital signal processor, the proposed implementation is based on a single commercial off-the-shelf microcontroller unit. This method is possible due to the novel implementation of a synchronous finite state machine that realizes the four-step commutation strategy required by the current source rectifier stage. Since the complete control scheme is implemented in one IC, it inherently avoids important MC realization issues, such as communication delays and synchronization between controllers. In addition, both software and hardware requirements are reduced and lower the overall development effort and cost.

The Application of Distance-Measuring by Ultrasonic Based on CPLD in the Field of Agriculture Robot

In order to further improve the accuracy of the distance measurement of agricultural robots and realize the precise delivery of crop feeds, thereby increasing the yield of crops, this paper proposed a ultrasonic distance measurement system for agricultural robots based on Complex Programmable Logic Device (CPLD). The system mainly included two parts: hardware and software. The hardware part mainly included CPLD control part, ultrasonic sensor and temperature sensor. The software part mainly included the identification and counting of ultrasonic signals, data processing and temperature compensation. The system performed accurate ultrasonic ranging based on the current temperature and ultrasonic echo measurement. In order to improve the degree of humanization of the system, the system used a high-brightness digital tube to display the measured data in real time. The part of hardware had been analyzed and designed, and the same time the part of software had been designed by the language of VHDL and simulated by wave in QUARTUSII platform. Finally the design was downloaded to a CPLD chip named EPM1270T144C5. The system was tested by measuring the distance of block range from 50mm to 5500mm in the temperature of 28°C. After actual system testing, we found that the precision of test could be controlled less than 0.1 mm as a result of temperature compensating and high-speed characteristic of CPLD.

A Flexible DSP-FPGA Based Platform for Experiments with Modular Multilevel Cascade Converters


 The growing use of Modular Multilevel Cascade Converter (MMCC) topologies in applications such as High Voltage Direct Current Transmission, Static Var Compensation, Alternating Current (AC) Drives and renewable energy systems, among others, turns their study relevant. However, as the number of Power Submodules in the MMCCs increases, the applied control strategies, data communication and digital hardware complexity increases as well. This paper proposes a flexible and scalable platform, that is adequate for implementing different MMCC topologies (single star, single delta or double star), communication schemes (star or ring) and control strategies (centralized or distributed). The Processing Board explores the availability of Field Programmable Gate Arrays, Digital Signal Processors and ARM microcontrollers. The Power and Measurement Submodules processing capability is provided by Complex Programmable Logic Devices and ARM microcontrollers. Description of the tasks implemented in the processing devices and experiments are presented for a test case, in which a double star topology with star communication and centralized processing strategy is tested using fixed switching frequency and equally displaced carriers.

Design of an automated railway crossing system with Verilog language in CPLD

In this paper the basic requirements for the automatic railways crossing devices are formulated. A block diagram, which consists of elements that make the automatic railways crossing systems are presented and their working principles are discussed. Based on the hardware description language - Verilog, a digital railway crossing control system is designed and is implemented with complex programmable logic device, taking into account the requirements. As an opportunity for practical application the controller CoolRunner II could be used. Simulation results with set input parameters are shown to represent the functionality of the designed system. The results obtained can be used for design, implementation, simulation and development of such types of systems in railway crossing automatics.

Design and Adaptive Control of Matrix Transformer Based Indirect Converter for Large-Capacity Circuit Breaker Testing Application

Circuit breakers (CBs) play an important role in distribution networks. According to IEC standards, protection characteristics need to be investigated to ensure reliability in the manufacturing process. It is required from IEC 60947 that the instantaneous release shall be verified with a test current at least 10 times greater than the rated current. For large-capacity CB testing, converters with large output current, high accuracy and fast response are needed. A large current indirect converter including four converting units and a matrix transformer is proposed. The converting units are synchronized using a complex programmable logic device (CPLD)-based logic control unit. To increase the current accuracy, an adaptive feedforward control strategy is developed to compensate for the influences of CB-dependent resistances and inductances. The equivalent load impedance is adaptively identified from a robust identifier, which is then used to construct the feedforward compensator. Simulation and experimental results show that different CBs create CB-dependent contact resistances and inductances in the testing circuit. The impedance change can be successfully identified by the robust identifier with limited errors. The proposed converter is capable of generating a wide range of current from 100 A to 40 kA with an error no greater than 2.2%.

The Design of SVPWM Waveform Generator Based on CPLD_DSP

Space vector pulse width modulation (SVPWM) control technology could obtain quasi circular rotating magnetic field by switching the space voltage vector of the inverter. Under the condition of low switching frequency, the performance of AC motor was better than that of sine wave pulse width modulation. When this technology was applied to inverter control system, better output voltage waveform could be obtained than conventional six step waveform. And in order to further improve the control performance of the motor, it was very necessary to design SVPWM waveform generator. The design of SVPWM waveform generator based on Complex Programmable Logic Device and Digital Signal Processing (CPLD_DSP) was introduced in the article. The main idea of SVPWM was to synthesize reference voltage vector by switching space voltage vector of inverter. Time holding data and sector number could be calculated from coordinate switch of Voltage gathered from inverter by DSP. And the data was sent into CPLD. SVPWM waveform was generated by state machine programed in VHDL. Finally program was download in CPLD chip named EPM1270T144C5N. The transformation from time signal to SVPWM switch signal was finished successfully. The three phrase output signal had good coherence. Thus the controlling function of the motor control system was improved in a certain extent.

Graph of Outputs in the Process of Synthesis Directed at CPLDs

The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.

Development and Optimization Design of Digital Logic device based on FPGA

FPGA is the abbreviation of Field Programmable Gate Array. The corresponding CPLD is the abbreviation of complex Programmable Logic device. So sometimes the difference can be ignored, collectively called programmable logic devices or CPLD/PGFA. FPGA has a universal structure of masked programmable gate arrays, which is arranged by logical function blocks and connected by programmable interconnection resources to implement different designs. The basic function of a digital electronic clock based on FPGA is designed, simulated and realized by using digital electronic technology, such as FPGA and so on.