Complex Printed Circuit Boards Research Articles

Improved Ground Radiation Antenna Performance for a Vertically Attached PCB

A small, loop-type ground radiation antenna for 2.4-GHz WLAN applications in the complex ground with two vertically attached printed circuit boards (PCBs) was designed. In the presence of a vertical PCB (sub-PCB), the antennas in two different positions, far from and near the sub-PCB, were designed. The current distribution of the complex PCB was stronger near the sub-PCB. Therefore, the coupling between the antenna and the complex PCB was stronger when the antenna was located near the sub-PCB. The antenna close to the sub-PCB obtained more than twice the 3:1 VSWR bandwidth and the efficiency bandwidth than the distant antenna.

Surrogate Modeling for Creep Strain-Based Fatigue Prediction of a Ball Grid Array Component

Abstract In the past years, the finite element analysis (FEA) has proven to be a suitable way for fatigue prediction of electronic equipment based on the physics-of-failure-approach. For this, inelastic strain parameters like creep strain or creep energy density are evaluated in crack susceptible regions of solder joints. Due to the nonlinearity of the creep behavior, which is the basis for these simulations, the computational effort can be significant. This mostly leads to a component-focused approach. Global influences on components like local stiffness variations due to adjacent components, copper traces, or fixations of the printed circuit board (PCB) are often ignored. To make creep-based fatigue predictions suitable for complex printed circuit board assemblies (PCBA), a method for reducing computational effort needs to be established. For this matter, a machine learning-based approach for solder joints has been developed. First, the process for data generation and model training has been established. Thereafter, several methods for input parameter reduction are discussed. Finally, a model is being trained based on the generated simulation data.

Reflow Recipe Establishment Based on CFD-Informed Machine Learning Model

This article proposes a computational fluid dynamics-based machine learning (ML) model to set the temperature of a convection reflow oven and control conveyor speed. Due to the thermal mass variation of printed circuit boards (PCB) and surface mount components, the reflow recipe should be specified for each PCB assembly individually. Instead of relying on process engineers’ skills and experience, the machine learning model supported by heat transfer mechanisms provides a clear and logical path in the reflow recipe setup. An ideal recipe should let the largest component reach the minimum reflow temperature, meanwhile, the temperature cannot damage the small or heat-sensitive components. To simulate the reflow soldering process, the computational fluid dynamics (CFD) model was used after being validated with experiment results. A system was programmed to feed the output of the CFD model as the input to the ML model. Benefiting from the interpolation and fast response brought by ML models, we can rapidly obtain the results subjected to millions of recipes, which are the combination of preset temperatures of all the heating zones and the conveyor speed in the oven. Using a weighting filter function, the optimal recipe can be obtained. This methodology is especially beneficial to reflowing smaller batches of complex PCB assemblies with a big heat capacity.

Impact of THT-hole dimensioning on manufacturability in selective wave soldering

Higher functional integration and increased electrical and reliability requirements are leading to increasingly complex printed circuit board (PCB) designs. Highly integrated PCBs with mixed SMT/THT assembly cause difficulties in soldering processes due to the thermal mismatch between heat demand and heat supply during soldering and the limited accessibility of THT-solder joints. This directly affects the manufacturability and robustness of the THT-soldering process with respect to sufficient hole fill according to typical quality standards like IPC-A-610. Partial hole fill also affects the mechanical reliability and fatigue resistance of a solder joint as well as its current carrying capacity and high frequency behavior. In the literature, several publications show the positive correlation between a larger hole diameter and vertical hole filling. In this paper, the fundamental relationships between hole diameter, hole filling and process robustness are investigated using design of experiments (DoE). It is shown that hole filling increases with increasing hole diameter, while keeping all other parameters constant. It was found that the process also becomes more robust at shorter solder contact times and lowers preheat temperatures. From these results, a general recommendation for larger THT holes in selective wave soldering can be derived. This is consistent with several other literature reports. In contrast to previous publications, it is not only shown how increasing the gap favors hole filling, but also what this means for the robustness of the soldering process to different PCB copper layer designs and soldering parameters. In addition, the impact of hole diameter is evaluated with respect to robotic component placement and back-end processes such as testing. A Gap-Ratio of 30–40 % is recommended for selective wave soldering to ensure robust soldering processes.

Copper recovery through biohydrometallurgy route: chemical and physical characterization of magnetic (m), non-magnetic (nm) and mix samples from obsolete smartphones.

The more modern electronics are, the smaller and complex printed circuit boards are. Thus, these materials are continually changed (physicochemically), increasing the copper concentrations in smartphones. In this sense, it is challenging to set standardized recycling processes to improve metal recovery. In addition, biohydrometallurgy is a clean and cheap process to obtain critical metals from low-grade sources and waste electronic equipment. Therefore, the aim of this work was to characterize, physicochemically, 21 PCBs from smartphones manufactured from 2010 to 2015, and then to recover the copper by Acidithiobacillus ferrooxidans (biohydrometallurgy). The PCBs were comminuted and separated into Magnetic (M), Nonmagnetic (NM) and without magnetic separation (MIX) samples. It was identified 217.8; 560.3 and 401.3mg Cu/g of PCBs for M, NM and MIX samples, respectively. Regarding biohydrometallurgy, the culture media iron-supplemented (NM + Fe and MIX + Fe) increased the copper content by 2.6 and 7.2%, respectively, and the magnetic separation step was insignificant.

Interconnect Fabrication by Electroless Plating on 3D-Printed Electroplated Patterns.

The metallic interconnects are essential components of energy devices such as fuel cells and electrolysis cells, batteries, as well as electronics and optoelectronic devices. In recent years, 3D printing processes have offered complementary routes to the conventional photolithography- and vacuum-based processes for interconnect fabrication. Among these methods, the confined electrodeposition (CED) process has enabled a great control over the microstructure of the printed metal, direct printing of high electrical conductivity (close to the bulk values) metals on flexible substrates without a need to sintering, printing alloys with controlled composition, printing functional metals for various applications including magnetic applications, and for in situ scanning electron microscope (SEM) nanomechanical experiments. However, the metal deposition rate (or the overall printing speed) of this process is reasonably slow because of the chemical nature of the process. Here, we propose using the CED process to print a single layer of a metallic trace as the seed layer for the subsequent selected-area electroless plating. By controlling the activation sites through printing by the CED process, we control, where the metal grows by electroless plating, and demonstrate the fabrication of complex thin-film patterns. Our results show that this combined process improves the processing time by more than 2 orders of magnitude compared to the layer-by-layer printing process by CED. Additionally, we obtained Cu and Ni films with an electrical resistivity as low as ∼1.3 and ∼2 times of the bulk Cu and Ni, respectively, without any thermal annealing. Furthermore, our quantitative experiments show that the obtained films exhibit mechanical properties close to the bulk metals with an excellent adhesion to the substrate. We demonstrate potential applications for radio frequency identification (RFID) tags, for complex printed circuit board patterns, and resistive sensors in a Petri dish for potential biological applications.

Advanced utilization of 3D digital image correlation for thermal and impact reliabilities of electronics components

PurposeThis paper aims to present an adaptation of digital image correlation (DIC) to the electronics industry for reliability assessment of electronic packages. Two case studies are presented: one for warpage measurement of a micro-electro-mechanical system (MEMS) package under different temperature conditions and the other for the measurement of transient displacements on the surface of a printed circuit board (PCB) assembly under free-fall drop conditions, which is for explaining the typical camera setup requirement and comparing among different boundary conditions by fastening methods of PCB.Design/methodology/approachDIC warpage measurements on a small device, such as a MEMS package, require a special speckle pattern. A new method for the creation of speckle patterns was developed using carbon coating and aluminum evaporative deposition. To measure the transient response on the surface of a PCB during a free-fall impact event, three-dimensional (3D) DIC was integrated with synchronized stereo-high speed cameras. This approach enables the measurement of full-field displacement on the PCB surface during a free-fall impact event, contrary to the localized information that is obtained by the conventional strain gage and accelerometer method.FindingsThe authors suggest the proposed patterning method to the small-sized microelectronics packages for DIC measurements. More generally, the idea is to have a thin layer of the dark or bright color of the background and then apply the white or black colored pattern, respectively, so that the surface has high contrast. Also, to achieve a proper size of speckles, this paper does not want to expose the measuring objects to high temperatures or pressures during the sample preparation stage. Of course, it seems a complicated process to use aluminum evaporator, carbon coater and electroformed mesh. However, the authors intend to share one of the solutions to achieve a proper pattern on such small-sized electronic packages.Originality/value3D DIC technique can be successfully implemented for the measurement of micro-scale deformations in small packages (such as MEMS) and for the analysis of dynamic deformation of complex PCB.

MODERNIZATION OF COMPUTER-AIDED DESIGN OF PRINTED CIRCUIT BOARDS WITH INTRODUCTION OF ADDITIONAL FUNCTIONALITY

The paper considers the possibility of introducing additional functionality in Computer‑aided design systems (CAD) which can be used for the design of printed circuit boards (PCB). Two fundamentally different CAD systems were considered for this purpose: Xpedition Enterprise and Altium Designer. Each of the reviewed CAD systems has its advantages and disadvantages. The first has a complex interface and branched program structure, but at the same time provides the user with almost unlimited possibilities in the design of printed circuit boards. The second has a clear interface and simple program structure, but it has limitations in the design of complex printed circuit boards. Despite its shortcomings in both CAD systems, it is possible to implement additional functionality by writing new scripts in a programming language. This article describes the use of the internal development environment in Xpedition Enterprise. A script was written on VBScript language which perform count vias in a PCB project. The development of new scenarios in CAD can greatly simplify the work of topological engineers and accelerate the development of PCB designs.

Closed-Loop Recycling of Copper from Waste Printed Circuit Boards Using Bioleaching and Electrowinning Processes

In the present study, a model of closed-loop recycling of copper from PCBs is demonstrated, which involves the sequential application of bioleaching and electrowinning to selectively extract copper. This approach is proposed as part of the solution to resolve the challenging ever-increasing accumulation of electronic waste, e-waste, in the environment. This work is targeting copper, the most abundant metal in e-waste that represents up to 20% by weight of printed circuit boards (PCBs). In the first stage, bioleaching was tested for different pulp densities (0.25–1.00% w/v) and successfully used to extract multiple metals from PCBs using the acidophilic bacterium, Acidithiobacillus ferrooxidans. In the second stage, the method focused on the recovery of copper from the bioleachate by electrowinning. Metallic copper foils were formed, and the results demonstrated that 75.8% of copper available in PCBs had been recovered as a high quality copper foil, with 99 + % purity, as determined by energy dispersive X-ray analysis and Inductively-Coupled Plasma Optical Emission Spectrometry. This model of copper extraction, combining bioleaching and electrowinning, demonstrates a closed-loop method of recycling that illustrates the application of bioleaching in the circular economy. The copper foils have the potential to be reused, to form new, high value copper clad laminate for the production of complex printed circuit boards for the electronics manufacturing industry.Graphic

TDD‐net: a tiny defect detection network for printed circuit boards

Tiny defect detection (TDD) which aims to perform the quality control of printed circuit boards (PCBs) is a basic and essential task in the production of most electronic products. Though significant progress has been made in PCB defect detection, traditional methods are still difficult to cope with the complex and diverse PCBs. To deal with these problems, this article proposes a tiny defect detection network (TDD-Net) to improve performance for PCB defect detection. In this method, the inherent multi-scale and pyramidal hierarchies of deep convolutional networks are exploited to construct feature pyramids. Compared with existing approaches, the TDD-Net has three novel changes. First, reasonable anchors are designed by using k-means clustering. Second, TDD-Net strengthens the relationship of feature maps from different levels and benefits from low-level structural information, which is suitable for tiny defect detection. Finally, considering the small and imbalance dataset, online hard example mining is adopted in the whole training phase in order to improve the quality of region-of-interest (ROI) proposals and make more effective use of data information. Quantitative results on the PCB defect dataset show that the proposed method has better portability and can achieve 98.90% mAP, which outperforms the state-of-arts. The code will be publicly available.

Near-Field Scanning and Propagation of Correlated Low-Frequency Radiated Emissions

Electromagnetic radiation from complex printed circuit boards can occur over a broad frequency bandwidth, ranging from hundreds of megahertz to tens of gigahertz. This is becoming a critical issue for assessment of EMC and interoperability as electronic components become more and more integrated. We use emissions from an enclosure with a single-slot aperture and equipped with operating electronics to exemplify and model such sources. Spatial correlation functions obtained from two-probe measurements are used both to characterize the source and to propagate the emissions. We examine emissions in the submicrowave frequency range, where evanescent decay dominates the measured correlation function at the distances measured. We find that an approximate, diffusion-like propagator describes the measured emissions well. A phase-space approach based on Wigner functions is exploited to develop this approximation and to provide enhanced understanding of the emissions.

Sequential combined thermal cycling and vibration test and simulation of printed circuit board

Automotive environment generates vibration and temperature fluctuation, which can be damaging for electronic boards. Furthermore, combined temperature and vibration is a type of testing that recreates environments approximating more closely operating environments. In this paper, vibration tests are performed during thermal cycling to investigate the influence of temperature on Printed Circuit Board (PCB) responses. A combined test of temperature and vibration is designed to evaluate the PCB response after each step of one thermal cycle [−40/125] °C. The frequency and displacement can be linked to the strain and strain rate during a board level vibration test. They are obtained from the acceleration during a sine sweep application on a shaker, which is measured using a light weight accelerometer. Experimental results show that temperature significantly affects the PCB responses. Temperature variation leads to striking differences in vibration loading intensity. The PCB first natural frequency shifts from 328 Hz to 313 Hz with temperature increase from 25 °C to 125 °C. A complex PCB is characterized using tension and flexure tests at different temperatures, to extract user input parameter for simulations. An accurate numerical model for sequential combined thermal cycling and vibration simulation is developed and validated using experiments. Thanks to these simulations, the displacement evolution due to combined loading is possible.

Assessment of Joule Heating and Temperature Distribution on Printed Circuit Boards Via Electrothermal Simulations

A printed circuit board (PCB) comprises a solid piece of dielectric material with embedded layers of current carrying metal traces and vias. Geometric features of these metal traces and vias in modern PCBs are highly nonuniform and complicated such that the card level or system level numerical simulations by using the actual trace and via geometries are computationally expensive. The present study investigates the effects of Joule heating in current carrying traces on the temperature distribution of PCBs by conducting one-way and two-way direct current (DC) electric and computational fluid dynamics (CFD) simulations. DC electric field simulations are performed to determine the power map of trace layers which are modeled as planar heat generating sources by using the temperature-dependent electrical conductivity of the metal trace. The power distribution varies with the implemented size and power thresholds. Thermal conductivity map of the PCB is determined by using the electronic computer-aided design (ECAD) images of the individual layers. By using these planar source and thermal conductivity maps, CFD simulations are conducted to determine the resulting temperature distribution on the board. A methodology is developed and applied to a sample, complex PCB, and the generated results are compared with those of the previous studies and conventional models. The computational data show that the temperature distributions over the PCB and its mounted components experience large variations based on the implemented thermal conductivity mapping and the Joule heating modeling technique.

Application of a New Power Distribution Scheme for Complex Printed Circuit Boards for High-Speed Signaling

This paper presents a new power distribution scheme using power transmission lines (PTLs) applied to complex printed circuit boards. The structure consists of three daughter cards stacked on a motherboard where the board–board connectors used for connection are highly inductive. We show that in spite of the inductive connections, good signal integrity (SI) and power integrity (PI) are possible without relying too much on decoupling capacitors. This is achieved using a combination of PTL that replaces the voltage planes and current steering techniques. The PTL scheme described in this paper can be used for high-speed digital signaling. The SI and PI are demonstrated for up to 3-Gbit/s transmission between the boards.

RADIATED NEAR-FIELD EMISSION EXTRACTION ON 3D CURVILINEAR SURFACES FROM 2D DATA

This paper deals with a fast and simple computational method of 3D near-field (NF) radiation from 2D planar frequency- and time-dependent data. The established calculation method can be used to predict the electromagnetic (EM) emission from various types of electronic devices. The proposed method is originally applicable to the computation of the EM NF along the arbitrary shaped curvilinear 3D surface of multi-shape objects. The EM computation consists in the application of the planar NF-to-NF transform using plane wave spectrum. The relevance of the established method is verified with three different validation tests of analytical and practical demonstrations. The first validation is based on the analytical NF radiation from set of elementary dipoles excited by a harmonic signal. The second validation test is based on the experimented data from a hybrid active printed circuit boards (PCBs) in the frequency domain. The last validation test is performed with the measured NF data from a microstrip planar circuit in the time-domain. For all the different test cases, the plots of EM NF on arbitrary curvilinear surfaces are presented. Applications with 3D visualization or holographic surface with arbitrary geometry of EM radiation from planar data in both frequency- and time-domains confirm the effectiveness of the proposed method to predict the EM NF emission from complex PCBs. The developed 2D-to-3D computational method is particularly useful for radiated EM compatibility engineering.

Escape Routing for Staggered-Pin-Array PCBs

To accommodate the ever-growing pin number of complex printed circuit board (PCB) designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. A linear programming/integer linear programming-based algorithm is presented to solve the staggered-pin-array escape routing problem. Experimental results show that our approach successfully routes all test cases efficiently and effectively.

Modeling Printed Circuit Board Curvature in Relation to Manufacturing Process Steps

This paper presents an analytical method to predict deformations of Printed Circuit Boards (PCBs) in relation to their manufacturing process steps. Classical Lamination Theory (CLT) is used as a basis. The model tracks internal stresses and includes the results of subsequent production steps, such as bonding, multilayer press cycles and patterning processes. The aim of this research is to develop a model that can be applied to predict laminate deformations in the production of complex PCBs. Initial experimental results of simplified test specimens show that the modeling approach is valid and capable of accurately predicting laminate deformations for standard bi-layer bonding and multiple press cycles. In the future, the evolved model can be used to analyze PCB manufacturing processes and optimize PCB design.

Modeling Electromagnetic Emissions From Printed Circuit Boards in Closed Environments Using Equivalent Dipoles

In this paper, a method for representing electromagnetic emissions from a printed circuit board (PCB) using an equivalent dipole model deduced from near-field scanning is proposed. The basic idea is to replace the PCB with a set of infinitesimal dipoles that generate the same radiated fields. Parameters of the equivalent dipoles are determined by directly fitting to the measured magnetic near fields. In closed-environment simulations, the equivalent method is extended to a dipole-dielectric conducting plane model to account for the interactions between the PCB and enclosure by including the basic physical features of the PCB. The electromagnetic emissions can then be predicted by solving the equivalent model with numerical methods, thereby, significantly reducing the simulation time and storage costs. A basic test board and a more complex practical telemetry PCB are modeled in different configurations and compared with measurements and full-field simulations, confirming the validity and efficiency of the model.

Test Access Port & Scan Based Technique of In-System Timing Extraction and Control

Historically, most Printed Circuit Board (PCB) testing was done using bed-of-nail in-circuit test equipment. The progress in the field of miniaturization and integration density has possible to design very complex PCBs, which presents very high testability requirements. Boundary scan is now the most promising technology for testing high complexity PCBs. This paper presents scan-based test access port standard for testing complex ICs and also presents a method which allow the extraction of fine-grained timing information using Test Access Port (TAP).

Fast and Accurate Multi-Layer PDN Analysis for Power Integrity and EMC

Views Icon Views Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Icon Share Twitter LinkedIn Tools Icon Tools Get Permissions Cite Icon Cite Search Site Citation Bruce Archambeault, Ketan Shringarpure, Jun Fan, Sam Connor; Fast and Accurate Multi-Layer PDN Analysis for Power Integrity and EMC. International Symposium on Microelectronics 1 January 2010; 2010 (1): 000566–000571. doi: https://doi.org/10.4071/isom-2010-WP2-Paper1 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu nav search search input Search input auto suggest Search