Complex Instruction Research Articles

Where knowledge construction, equity, and context intersect: Student learning of science in small groups

To provide insight into the strengths and limitations of using groupwork to promote excellence and equity in science education, the researcher investigated how students using the Complex Instruction model of groupwork constructed scientific knowledge. Eighty sixth-grade students and one life science teacher at an urban middle school participated in this study. Qualitative analysis of videotapes and interviews makes clear that group discussions rarely moved beyond observational or procedural matters, that students of high status (perceived academic ability and popularity) had greater access to their groups' materials and discourse, and that students made few connections among the contexts of school, science, and everyday life. Quantitative analyses of participation during groupwork and performance on unit tests show that high-status students had significantly higher rates of on-task talk than their middle- or low-status counterparts, and that those students who talked more learned more as well. Thus, although groupwork should not be summarily dismissed as an instructional strategy, group tasks and implementation must be further refined to adequately address the dual goals of excellence and equity: Students need greater guidance in how to talk and do science, and teachers, greater assistance in eliminating differences in student participation and achievement. © 1997 John Wiley & Sons, Inc. J Res Sci Teach 34: 1039–1065, 1997.

Implementing the Science Teaching Standards Through Complex Instruction: A Case Study of Two Teacher‐Researchers

In this case study, an “interpretive collaborative” methodology is applied. The experiences of two elementary teacher‐researchers are described, as they explore science teaching and learning in their two nongraded primary classrooms through the process of complex instruction. This study involves three strands: the theoretical base of complex instruction, the on‐going collaboration between two experienced teachers, and the Science Teaching Standards in relation to complex instruction. Findings suggest that, because the teacher's role in conducting complex instruction activities is multifaceted and complex, successful implementation of complex instruction and the National Science Education Standards required ongoing collaboration and support among teachers. The teacher‐researchers reported that it was their collegial relationship that encouraged them to explore, prepare, and implement inquiry activities or tasks for their students.

Restructuring Schools: Promising Practices and Policies

Introduction (M.T. Hallinan). Achievementoriented School Design (J.S. Coleman). Reforming Education: A Critical Overlooked Component (A.C. Kerckhoff). Lessons from Catholic High Schools on Renewing Our Educational Institutions (A.S. Bryk). Ideology and Organizations: Private Education in PostCommunist Poland (B. Heyns). School Choice in New York City: Preliminary Observations (P. Cookson, Jr., C. Lucks). Lost in Translation: Applying Total Quality Management to Schools, Colleges, and Universities (A.M. Pallas, A. Neumann). Creating Linkages in the High SchooltoWork Transition: Vocational Teachers' Networks (J. Rosenbaum, S.A. Jones). Talking and Working Together: Conditions for Learning in Complex Instruction (E. Cohen et al.). Local Constraints on Opportunity to Learn Mathematics in High School (J. Manlove, D. Baker). Tracking Students for Instruction: Consequences and Implications for School Restructuring (A. Gamoran, M.T. Hallinan). Academic Challenge, Motivation, and Self Esteem: The Daily Experiences of Students in High School (B. Schneider, S. Knauth). Overview (M.T. Hallinan). Index.

Superscalar and superpipelined microprocessor design, and simulation: a senior project

An undergraduate senior project to design and simulate a modern central processing unit (CPU) with a mix of simple and complex instruction sets using a systematic design method is presented. The main objectives of the project are to accustom students to modern design methods as well as to help them gain practical experience in designing digital computers. Findings and suggestions on the use of modern work and design concepts in a group profit environment are discussed.

The microprocessor today

Outlines technology and business issues in today's microprocessor industry. From their humble beginnings 25 years ago, microprocessors have proliferated into an astounding range of chips, powering devices ranging from telephones to supercomputers. Today, microprocessors for personal computers get widespread attention-and have enabled Intel to become the world's largest semiconductor maker. In addition, embedded microprocessors are at the heart of a diverse range of devices that have become staples of consumers worldwide. Microprocessors have become specialized in many ways. Those for desktop computers fall into classes based on their instruction set architectures: either x86, the primary surviving complex instruction set computing (CISC) architecture, or one of the five major reduced instruction set computing (RISC) architectures-PA-RISC, Mips, Spare, Alpha, and PowerPC. Such chips typically integrate few functions other than cache memory and bus interfaces with the processor but usually include a floating-point unit and memory management unit. Embedded microprocessors, on the other hand, typically do not have floating-point or memory management units but often integrate various peripheral functions with the processor to reduce system cost.

A RECONFIGURABLE SYSTOLIC TORUS FOR ITERATIVE MATRIX OPERATIONS

This paper discusses the efficient implementation of iterative matrix operations on application specific processor arrays. Recursive equations, frequently met in a wide range of problems, can be solved through a new systolic structure, the Reconfigurable Systolic Torus, in almost optimal Area and Time requirements. Moreover, flexibility is maintained with no demand of complex instruction sets or extensive control units implemented inside the systolic cells. The general design together with the computation schedules are presented and the description of this new structure is gradually built towards the satisfaction of some basic predefined criteria.

Enhancing academic achievement through cooperative learning. How it works

Abstract An educational application inspired by social constructivism, such as can be found in the theories of Vygotzky (1962, 1978) and Piaget (1925), was attempted, in order to improve the academic achievement of children studying in a heterogeneous class. A MANOVA analysis based on a study of 1046 pupils (8 to 11 years old, studying in 36 classrooms) shows that teaching within the framework of a cooperative learning program named ‘Complex Instruction’, when compared to frontal instruction, improves academic achievement, especially that of lower level children. Improvement seems to be primarily the result.of students’ verbal interaction, while non‐interaction is either not related or related negatively.

Pregnancy registry system. A model database system for collection, dissemination, and analysis of data in multiple international prenatal drug exposure registries

One of the most common types of architecture has been based on the classical Von Neumann structure extended with features to support high-level languages or operating system execution. The most frequent additions are a stack for subroutine calls, virtual memory support, multitasking support through special instructions, addressing modes to facilitate array and record accessing, user/supervisor modes, and a richer variety of data types. To accommodate all these functions, these machines implement a large number of instructions, typically 200–300. Because of their complexity, the instructions of this type of system require several machine cycles for their execution, which is why these types of machine are called complex instruction set computers. For applications that do not require maximum performance, for single-user environments or for multiuser environments that do not require a high level of security or integrity, this approach is convenient and sufficient. The chapter presents four commercial systems that require the state of the art for this type of architecture: (1) Motorola MC68020, (2) Motorola MC68030, (3) National semiconductor NS32000 series, and (4) Zilog Z80000.

BURS automata generation

A simple and efficient algorithm for generating bottom-up rewrite system (BURS) tables is described. A small code-generator generator implementation produces BURS tables efficiently, even for complex instruction set descriptions. The algorithm does not require novel data structures or complicated algorithmic techniques. Previously published methods for on-the-fly elimination of states are generalized and simplified to create a new method, triangle trimming, that is employed in the algorithm. A prototype implementation, burg, generates BURS tables very efficiently.

CISC, RISC and DSP processors in real-time signal processing and control

This paper presents an investigation into the performance evaluation of advanced complex instruction set computer (CISC) processors, reduced instruction set computer (RISC) processors and digital signal processing (DSP) devices in the real-time implementation of signal processing and control algorithms. The algorithms considered are of varying degree of regularity relative to one another. These include a fast Fourier transform algorithm, a second-order correlation algorithm, two adaptive filtering algorithms, a simulation algorithm of a flexible manipulator system and simulation, identification and active vibration control algorithms of a flexible beam system. The algorithms are implemented on an 80486DX2 CISC processor, an 80386DX CISC processor, a SPARC TMS390S10 RISC processor, a T805 RISC processor, an 80i860 RISC processor and a TMS320C40 DSP device. The hardware and software resources and capabilities of the processors and the characteristics of the algorithms are discussed to provide a matching between the algorithms and the architectures. Finally, a comparison of the results of the implementations, on the basis of real-time computation performance, is made and discussed.

RISC versus CISC

The author carries out a comparison of CISC (complex instruction set computing) and RISC (reduced instruction set computing). The author discusses what RISC is and its shortcomings. The evolution of CISC and RISC microprocessors is then discussed and prospects for the future are examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The hypercube of innovation

Innovation has frequently been categorized as either radical, incremental, architectural, modular or niche, based on the effects which it has on the competence, other products, and investment decisions of the innovating entity. Often, however, an innovation which is, say, architectural at the innovator/ manufacturer level, may turn out to be radical to customers, incremental to suppliers of components and equipment, and something else to suppliers of critical complementary innovations. These various faces of one innovation at different stages of the innovation value-added chain are what we call the hypercube of innovation. For many high-technology products, a technology strategy that neglects these various faces of an innovation and dwells only on the effects of the innovation at the innovator/manufacturer level can have disastrous effects. This is especially so for innovations whose success depends on complementary innovations, whose use involves learning and where positive network externalities exist at the customer level. We describe the hypercube of innovation model and use it to examine RISC (Reduced Instruction Set Computers) and CISC (Complex Instruction Set Computers) semiconductor chips, and supercomputers, and suggest how firms can better manage the relationships along the innovation value-added chain using the model. The model forces innovation managers to think in terms of their customers, suppliers and complementary innovators.

A high speed software implementation of the Data Encryption Standard

This paper describes a very fast software implementation of the Federal Data Encryption Standard (DES) for the 80–786 processor family. The complex instruction set of this processor family is exploited to implement the low-level bit manipulation of the DES in an efficient manner. A 386/33 MHz PC is capable of data rates of over 200 kpbs, including time taken to read from and write to hard disk.

Copper Metallization Technology for Deep Submicron ULSIs

Investment in high-performance and large-scale integration (LSI) has been increasing and low-cost fabrication equipment, simple processing, and short turnaround are big concerns. The propagation delay time in a device is reduced with a reduction in device size, and wiring delay becomes longer than device delays. Wiring then has become as important as the device itself. Future multilevel wiring will require five to seven levels. The multilayer wiring itself will not be easy to achieve, because of increased wiring cost, process complexity, and longer turnaround. We must overcome these problems.The materials required for wiring so that ULSI performance and reliability in RISC (reduced instruction set computer), and CISC (complex instruction set computer) type processors and DSPs (digital signal processors) can be increased must have a lower resistivity and higher resistance to electromigration (EM) and stress migration (SM) than do aluminum alloys. Gold, copper, and silver are candidate wiring materials. Copper is especially attractive, but we must overcome several obstacles to take advantage of its potential.This article will discuss wring and via resistance delay, Cu CVD technology, the surface reaction mechanism, copper patterning technology, copper oxidation and diffusion prevention, and copper wiring reliability.

The commercialization of RISC: Strategies for the creation of dominant designs

Reduced instruction set computers (RISC) recently have mounted a strong challenge to the complex instruction set computers (CISC) that previously dominated the computer workstation industry. This change has had a tremendous impact on systems developers, and may have far-reaching implications for the structure of the U.S. microprocessor industry. Intel and Motorola, who dominate the CISC microprocessor market, ignored or failed to respond to early evidence of the advantages of RISC architectures and have lost the initiative in this fast-growing market to Sun Microsystems and other producers of workstations who have developed RISC microprocessors. This paper discusses the development and commercialization of RISC architectures, focusing on the licensing strategies of Sun and MIPS Computer Systems, two pioneers in RISC microprocessors. Rather than an exogenous event, to which managers must adapt, the history of RISC suggests that firms can pursue strategies that aid in the establishment of their products as dominant designs. In the case of RISC, licensing has assumed particular significance because of the important complementarities between hardware and applications software, which results in network externalities. In such technologies, the innovator may gain significant advantages from a relatively permissive attitude toward “giving away” important intellectual property.

Using databases to support the development of microcode

The design and verification of microcode for a processor with a complex instruction set can be a complicated task. In this paper it is shown how a standard relational database can be used at various stages to simplify such a design process, as automatic microcode generation is not always suitable for this process. Using the example of a coprocessor for list manipulation, it is demonstrated how the database can be used to enter the microprogram, check various aspects of consistency, generate simulation patterns for the datapath and finally to generate the optimized microcode.

In search of insights into the generation of techno-economic trends: Micro- and macro-constituencies in the microprocessor industry

In the field of technology policy, few challenges are more intriguing than understanding the nature of technical and market trends. This paper deals with this problem by using the sociotechnical constituencies approach in order to integrate the treatment of “micro”/“macro” issues — from product to industry. The case study is that of the microprocessor industry where at present a Risc (reduced instruction set computer) technology is emerging in a field where a powerful and far-from-exhausted Cisc (complex instruction set computer) technology tends to occupy almost every segment of the market. The analysis reveals how emerging product-constituencies do implement pro-active trend-creating strategies in order to establish themselves as industrial trends, and, by so doing, they simultaneously re-define the existing content of the “macro” industrial level. The study also reveals the important role of the nature and maturity of microprocessor technology in conditioning the constituency-building strategies implemented by different players. Microprocessor technology is specifically characterised as an architectural, codified-knowledge component with indirect network externalities and weak appropriability regime. Finally, the paper also highlights the potential risks of both fragmentation and complete proprietary control of technology in technological processes involving strongly competitive situations.

Pressures for change in the global distribution of the microprocessor industry

At present, the world's microprocessor market is completely dominated by the US semiconductor industry. In particular, two companies (Intel and Motorola) have overwhelmingly controlled the development of the market through their dominant 80 × 86 and 68000 Cisc (complex instruction set computer) architectures. This paper shows that this Cisc-based arrangement is now under pressure. The emergence of the new Risc (reduced instruction set computer) microprocessor architecture i n the mid-1980s is bringing a new era of instability to the sector. On the surface, this instability would seem to be very much an internal US affair. The author argues, however, that new opportunities are emerging for other countries or regions to play a greater part in the development of the microprocessor industry. This paper discusses the combination of factors at the heart of this process and a glance is given at the future beyond Risc.

Competitive strategies in the microprocessor industry: the case of an emerging versus an established technology

Risc (reduced instruction set computer) architecture in challenging the dominance of the older Cisc (complex instruction set computer) microprocessor technology. The rise of Risc provides an example of a new, emerging technology struggling against an established one. This paper examines the character and state of development of the two architectural constituencies of Risc and Cisc and the strategies being implemented by their leading players. Both technologies are treated as evolving 'sociotechnical constituencies'. The microchips of which Risc and Cisc are composed are treated as subconstituencies or product–constituencies.

Microprocessor architectures and systems: RISC, CISC and DSP

Part 1 Complex instruction set computers: enter the MC68000 complex instructions, Microcode and Nanocode the MC68000 hardware M68000 asynchronousbus M6800 synchronousbus the user/supervisor concept the MC68010 virtual memory processor MC68010 supervisor resource the MC68008. Part 2 32-bit CISC processors: enter HCMOS technology the MC68020 32-bit performance standard coprocessor interface MC68881 and MC68882 floating point coprocessors the MC68851 paged memory management unit (PMMU) the MC68030, the first commercial 50 MHz. Part 3 The rise challenge: the 80/20 rule the initial RISC research the Berkeley model the Stanford model the catalysts the M88000 family the MC88100 programming model the MC88100 instruction set MC88100 external functions M88200 cache MMU the MBUS protocol M88000 master/checker fault tolerance. Part 4 Digital signal processing: the DSP56000 family move commands. Part 5 Memory, memory management and caches: shadow RAM DRAM v SRAM optimizing the DRAM interface memory management multitasking and user/supervisor conflicts. Part 6 Real time software interrupts and exceptions: interrupting an MC88100 MC88100 interrupt service routines interrupting the DSP56000 triadic instruction sets register windowing the M68300 family. Part 7 Multiprocessing: SISD - single instruction, single data SIMD - single instruction, multiple data MIMD - multiple instruction, multiple data MISD - multiple instruction, single data constructing a MIMD architecture processor bandwidths. Part 8 Application ideas: MC68020 and MC68030 design techniques for high-reliability applications transparent update techniques for digital filters using the DSP56000 motor and servo control. Part 9 Semiconductor technology: semiconductor technology silicon technology CMOS and bipolar technology. Part 10 The changing design cycle: the changing design cycle the shortening design cycle simulation v emulation. Part 11 Generation: enter the MC68040 the instruction execution unit the bus interface unit the M68300 family DSP96000 combining integration and performance once a new approach to emulation integration and higher performance. Part 12 Selecting a microprocessor architecture: meeting performance needs development support considering all the options. Appendices: benchmarking binary compatibility standards.