Complex Bandpass Filter Research Articles

Serial analog QAM modems based on complex band-pass filters with LF Bessel prototypes

The article is devoted to the development and implementation of algorithms for quadrature amplitude modulation and demodulation based on analog complex band pass filters with low-frequency Bessel prototypes. The use of complex Bessel filters makes it possible to obtain orthogonal carrier signals close in shape to symmetric signals with practically non-overlapping spectra. Overview of the development and implementation of a serial QAM modem based on analog complex band-pass Bessel filters. The procedure for obtaining the expression for the impulse response of analog complex band-pass Bessel filters is considered. With the help of circuit simulation, the frequency response and impulse response of such a filter are determined. The choice of the center frequency is carried out by setting two coefficients. A block diagram of a serial data transmission system with quadrature amplitude modulation (QAM) based on analog complex band-pass Bessel filters is proposed. The results of its circuit simulation in the Micro-Cap environment are presented.

Serial Analog-Digital QAM Modems Based on Complex Band-Pass Filters with LF Butterworth Prototypes

The article is devoted to the development and implementation of quadrature amplitude modulation algorithms based on an analog complex band-pass filter with Butterworth low-frequency prototypes. The use of complex Butterworth band pass filters makes it possible to obtain carrier signals with practically non-overlapping spectra. But the analog complex Butterworth filter has a non-linear phase-frequency response and, accordingly, the impulse responses of which are infinite and asymmetric. An overview of the development and implementation of a serial QAM modem based on an analog Butterworth complex band-pass filter and an inverse digital FIR filter. The procedure for obtaining the expression for the impulse response of analog complex band-pass Butterworth filters is considered. With the help of circuit simulation, the frequency response and impulse response of such a filter are determined. The choice of the center frequency is carried out by setting two coefficients. A block diagram of a serial data transmission system with quadrature amplitude modulation based on an analog complex Butterworth bandpass filter and an inverse digital FIR filter is proposed. The results of its circuit simulation in the Micro-Cap environment are presented.

Serial digital QAM-modem based on complex band-pass IIR filters with LF-prototypes of Bessel

The article is devoted to the development and implementation of algorithms for the single-channel sequential quadrature amplitude modulation and demodulation based on digital complex band-pass IIR filters with LF-prototypes of Bessel. The use of complex IIR filters of Bessel allows to obtain orthogonal carrier signals which are close in shape to symmetric signals with practical non-overlapping spectra. The procedure for calculating the 4th-order digital low-pass Bessel filter using the generalized bilinear transformation method, which is used in the theory of digital signal processing to convert a continuous-time system into a discrete-time system, is considered. The variants of implementing the digital complex bandpass filters with a sequential structure using the complex delay method are considered, which allows to obtain the block diagrams of complex bandpass filters without additional calculations and to realize the restructuring of the central frequency without changing the frequency response shape by changing only two coefficients in complex delays. The procedure for obtaining of the expression of the impulse response of digital complex band-pass IIR filters of Bessel is considered. With the help of circuit modeling, the amplitude-frequency response and impulse response of such filter are determined. If the IIR filters are used in the modulator, the pulse characteristics of which are infinite and asymmetric, then it is necessary to use digital complex FIR filters consistent with the truncated pulse characteristic in the demodulator. But as an exception, the Bessel digital IIR filter has a phase-frequency response similar in shape closely to the linear one and, accordingly, a pulse response close to the symmetric one. In this case, the same recursive complex Bessel filters, similar to the filter in the modulator, can be used as matched filters in the demodulator. Therefore, the serial block diagram of the modem contains the same complex band-pass IIR filters with LF-prototypes of Bessel. The choice of the central frequency of the channel digital complex bandpass IIR filter is carried out by setting two coefficients. The results of circuit modeling of the data transmission system with the quadrature amplitude modulation (QAM-16) in the Microcap environment are presented, confirming the operability of the proposed option.

Multiple Delayed Signal Cancellation Filter-Based Enhanced Frequency-Locked Loop Under Adverse Grid Conditions

An accurate and prompt estimation of phase angles, frequency, and magnitudes of the grid voltage is extremely important in paving a good platform for a fast and reliable operation of power grid monitoring, protection, and control. The phase-locked loop (PLL) served this purpose for decades, while the concept of the frequency-locked loop (FLL) has been proposed more recently. Even though the FLL and the PLL share some similarities, some differences still exist. Further research on FLLs can boost their capabilities and open up new windows in designing devices for grid synchronization. Multiple delayed signal cancellation (MDSC) filters are a peculiar system of filters. Their applications to FLLs can enrich FLL’s performance. This article focuses on applying the stationary reference frame MDSC filters at in-loop and prefiltering stages of the FLL and compares its effectiveness with widely used cascaded delayed signal cancellation (CDSC) and complex bandpass filter (CBF) based filtering techniques. The application of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$K$</tex-math></inline-formula> -factor-methodology-based controller design to FLLs has also been explored for dynamic performance enhancements. A new cascaded multiple delayed signal cancellation (CMDSC) filter is proposed and is compared with its CDSC counterpart proposed in the literature to address the effects of dc offsets and imbalances under adverse grid conditions. The effectiveness of the proposed method is verified through OPAL-RT real-time simulations and dSPACE ds1104 and TMS320F28335 microcontroller experimental test bench.

A 0.015mW quasi-passive reconfigurable complex band-pass filter for analog baseband

A 0.015mW quasi-passive reconfigurable complex band-pass filter for analog baseband

Estimated Position Error Suppression Using Novel PLL for IPMSM Sensorless Drives Based on Full-Order SMO

To heighten the position estimation accuracy of sensorless control of interior permanent magnet synchronous motor (IPMSM), an improved full-order sliding mode observer (FSMO) based on novel phase-locked loop (PLL) is proposed in this article. By contrast with the traditional FSMO, the improved FSMO (IFSMO) with piecewise power function has merits of higher estimation accuracy and more chattering suppress capability, which is beneficial to the position sensorless drives. Based on that, to pledge the rotor position observation precision of the IFSMO during wide speed range, a variable sliding mode gain related to the rotor speed is designed. However, due to the inverter nonlinearity and rotor spatial harmonics, the extended back electromotive force contains high-order harmonics, which will reduce the estimation accuracy of PLL and cause notable position error. Therefore, a novel PLL with complex bandpass filter as the preprocessing stage that features high estimation accuracy, high filtering capability, and fast dynamic response is proposed. Meanwhile, the linearized model and parameter design of the proposed PLL is developed, and hence the stability of the designed PLL is analyzed by the derived linearized model. The availability of the proposed sensorless strategy is verified via experiments on 2-kW IPMSM drive.

Field PMU Test and Calibration Method– Part I: General Framework and Algorithms for PMU Calibrator

Laboratory testing of phasor measurement units (PMUs) guarantees their performance under laboratory conditions. However, many factors may cause PMU measurement problems in actual power systems, resulting in the malfunction of PMU-based applications. Therefore, field PMUs need to be tested and calibrated to ensure their performance and data quality. In this paper (Part I), a general framework for the field PMU test and calibration in different scenarios is proposed. This framework consists of a PMU calibrator and an analysis center, where the PMU calibrator provides the reference values for PMU error analysis. Two steps are implemented to ensure the calibrator accuracy for complex field signals: <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\textcircled{1}$</tex> by analyzing the frequency-domain probability distribution of random noise, a Fourier-transform-based signal denoising method is proposed to improve the anti-interference capability of the PMU calibrator; and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\textcircled{2}$</tex> a general synchrophasor estimation method based on complex bandpass filters is presented for accurate synchrophasor estimations in multiple scenarios. Simulation and experimental test results demonstrate that the PMU calibrator has a higher accuracy than that of other calibrator algorithms and is suitable for field PMU test. The analysis center for evaluating the performance of field PMUs and the applications of the proposed field PMU test system are provided in detail in Part II of the next-step research.

A Complex Band-Pass Filter for Low-Power and High-Performance Transceivers

In this paper a low-power and high-performance 2nd-order complex band-pass filter in trans-impedance amplifier (TIA) configuration is presented. Thanks to the adopted topology for the passive network and active-components exceeds current solutions exhibiting a gain as high as 121.5 dB $_Ω$ and 1.57 MHz of bandwidth centered around 1.33 MHz. The output noise is only 630 nV/√Hz. Furthermore, a new fully-differential class-AB operational trans-conductance amplifier (OTA) provides the required current to drive heavy ADC loads with very fast signals while an improved common-mode feedback circuit enables ultra low current without introducing stability and avoids start-up problems. The filter has been integrated in a 90-nm complementary metal oxide semiconductor (CMOS) technology. Despite the high performance and accuracy of the transfer function the power consumption is only 400 μA from a 1.2-V power supply.

A CMOS RF Receiver with Improved Resilience to OFDM-Induced Second-Order Intermodulation Distortion for MedRadio Biomedical Devices and Sensors

A MedRadio RF receiver integrated circuit for implanted and wearable biomedical devices must be resilient to the out-of-band (OOB) orthogonal frequency division modulation (OFDM) blocker. As the OFDM is widely adopted for various broadcasting and communication systems in the ultra-high frequency (UHF) band, the selectivity performance of the MedRadio RF receiver can severely deteriorate by the second-order intermodulation (IM2) distortion induced by the OOB OFDM blocker. An analytical investigation shows how the OFDM-induced IM2 distortion power can be translated to an equivalent two-tone-induced IM2 distortion power. It makes the OFDM-induced IM2 analysis and characterization process for a MedRadio RF receiver much simpler and more straightforward. A MedRadio RF receiver integrated circuit with a significantly improved resilience to the OOB IM2 distortion is designed in 65 nm complementary metal-oxide-semiconductor (CMOS). The designed RF receiver is based on low-IF architecture, comprising a low-noise amplifier, single-to-differential transconductance stage, quadrature passive mixer, trans-impedance amplifier (TIA), image-rejecting complex bandpass filter, and fractional phase-locked loop synthesizer. We describe design techniques for the IM2 calibration through the gate bias tuning at the mixer, and the dc offset calibration that overcomes the conflict with the preceding IM2 calibration through the body bias tuning at the TIA. Measured results show that the OOB carrier-to-interference ratio (CIR) performance is significantly improved by 4–11 dB through the proposed IM2 calibration. The measured maximum tolerable CIR is found to be between −40.2 and −71.2 dBc for the two-tone blocker condition and between −70 and −77 dBc for the single-tone blocker condition. The analytical and experimental results of this work will be essential to improve the selectivity performance of a MedRadio RF receiver against the OOB OFDM-blocker-induced IM2 distortion and, thus, improve the robustness of the biomedical devices in harsh wireless environments in the MedRadio and UHF bands.

2.4-GHz Low-Power Low-IF Receiver With a Quadrature Local Oscillator Buffer for Bluetooth Low Energy Applications

In this brief, a 2.4-GHz low-power single-quadrature low-IF Bluetooth low energy receiver employing a quadrature local oscillator (LO) buffer is presented for Internet of Things applications. The quadrature LO buffer, which consists of common-source amplifiers with capacitive degeneration, compensating resistors, compensating PMOS transistors and LC tanks, performs quadrature generation and supplies quadrature signals to a single-quadrature mixer, thus eliminating an additional circuitry for quadrature generation in the LO path and saving dc current consumption. The implemented receiver consists of a low-noise amplifier, a G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -stage, double-balanced current-mode passive mixers, transimpedance amplifiers, an active- RC complex bandpass filter, and the quadrature LO buffer. Fabricated in a 65-nm CMOS process, the implemented receiver achieves a noise figure of 8.16 dB, a conversion gain of 54.5 dB, an image rejection ratio of 32.1 dB, and an input-referred third-order intercept point of -27.5 dBm. It draws a bias current of 2.5 mA from a nominal supply voltage of 0.8 V, and the active die area is 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

2.4-GHz Bluetooth Low Energy Receiver Employing New Quadrature Low-Noise Amplifier for Low-Power Low-Voltage IoT Applications

In this article, a 2.4-GHz Bluetooth low-energy (BLE) receiver employing a new quadrature low-noise amplifier (LNA) is presented for low-power low-voltage Internet of Things (IoT) applications. The proposed quadrature LNA consists of a common-source (CS) amplifier with inductive degeneration, an active-type poly-phase filter (PPF), and an LC tank. The proposed active-type PPF between the CS amplifier and the LC tank provides quadrature generation, and the CS amplifier determines and optimizes the overall LNA performance parameters. Moreover, the proposed active-type PPF shares the dc bias current with the CS amplifier, thereby eliminating the necessity for additional current consumption. The implemented BLE receiver is composed of the quadrature LNA, a $G_{m}$ -stage, a double-balanced current-mode passive mixer, a transimpedance amplifier, and an active- RC complex bandpass filter. The proposed design was fabricated in a 65-nm CMOS process and mainly characterized in the BLE operating frequency bands. The receiver achieves a noise figure of 8.2 dB, a conversion gain of 49.5 dB, an image rejection ratio of more than 33 dB, and an IIP3 of −25.75 dBm. The active die area of the implemented receiver is 1.16 mm2, and it draws a bias current of 2.7 mA from a nominal supply voltage of 0.8 V.

A General Design Method for Phasor Estimation in Different Applications

Driven by the increasing development and complexity of bulk power systems, the requirements of phasor estimation methods differ for different scenarios and applications. In this study, a general design method for phasor estimation algorithms in different applications is proposed based on a complex finite impulse response (FIR) bandpass filter. A design framework based on mathematical error models is proposed to facilitate the design of a complex bandpass filter for different requirements and to reduce the trial and error process. The general error models between the filter gain and the error limitations of all variables measured by the phasor measurement units (PMUs) are established separately, according to the absolute value inequality. The filter design criteria obtained from the error models can determine the passband and stopband gain range of the complex bandpass filters. Three phasor algorithms for different classes of PMUs are designed, and their performances are validated and compared using experimental tests. The results demonstrate that the proposed method can design phasor algorithms to provide accurate measurements under different scenarios.

A Novel Frequency Estimation Method Based on Complex Bandpass Filters for P-Class PMUs With Short Reporting Latency

The measurement data of P-class phasor measurement units (PMUs) is used for protection and control applications. The reporting latency is critical for these applications. However, the data window of fundamental frequency estimation is commonly longer than that of phasor estimation, which introduces additional latency. In this paper, a novel frequency estimation method that uses sampling values rather than phase angles is proposed for P-class PMUs to reduce their reporting latency. This method uses two complex bandpass filters with different gains to extract the two positive fundamental components of the power signals. A one-to-one correspondence between the frequency and the ratio of the two positive fundamental components is established. By polynomial fitting this relationship, the frequency under static and dynamic conditions can be accurately estimated. In addition, to ensure the accuracy, the two applied complex bandpass filters are designed according to standard requirements, which can effectively suppress the negative fundamental component and harmonics. The simulation and experimental test results show that the proposed method achieves a frequency measurement accuracy that is 10 times higher than the standard requirements with a low computational burden and a data window of two cycles, indicating that the proposed method is suitable for P-class PMUs.

Flexible reconfigurable GNSS RF receiver for portable application of Internet of Things

A fully integrated single input, dual-channel, single-band reconfigurable GNSS radio frequency receiver supporting GPS, BD2 and Galileo systems is designed and implemented in a 0.18 ​μm CMOS process for portable Internet of Things applications. The receiver incorporates a single RF front-end, low-power fractional-N synthesizer, and reconfigurable complex band-pass filter, which can be flexibly configured to receive GPS L1/BD2 B1 or GPS L1/Galileo E1, and any of these signals separately, and can also effectively simplify the design complexity of the receiver and reduce power consumption. Moreover, a flexible frequency plan is employed to meet the different frequency requirements of the receiver. While drawing 16 ​mA current from a 1.8 ​V supply, this RF receiver achieves a total noise figure of 1.79 ​dB, a maximum voltage gain of 108 ​dB, a gain dynamic range of 56 ​dB and the input third-order intercept point of -18.09 dBm and -23.66 dBm at 1575 ​MHz and 1561 ​MHz, respectively, with an active die area of 1.86 ​mm2.

A Compct 5.8 GHz CPW Double Square Edge Antenna With BPF Stepped Impedance Resonator

This research proposes a 5.8 GHz circular polarization double square edge antenna with a bandpass filter that used a method stepped impedance resonator (BPF-SIR) structure for designing a compact integrated antenna with the filter. the double layer electromagnetic circuit structure is used to miniaturize antenna integrated with complex bandpass filter at 5.8 GHz frequency operation. furthermore, a novel electromagnetic component has been developed to produce a 5.8 GHz antenna with good gain value. even this circuit have not complex configuration, and inexpensive material, especially for the premium-frequency.

Low-Power CMOS Complex Bandpass Filter with Passband Flatness Tunability

We present a low-power CMOS active-resistance-capacitance (active-RC) complex bandpass filter (BPF) with tunable gain, bandwidth, center frequency, quality factor, and passband flatness for Bluetooth applications. A transfer function analysis for a cross-coupled Tow-Thomas biquad structure is presented to prove that the flatness profile of the passband gain can be effectively controlled by independently tuning two cross-coupling resistors. The proposed biquad-based complex BPF was employed to realize a fourth-order baseband analog processor for a low intermediate frequency (low-IF) RF receiver. The baseband analog processor was composed of two complex biquad filters and three first-order variable-gain amplifiers. It was fabricated in a 65-nm RF CMOS and achieved wide tuning capabilities, such as a gain of −15.6 to 50.6 dB, a bandwidth of 1.4–3.9 MHz, a center frequency of 1.5–4.1 MHz, and a passband flatness of −1 to 1 dB. It also achieved an image rejection ratio of 40.3–53.3 dB across the entire gain tuning range. It consumed 1.4 mA from a 1 V supply and occupied an area of 0.19 mm2 on the silicon substrate. The implementation results prove that the proposed complex BPF was able to effectively enhance the signal processing performances through the flexible and wide-range tunability of the passband flatness, as well as that of the gain, bandwidth, center frequency, and quality factor.

An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration

This article presents a new analog circuit optimization system for automated sizing of analog integrated circuits. It consists of a genetic algorithm (GA)-based global optimization engine and an artificial neural network (ANN)-based local optimization engine. The key new idea is to use parallel computation to train ANN models for design space neighborhoods thus the local minimum search (LMS) can have a much faster search speed. For the GA-based global optimization, circuit performances are calculated by parallel SPICE simulations. For the LMS, circuit performance data are derived from ANN model predictions instead of SPICE simulations. Since the most time for an ANN-based LMS is spent on SPICE calls which can be run in parallel, the LMS process can also exploit the multiple core configuration of a modern computational server in addition to the GA global search. The fully parallelized optimization system is deployed to design a two-stage rail-to-rail operational amplifier and a fifth-order active-RC Chebyshev complex band-pass filter. The experimental results show that the proposed method provides about four times speed enhancement and comparable results compared with traditional approaches employing the same parallel global optimization but sequential SPICE calls during LMS.

Комплексный полосовой фильтр на базе инвертирующих интеграторов, реализуемых на переключаемых конденсаторах

A new scheme of a complex section with the use of inverting integrators implemented on two operational amplifiers, capacitors and switches is described. A procedure for calculating complex band-pass filters based on complex sections implemented using switched capacitors is considered. As an example, two basic schemes of a complex band-pass filter with a low-frequency Butterworth prototype of the 3rd order are developed. The first scheme is implemented on the basis of operational amplifiers and RC elements, and the second scheme contains operational amplifiers, capacitors and switches. The circuit solutions of the complex filters were simulated in the Micro- Cap software environment. Amplitude-frequency responses (AFRs) of complex filter were calculated for both the first and the second schemes. The frequency responses of both filters were found to be almost identical with each other. Conversion of an impulse signal was simulated in the time domain. Both filters produced the same output signals. The simulation results have confirmed the efficiency of the proposed method for calculating complex filters on switched capacitors.

A CMOS RF BeiDou-1 Transceiver for Regional Positioning and Short Message Service Applications

This paper presents a fully integrated CMOS radio-frequency (RF) transceiver for BeiDou-1, a radio determination satellite service system which can provide regional positioning and short message service. The proposed transceiver incorporates a low-IF receiver and a BPSK transmitter to realize a dual-way communication between users and the central control station via satellites. The receiver (RX) RF front-end down-converts the 2491.75 MHz RF signals to a 12.24 MHz IF band with a bandwidth of 8.16 MHz. The complex band-pass filter utilizes passive compensation technique to compensate the phase lag and achieve in-band flatness. The 4.08 Mchip/s baseband signal alternatively selects one of the differential 1615.68 MHz local signals to achieve BPSK modulation for the transmitter (TX). Besides, on-chip low dropout regulators adopt improved power supply rejection ratio techniques by integrating active filtering to obtain stable 1.5 V supply voltages. The transceiver is fabricated in a 130 nm CMOS technology and occupies an area of 5.88 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with electrostatic discharge circuitry and pads included. The RX channel achieves a 106 dB maximum voltage gain with a 65 dB dynamic range, a 4.95 dB noise figure and a 46 dB image rejection ratio. The output power for the TX ranges from -10 dBm to 5 dBm, with a phase error less than 1.5 degree.

A Low-Voltage Multi-Band ZigBee Transceiver

This paper presents a low-voltage ZigBee transceiver covering a unique frequency band of 780/868/915/2400 MHz in 180 nm CMOS technology. The design consists of a receiver with a wideband variable-gain front end and a complex band-pass filter (CBPF) based on poles construction, a transmitter employing the two-point direct-modulation structure, a Ʃ-Δ fractional-N frequency synthesizer with two VCOs and some auxiliary circuits. The measured results show that under 1 V supply voltage, the receiver reaches −93.8 dBm and −102 dBm sensitivity for 2.4 GHz and sub-GHz band, respectively, and dissipates only 1.42 mW power. The frequency synthesizer achieves −106.8 dBc/Hz and −116.7 dBc/Hz phase noise at 1 MHz frequency offset along with 4.2 mW and 3.5 mW power consumption for 2.4 GHz and sub-GHz band, respectively. The transmitter features 2.67 dBm and 12.65 dBm maximum output power at the expense of 21.2 mW and 69.5 mW power for 2.4 GHz and sub-GHz band, respectively.