Complementary Metal Oxide Semiconductor Techniques Research Articles

Comparative Analysis of High Speed and Area Efficient Full-Adder using CMOS and MGDI Techniques

Extremely quick processing is crucial for very large-scale integrated (VLSI) circuits in the arithmetic logic unit. Complementary metal oxide semiconductor (CMOS) and modified gate diffusion input (MGDI) are beneficial technologies for designing high-speed circuits with better reliability and performance with regard to area and power consumption. This research work provides a comparative performance analysis of a full adder that is implemented with CMOS and MGDI technology. This work aims to develop a CMOS-based full-adder and a MGDI-based full-adder circuit for area-efficient and high-speed applications. First, the analysis and implementation of the XOR and NAND logic gates are designed using CMOS technology and the MGDI technique to create a full-adder design. The comparative analysis of integrated circuits in CMOS and MGDI technologies is primarily determined by the number of transistors and delay time. The full-adder is designed and analyzed using 90 nm technology, with performance characteristics evaluated using Cadence Virtuoso Tools.

Design of high efficient low power static logic circuit using SG FinFET

ABSTRACT The increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor (CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, gate oxide tunneling leakage current, sub threshold leakage current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS technology (SLC-SG-FinFET-INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET-INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using noise margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS technology (SLC-SCLSB-22 nm CMOS), and static logic circuit using computational digital low dropout in 22 nm CMOS technology (SLC-CDLDO-22 nm CMOS) methods, respectively.

Single-bit comparator in quantum-dot cellular automata (QCA) technology using novel QCA-XNOR gates

To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor (CMOS) technology developers. The scaling scenario is not an option nowadays and other technologies need to be investigated. The quantum-dot cellular automata (QCA) technology is one of the important emerging nanotechnologies that have attracted much researchers’ attention in recent years. This technology has many interesting features, such as high speed, low power consumption, and small size. These features make it an appropriate alternative to the CMOS technique. This paper suggests three novel structures of XNOR gates in the QCA technology. The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology. The proposed structures are used as the main building blocks for a single-bit comparator. The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature. The comparison results are encouraging to append the proposed structures to the library of QCA gates.

Physical vapor deposited 2D bismuth for CMOS technology

Two-dimensional (2D) bismuth, bismuthene, is an emerging pnictogen family member that has received increasing research attention in the past few years, which could yield exotic electrical, thermal, and optical properties due to unique band structure. This review provides a holistic view of recent research advances on 2D bismuth material synthesis and device applications in complementary metal oxide semiconductor (CMOS) technology. Firstly, the atomic and band structure of bismuthene is reviewed as the fundamental understanding of its physical properties. Then, it highlights material synthesis of 2D bismuth atomic sheets with emphasis on physical vapor deposition method with accurate layer controllability and process compatibility with CMOS technology. Moreover, it will survey latest applications of 2D bismuth in terms of electronic, optic, thermoelectric, spintronic and magnetic nanodevices. 2D bismuth derivatives (Bi–X, X = Sb, Te, Se) will also be mentioned as a promising strategy to further improve device performance. At last, it concludes with a brief summary on the current challenges and future prospects in 2D bismuth and its derivatives for innovative electronics, sensors and other devices compatible with CMOS techniques.

Novel Area-efficient Null Convention Logic based on CMOS and Gate Diffusion Input (GDI) Hybrid

Null convention logic (NCL) is a promising delay insensitive paradigm for constructing asynchronous circuits. Traditionally, NCL circuits are implemented utilizing complementary metal oxide semiconductor (CMOS) technology that has large area overhead. To address this issue, a HYBRID methodology is introduced for realizing NCL circuits in this paper. The proposed approach utilizes both CMOS and gate diffusion input (GDI) techniques to significantly reduce the area. Compared with the conventional static CMOS NCL counterpart, the HYBRID implementation of an NCL up counter demonstrate an average of 10% reduction in the transistor count.

A Silicon Nanowire Array Biosensor Fabricated by Complementary Metal Oxide Semiconductor Technique for Highly Sensitive and Selective Detection of Serum Carcinoembryonic Antigen.

In this paper, we present a highly sensitive and selective detection of serum carcinoembryonic antigen (CEA) based on silicon nanowire (SiNW) array device. With the help of traditional microfabrication technology, low-cost and highly controllable SiNW array devices were fabricated. After a series of surface modification processes, SiNW array biosensors show rapid and reliable response to CEA; the detection limit of serum CEA was 10 fg/mL, the current signal is linear with the logarithm of serum CEA concentration in the range of 10 fg/mL to 100 pg/mL. In this work, SiNW array biosensors can obtain strong signal and high signal-to-noise ratio; these advantages can reduce the production cost of the SiNW-based system and promote the application of SiNWs in the field of tumor marker detection.

Polarization-selective uncooled infrared sensor with asymmetric two-dimensional plasmonic absorber

A polarization-selective uncooled infrared (IR) sensor was developed based on an asymmetric two-dimensional plasmonic absorber (2-D PLA). The 2-D PLA has an Au-based 2-D periodic dimple structure, where photons can be manipulated by spoof surface plasmon polaritons. Asymmetry was introduced into the 2-D PLA to realize a polarization selective function. Numerical investigations demonstrate that a 2-D PLA with ellipsoidal dimples (2-D PLA-E) gives rise to polarization-dependent absorption properties due to the asymmetric dimple shape. A microelectromechanical systems-based uncooled IR sensor was fabricated using a 2-D PLA-E through complementary metal oxide semiconductor (CMOS) and micromachining techniques. The 2-D PLA-E was formed with an Au layer sputtered on a SiO2 layer with ellipsoidal holes. The dependence of the responsivity on the polarization indicates that the responsivity is selectively enhanced according to the polarization and the asymmetry of the ellipsoids. The results provide direct evidence that a polarization-selective uncooled IR sensor can be realized simply by the introduction of asymmetry to the surface structure of the 2-D PLA, without the need for a polarizer or optical resonant structures. In addition, a pixel array where each pixel has a different detection polarization could be developed for polarimetric imaging using standard CMOS and micromachining techniques.

Complementary metal-oxide-semiconductor-compatible and self-aligned catalyst formation for carbon nanotube synthesis and interconnect fabrication

We have for the first time developed a self-aligned metal catalyst formation process using fully CMOS (complementary metal-oxide-semiconductor) compatible materials and techniques, for the synthesis of aligned carbon nanotubes (CNTs). By employing an electrically conductive cobalt disilicide (CoSi2) layer as the starting material, a reactive ion etch (RIE) treatment and a hydrogen reduction step are used to transform the CoSi2 surface into cobalt (Co) nanoparticles that are active to catalyze aligned CNT growth. Ohmic contacts between the conductive substrate and the CNTs are obtained. The process developed in this study can be applied to form metal nanoparticles in regions that cannot be patterned using conventional catalyst deposition methods, for example at the bottom of deep holes or on vertical surfaces. This catalyst formation method is crucially important for the fabrication of vertical and horizontal interconnect devices based on CNTs.

Intellectual Property and Patent Abstracts

A collection of 11 patents along with abstracts and diagrams where applicable. Also listed are inventors, assignees, and dated filed. Covers some of the following technologies, theories, and schemes: a composite dipole array; an antenna system using complementary metal oxide semiconductor techniques; an electronically scanned wideband antenna; nanostructured tunable antennas for communication devices; and a beam tilting patch antenna using higher order resonance mode.