Complementary Metal Oxide Semiconductor Process Research Articles

Ultra Low Power Temperature Compensated Complementary Metal Oxide Semiconductor Ring Oscillator in Subthreshold

Low power consumption, low chip area and fabrication in the standard complementary metal oxide semiconductor (CMOS) process are vital requirements for oscillators used in low-cost bio-implantable and wearable devices. Conventional ring oscillators (ROs) are good candidates for using in biomedical applications. However, their oscillation frequency strongly depends on the temperature. In this study, a temperature compensated ring oscillator with low power consumption is proposed. The transistors of the proposed ring oscillator operate in the subthreshold region to achieve a low power and low voltage performance. Since, in the subthreshold region, the oscillation frequency of a conventional ring oscillator increases with increase in the temperature, two current sources are used to power the proposed subthreshold ring oscillator: a temperature independent current source and a complementary to absolute temperature (CTAT) current source. In the proposed circuit, the CTAT current forms a small part of the total supplied current and its duty is to compensate for the oscillation frequency deviation. Two prototypes of the subthreshold ring oscillator were designed and simulated for a target frequency of 1MHz using commercially available 0.18µm RF-CMOS technology. The thermal coefficient (TC) of the uncompensated ring oscillator was 2400 ppm/ºC from -40ºC to 85ºC, though applying the proposed technique reduces the TC of the ring oscillator to 80.4 ppm/ºC with total power consumption as low as 14.5µW.

Design and Implementation of Vertically Integrated Deformable Hermetic Chambers for the Sensitivity Enhancement of CMOS-MEMS Capacitive Pressure Sensor

This study presents the design and implementation of a capacitive type pressure sensor with vertically integrated deformable hermetic chambers based on the standard commercial processes (the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> 1P6M complementary metal-oxide-semiconductor (CMOS) process) and the in-house post CMOS processes. The proposed pressure sensor features the realization of two vertically integrated hermetic chambers consisting of two deformable diaphragms with embedded sensing electrodes and one diaphragm with reference electrodes. Thus, the sensitivity of the pressure sensor can be improved for near twofold within the same footprint. Moreover, the stepped structure is designed to reduce the stiffness of the deformable diaphragms to further enhance the sensitivity of the proposed sensor. The feasibility of the proposed design has been evaluated through both finite element method (FEM) simulations and experiments. Measurement results indicate, as compared with the reference design with only one deformable hermetic chamber, the proposed pressure sensor with vertically integrated deformable hermetic chambers has a near twofold enhancement in sensitivity within the pressure range of 20–120 kPa. Additionally, the proposed design with the deformable stepped-diaphragm can enhance the sensitivity by about 5.1-fold within the same pressure range.

A Dual-Mode Polarization Image Sensor Design Based on In-Pixel Dual-Band Metal Wire Grid for Trustworthy Sensing

In this article, we present the design of an on-chip polarization image sensor with a hardware root of trust (RoT) for trustworthy sensing provided by an interconnection metal-wire-grid (MWG) structure using a standard complementary-metal-oxide-semiconductor (CMOS) process. The proposed MWG structure features dual operation modes, which are polarization image sensing mode at the visible spectrum and physical unclonable function (PUF) mode at the near-infrared spectrum. By integrating the MWG on top of the photo-sensing pixel, the corresponding photocurrent is read out with a mainstream three-transistor-active-pixel-sensor (3T-APS). Moreover, prototype chips are fabricated using a 65-nm 1P8M CMOS process to validate the proposed design. For the polarization mode at 630 nm, the extinction ratio (ER) is measured to be 17 dB. For the PUF mode at 875 nm, the averaged unstable bits and bit error rate (BER) of 15 test chips are reported to be 3.5% and 0.29%, respectively. The responses generated in the PUF mode of the fabricated sensor chips also passed the widely adopted National Institute of Standards and Technology (NIST) and the autocorrelation function (ACF) randomness tests.

Scandium-Doped Aluminum Nitride for Acoustic Wave Resonators, Filters, and Ferroelectric Memory Applications

Scandium-doped aluminum nitride (AlScN) has generated great research interest owing to its unique properties. The wurtzite-structure AlScN is compatible with the complementary metal oxide semiconductor (CMOS) process and has improved piezoelectricity compared with undoped aluminum nitride (AlN), making it a promising candidate to be used for next-generation radio frequency (RF) microelectromechanical system (MEMS) building blocks. Additionally, the ferroelectricity observed in AlScN can be potentially applied to ferroelectric memory devices. In this spotlight article, we provide a brief introduction of AlScN and summarize the recent progress of AlScN-based applications, including RF acoustic wave resonators, filters, and ferroelectric memory devices. Finally, the current challenges as well as the future opportunities of AlScN materials and related applications are discussed.

A High Dynamic Range Dual 8×16 Capacitive Sensor Array for Life Science Applications.

This paper presents a fully integrated complementary metal-oxide-semiconductor (CMOS) capacitive sensor array for life science applications. This sensing device consists of an array of 16 × 16 interdigitated electrodes (IDEs) integrated with a charge-based readout and multiplexing circuitries on the same chip. This chip was implemented in 0.35 µm AMS CMOS process. This sensing device has a wide input capacitance range (ICR) of about 100 fF and a resolution of 150 aF, and the capability of temporal, spatial, and dielectric sensing. It makes it possible to develop a low-cost, multimodal, calibration-free sensing platform for life science applications. Here, we demonstrate and discuss the functionality and applicability of the proposed sensing device by introducing various chemical solvents including ethanol, methanol, and pure water. The simulation and experimental results achieved in this work have taken us one step closer to a fully automated calibration-free multimodal capacitive sensing platform for high-throughput drug development and other purposes.

An maximum power point tracking interface circuit for low-voltage DC-type energy harvesting sources

This paper presents a maximum power point tracking (MPPT) interface circuit for low-voltage DC-type energy harvesting sources such as light and thermal energy. Most energy harvesting systems used in miniature-sized sensor systems require start-up circuits because the output voltages of small-sized energy transducers are very low and not enough to directly power electronic systems. The proposed interface circuit is driven directly by the low output voltages of small size energy transducers, eliminating the need for complex start-up circuitry. A simple MPPT controller with the fractional open-circuit voltage (FOCV) method is designed and fabricated in a 65-nm complementary metal oxide semiconductor (CMOS) process. Measurement results show that the designed circuit can track the MPP voltage even in the presence of the open-circuit voltage fluctuations and can operate properly at operating voltages as low as 0.3 V. The interface circuit achieves a peak power efficiency of 97.1% and an MPPT accuracy of over 98.3%.

Neurostimulators for high-resolution artificial retina: ASIC design challenges and solutions

Objective. Neurostimulator is one of the most important part in artificial retina design. In this paper, we discuss the main challenges in the design of application-specific integrated circuit for high-resolution artificial retina and suggest corresponding solutions. Approach. Problems in the design of the neurostimulator for the existing artificial retina have not been solved yet are analyzed and solutions are presented. For verification of the solutions, mathematical proof, MATLAB and Ansys simulations are used. Main results. The drawbacks of resorting to a high-voltage complementary metal oxide semiconductor (CMOS) process to deal with the large voltage compliance demanded by the stimulator output stage are pointed out, and an alternative approach based on a circuit that switches the voltage of the common reference electrode is proposed to overcome. The necessity of an active discharge circuit to remove the residual charge of electrodes caused by an unbalanced stimulus is investigated. We present a circuit analysis showing that the use of a passive discharge circuit is sufficient to suppress problematic direct current in most situations. Finally, possible restrictions on input and output (I/O) count are investigated by estimating the resistive-capacitive delay caused by the interconnection between the I/O pad and the microelectrode array. Significance. The results of this paper clarified the problems currently faced by neurostimulator design for the artificial retina. Through the solutions presented in this study, circuits with more competitiveness in power and area consumption can be designed.

Multilevel state ferroelectric La:HfO2-based memristors and their implementations in associative learning circuit and face recognition

As Moore’s Law approaches physical limits, traditional von Neumann buildings are facing challenges. The application of memristors in multilayer storage, neuromorphic systems and analog circuits has the potential to overcome the von Neumann architecture bottleneck. Here, we fabricated high-performance memristors based on the Pd/La: HfO2/La2/3Sr1/3MnO3 device on silicon substrate, which facilitate the compatibility with complementary metal oxide semiconductor processes. The memristor devices exhibited good cycling stability and multilevel resistive state storage capabilities. And the synaptic properties of the device, such as long-term potentiation/depression, short-term memory to long-term memory, spike time-dependent plasticity, and double-pulse facilitation, were also shown. Based on the brain-like synaptic behavior of the device, a high recognition rate of 91.11% was achieved in recognizing face images in neural-inspired computing. Through theoretical calculation and hardware associative learning circuit test, the hafnium-based ferroelectric memristor was successfully applied to biological associative learning behavior for the first time.

Foldable-circuit-enabled miniaturized multifunctional sensor for smart digital dust

Smart dust, which refers to miniaturized, multifunctional sensor motes, would open up data acquisition opportunities for Internet of Things (IoT) and Environmental protection applications. However, critical obstacles remain challenging in the integration of high-density sensors, further miniaturization of device platforms, and reduction of cost. Here, we demonstrate the concept of smart digital dust to address these problems, the results of which combine the benefit of (i) maturity of complementary metal-oxide semiconductor (CMOS) processing approaches and (ii) unique form factors of emerging flexible electronics. As a prototype for smart digital dust, we present a millimeter-scale multifunctional optoelectronic sensor platform consisting of high-performance optoelectronic sensor cores and commercially available integrated-circuit components. The smart material-assisted optoelectronic sensing mechanism enables real-time, high-sensitivity hydrogen, temperature, and relative humidity (RH) sensing based on a single chip with ultralow power consumption. Such a microsystem presented here introduces a viable solution to the multifunctional sensing need of IoT and could serve as a building block for the rapidly evolving future framework of smart dust.

High-performance one-dimensional MOSFET array photodetectors in the 0.8-µm standard CMOS process.

This paper reports a series of novel photodetectors based on one-dimensional array of metal-oxide-semiconductor field-effect transistors (MOSFETs), which were fabricated using the standard 0.8-µm complementary metal oxide semiconductor (CMOS) process. Normally, the metal fingers of MOSFET must be manufactured above active region in standard CMOS process, causing MOSFET insensitive to light. The proposed photodetectors use the metal fingers of MOSFETs in a one-dimensional array to form periodical slit structures, which make the transmittance of incident light higher, due to the surface plasmons (SPs) resonance effect. The number of parallel MOSFETs in one-dimensional array is 3, 5, 7, 9 and 11. The experimental results show that all responsivities (Rv) are greater than 103 A/W within visible and near-infrared spectra under room temperature and a maximum value of 1.40 × 105 A/W is achieved, which is at least one order of magnitude larger than those of published photodetectors. Furthermore, a minimum noise equivalent power (NEP) of 5.86 fW/Hz0.5 at 30 Hz and a maximum detectivity (D*) of 2.21 × 1013 Jones are obtained. The photodetectors still have good signal-to-noise ratio when the bandwidth is 1 GHz. At the same time, the optical scanning imaging was completed by utilizing the photodetectors. This combination of high Rv, excellent NEP, high speed and broad spectrum range photodetectors will be widely used in imaging systems.

Device modeling of two-steps oxygen anneal-based submicron InGaZnO back-end-of-line field-effect transistor enabling short-channel effects suppression

Amorphous oxide semiconductor (AOS) field-effect transistors (FETs) have been integrated with complementary metal-oxide-semiconductor (CMOS) circuitry in the back end of line (BEOL) CMOS process; they are promising devices creating new and various functionalities. Therefore, it is urgent to understand the physics determining their scalability and establish a physics-based model for a robust device design of AOS BEOL FETs. However, the advantage emphasized to date has been mainly an ultralow leakage current of these devices. A device modeling that comprehensively optimizes the threshold voltage (VT), the short-channel effect (SCE), the subthreshold swing (SS), and the field-effect mobility (µFE) of short-channel AOS FETs has been rarely reported. In this study, the device modeling of two-steps oxygen anneal-based submicron indium-gallium-zinc-oxide (IGZO) BEOL FET enabling short-channel effects suppression is proposed and experimentally demonstrated. Both the process parameters determining the SCE and the device physics related to the SCE are elucidated through our modeling and a technology computer-aided design (TCAD) simulation. In addition, the procedure of extracting the model parameters is concretely supplied. Noticeably, the proposed device model and simulation framework reproduce all of the measured current–voltage (I–V), VT roll-off, and drain-induced barrier lowering (DIBL) characteristics according to the changes in the oxygen (O) partial pressure during the deposition of IGZO film, device structure, and channel length. Moreover, the results of an analysis based on the proposed model and the extracted parameters indicate that the SCE of submicron AOS FETs is effectively suppressed when the locally high oxygen-concentration region is used. Applying the two-step oxygen annealing to the double-gate (DG) FET can form this region, the beneficial effect of which is also proven through experimental results; the immunity to SCE is improved as the O-content controlled according to the partial O pressure during oxygen annealing increases. Furthermore, it is found that the essential factors in the device optimization are the subgap density of states (DOS), the oxygen content-dependent diffusion length of either the oxygen vacancy (VO) or O, and the separation between the top-gate edge and the source-drain contact hole. Our modeling and simulation results make it feasible to comprehensively optimize the device characteristic parameters, such as VT, SCE, SS, and µFE, of the submicron AOS BEOL FETs by independently controlling the lateral profile of the concentrations of VO and O in two-step oxygen anneal process.

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

Monolithic Integration of Gesn on Si for IR Camera Demonstration

Due to the development of cost-efficient detector technologies in the NIR (Near Infrared), new areas of application are constantly being addressed. This affects autonomous driving, where LiDAR (Light Detection and Ranging) systems with better eye safety are being developed, as well as low-cost night vision cameras. Another area of application is NIR spectroscopy, e.g. in the areas of food monitoring, environmental research or medical technology. The increasing need for portable, low-cost analysis devices, for example for "on-site" measurements or for everyday life, is driving the development of highly miniaturized and low-cost lab-on-a-chip systems. The NIR detectors and NIR cameras available on the market are primarily based on materials from group III/V compound semiconductors, e.g. InGaAs. However, the CMOS (Complementary Metal Oxide Semiconductor) standard process cannot be used for the production of this technology, which significantly increases the cost factor and thus limits its use on the market. A promising alternative is offered by group IV based detectors, in particular Ge and GeSn detectors, which can be monolithically integrated on a Si substrate. As a result, such detector systems can be processed much more cost-efficiently with CMOS compatible standard technology. The NIR absorption properties are also comparable to III/V components.This paper reports on the monolithic integration of Ge and GeSn detector arrays on Si substrates for the realization of a camera system. The entire system consists of a photonic chip, a readout chip and a standard microcontroller, which is connected to a laptop via USB. The SNR (signal-to-noise ratio) is an important parameter for such an integrated system. The quantum efficiency of each individual pixel sensor has to be maximized and a high fill factor per pixel is aimed for. A particularly high fill factor is achieved here with optical light coupling via the substrate back-side, since the front-side metallization does not interfere with the optical coupling area. Furthermore, the metallization acts then as a mirror, the light thus passes through the absorption area twice and leads to a higher quantum efficiency.However, the main obstacle of Ge and GeSn, compared to III/V devices, is the higher intrinsic charge carrier concentration, which leads to a significantly higher dark current. A possible solution is the zero bias operation of the detector at the expected dark current minimum. The dark current is 3 orders of magnitude smaller at 0 V compared to an operating point at -1 V. Another criterion for the circuit is that a signal range or photocurrent supports a wide dynamic range (between nA and µA). For this purpose, the photocurrent is fed into the evaluation electronics via a triple cascaded current mirror. The measured value is output to a 12-bit ADC (Analog Digital Converter) integrated in the microcontroller via a current/voltage converter, two buffers and a sample hold element. With the help of additional multiplexers, the circuit can be used to read out several detectors and thus address a pixel matrix.We report on the fabrication of the photonic chip, which is carried out using CMOS compatible processes and MEMS (Micro-Electro-Mechanical System) processes in combination with an epitaxial growth of the active device structures. The photonic chip is based on 150 mm Si substrates, which were prepared first with multiple ion implantation steps. The active pin detector layers, consisting of Si and Ge or GeSn, were grown by means of molecular beam epitaxy. Afterwards, deep trenches were now etched between the detectors in a MEMS process to minimize crosstalk between neighboring pixels. The detectors were structured then using CMOS processes, and the backside is polished or structured. Finally, a two layer frontside-metallization is applied for the contacts. We demonstrate the functionality of both two-dimensional and linear detector arrays and show possible applications such as NIR cameras or NIR spectrometers.

(Digital Presentation) Electrochemical Metallization Cell Based Memristive Neuron Chip Fabricated with 28nm CMOS Process for Real-Time Unsupervised Learning and Pattern Recognition

Spiking neurons communicate with other neurons using sparse and binary signals in a human brain, so they can achieve real-time processing of the information with ultra-low power consumption[1,2]. Thereby, spiking neurons are essential elements for building an energy-efficient biomimetic spatiotemporal system. Recently, to emulate the behavior of biological neuron, many researches for memristive device-based neurons with peripheral circuits (i.e., sense-amplifier or reset circuit)[3] and complementary metal-oxide-semiconductor (CMOS) neurons with capacitors have been reported[4]. Most of the reported memristive device-based neurons required a high operation voltage (>1.2 V) for emulating integrate function of a biological neuron. In addition, complementary metal-oxide-semiconductor-based neurons could not achieve high neuronal density due to using a capacitor in emulating integrate function.In this study, therefore, we propose an electrochemical metallization cell based memristive neuron chip fabricated with 28-nm CMOS process having a low operation voltage (<0.7 V) for emulating integrate function. In addition, since the proposed electrochemical metallization cell based memristive neuron chip does not require a capacitor for emulating integrate function, it can realize a high neuronal density. The memristive neuron chip exhibited a typical integrate-and-fire function; particularly, the frequency of generating a spiking output signal exponentially increased with the input voltage amplitude. Moreover, a spiking neural network was designed using the memristive neuron chip and the software program consisting of a crossbar synaptic memristor array, simplified spike-timing-dependent-plasticity learning rule, and current-to-voltage converters. Using the co-designed spiking neural network with software and hardware, real-time unsupervised learning was realized. Finally, using the trained spiking neural network, a real-time classification for the MNIST hand-written image taken by a live webcam was successfully performed in an inference process. Acknowledgement This research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT(2021M3F3A2A01037733). Reference Mead, C. Neuromorphic Electronic Systems. Encycl. Comput. Neurosci. 78, 1979–1979 (2015).Douglas, R. Neuromorphic Analogue VLSI. Annu. Rev. Neurosci. 18, 255–281 (1995).Tuma, T., Pantazi, A., Le Gallo, M., Sebastian, A. & Eleftheriou, E. Stochastic phase-change neurons. Nat. Nanotechnol. 11, 693–699 (2016).Aamir, S. A., Müller, P., Hartel, A., Schemmel, J. & Meier, K. A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic system. Eur. Solid-State Circuits Conf. 2016-Octob, 71–74 (2016). Figure 1

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (𝐹𝑜𝑀s) are the highest when compared to other reported FCOTAs in the literature.

Energy-Efficient All-Optical Control of Silicon Microring Resonators via the Optical Gradient Force

All-optical control of silicon photonic devices plays a key role in on-chip all-optical computing, switching and signal processing. However, due to the weak intrinsic nonlinear effects of silicon, current integrated devices are limited by high power consumptions. Here, an all-optical controllable optomechanical microring resonator (OMMR) is proposed and fabricated on the silicon platform. Due to the mechanical Kerr effect induced by the optical gradient force (OGF), we realize seamless wavelength tuning over a range of 2.56 nm which is 61% of the free-spectral range, with a high tuning efficiency of 80 GHz/mW. By controlling the pump power, the OMMR indicates three working regions, which are the cutoff region, amplified region and saturate region. Accordingly, this function is similar to a transistor. Furthermore, the dynamic properties of the OMMR are investigated. By analyzing the dynamic responses, we demonstrate that the OMMR is driven by the OGF, rather than other nonlinear effects. The method simplifies the experimental setup, compared with measuring the intrinsic mechanical frequency of the OMMR. This all-silicon device is energy-efficient and compatible with complementary metal-oxide semiconductor (CMOS) processing. We believe that this work is important for on-chip all-optial signal processing and beneficial to futher studies on integrated optomechanics.

Design, fabrication, characterization and reliability study of CMOS-MEMS Lorentz-force magnetometers

This article presents several design techniques to fabricate micro-electro-mechanical systems (MEMS) using standard complementary metal-oxide semiconductor (CMOS) processes. They were applied to fabricate high yield CMOS-MEMS shielded Lorentz-force magnetometers (LFM). The multilayered metals and oxides of the back-end-of-line (BEOL), normally used for electronic routing, comprise the structural part of the MEMS. The most important fabrication challenges, modeling approaches and design solutions are discussed. Equations that predict the Q factor, sensitivity, Brownian noise and resonant frequency as a function of temperature, gas pressure and design parameters are presented and validated in characterization tests. A number of the fabricated magnetometers were packaged into Quad Flat No-leads (QFN) packages. We show this process can achieve yields above 95 % when the proper design techniques are adopted. Despite CMOS not being a process for MEMS manufacturing, estimated performance (sensitivity and noise level) is similar or superior to current commercial magnetometers and others built with MEMS processes. Additionally, typical offsets present in Lorentz-force magnetometers were prevented with a shielding electrode, whose efficiency is quantified. Finally, several reliability test results are presented, which demonstrate the robustness against high temperatures, magnetic fields and acceleration shocks.

Supply less sensitive ring voltage-controlled oscillator for microwave L-band frequencies

PurposeThe primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.Design/methodology/approachFirst, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.FindingsThis work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.Originality/valueThe proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset

Sense amplifiers (SA) are facing increasing offset problems and amplifying problems due to mismatch of transistors and variations. This paper presents a structure that cancels the offset which is based on the delay and offset relation. The proposed structure can measure the delay of an SA due to its own offset voltage, and convert it into the length of a correction signal. The correction signal discharges the input of the SA, which reduces the voltage of the input to cancel the offset of the SA. The proposed technique can be applied to both the conventional latch-type SA (CLSA) and the current-latched SA with an NMOS footswitch (CSANF). The schematic simulations based on the 28 nm complementary metal-oxide semiconductor process show that the proposed technique can achieve a more centralized offset distribution than the CLSA and the CSANF. Moreover, the offset voltage of the two types SA can be reduced by 71.42% and 65.95%, respectively.

Integrated acoustic resonators in commercial fin field-effect transistor technology

In radio communication, the growth of beamforming and multiple-input–multiple-output technologies, which increase transceiver complexity, have led to a drive to reduce the size, weight and power of radio components by integrating them into a single system on chip. One approach is to integrate the frequency references of acoustic microelectromechanical systems (MEMS) with complementary metal–oxide–semiconductor processes, typically through a MEMS-first or MEMS-last approach that requires process customization. Here we report unreleased acoustic resonators that are fabricated in 14 nm fin field-effect transistor technology and operate in the X-band frequency range (8–12 GHz). The devices use phononic waveguides for acoustic confinement and exploit metal–oxide–semiconductor capacitors and transistors to electromechanically drive and sense acoustic vibrations. Fifteen device variations are analysed across 30 bias points, quantifying the importance of phononic confinement on resonator performance and demonstrating the velocity-saturated piezoresistive effect in active resonant transistors. Our results illustrate the feasibility of integrating acoustic devices directly into standard complementary metal–oxide–semiconductor processes.