Complementary Metal Oxide Semiconductor Process Research Articles

Piezoelectric energy harvesting interface with fast open-circuit voltage sampling

This paper presents a piezoelectric energy harvesting interface with fast open-circuit voltage (VOC) sampling and a wide operating frequency range. The fractional open-circuit voltage (FOCV) method is the primary method for maximum power point tracking (MPPT) in energy harvesting systems, due to its easy implementation and relatively low cost. For this method to be efficient, it is necessary to shorten the time required for VOC sampling. To minimize power loss due to VOC sampling, a novel technique is proposed that is capable of sampling the VOC within a time shorter than half a cycle by using an adaptive tracking pulse instead of conventional fixed ones. We also present a peak detector design technique that can operate across a broad frequency spectrum and adapt to diverse vibration scenarios. The proposed technique reduces the duty cycle of the tracking pulse to 0.42%, which is 3.7 times smaller than the conventional 1.56%. The proposed circuit, designed using a 0.35μm complementary metal oxide semiconductor (CMOS) process, consumes just 94nA at 100Hz, 3V VOC, and a 1kΩ load. In a 2~4V VOC range and a 15~500Hz frequency range, the MPPT efficiency exceeds 95%, peaking at 99.9%, and the power efficiency remains over 93%, reaching a maximum of 97.7%.

A review of silicon carbide CMOS technology for harsh environments

A comprehensive overview of the advancements, challenges, and prospects of silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) technology is presented. As the demand for high-performance and energy-efficient electronic devices continues to grow, SiC has emerged as a promising material due to its unique properties. The paper aims to provide a thorough understanding of the state-of-the-art developments in SiC CMOS technology. The paper delves into the key features of SiC and its compatibility with CMOS processing techniques. It highlights the challenges associated with SiC CMOS technology, such as substrate quality, interface states, and process integration. Examples of CMOS circuitry that have been successfully designed, fabricated, and tested are provided.

Effects of ion implantation with arsenic and boron in germanium-tin layers

Ion implantation is widely used in the complementary metal–oxide–semiconductor process, which stimulates to study its role for doping control in rapidly emerging group IV Ge1−xSnx materials. We tested the impact of As and B implantation and of subsequent rapid thermal annealing (RTA) on the damage formation and healing of the Ge1−xSnx lattice. Ion implantation was done at 30, 40, and 150 keV and with various doses. The implantation profiles were confirmed using secondary ion mass spectrometry. X-ray diffraction in combination with Raman and photoluminescence spectroscopies indicated notable crystal damage with the increase of the implantation dose and energy. Significant damage recovery was confirmed after RTA treatment at 300 °C and to a larger extent at 400 °C for a Ge1−xSnx sample with Sn content less than 11%. A GeSn NP diode was fabricated after ion implantation. The device showed rectifying current-voltage characteristics with maximum responsivity and detectivity of 1.29 × 10−3 A/W and 3.0 × 106 cm (Hz)1/2/W at 77 K, respectively.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Configurable in-memory computing architecture based on dual-port SRAM

In the emerging field of in-memory computing (IMC), this study proposes a dual-port static random access memory (SRAM) IMC architecture with the distinct capability of realizing XOR encryption (XORE), thus serving as a potential solution for the Von Neumann bottleneck. Beyond providing traditional SRAM read and write operations, the proposed architecture carries out additional tasks such as multi-bit multiply and accumulate (MAC) and XOR accumulation (XORA). The architecture was simulated using a 28-nm Complementary Metal Oxide Semiconductor Process, demonstrating a minor standard deviation of 9.41 mV in bit line voltage at the SS process corner, as evidenced by Monte Carlo simulation. Energy expenditure for the MAC, XORA, and XORE, was found to be 1.65, 1.46, and 9.02 fJ/ops respectively at the TT process corner. Furthermore, the presented architecture showed considerable energy efficiency, with MAC, XORA, and XORE operations achieving energy efficiency values of 604.9, 682.7, and 110.8 TOPS/W respectively, at a supply voltage of 0.9 V at the TT process corner.

Manufacturing and characterization of CMOS-MEMS magnetic field microsensors with isolated cavities

The study investigates a magnetic field (MF) microsensor with isolated cavities manufactured utilizing complementary metal oxide semiconductor (CMOS)-microelectromechanical system technology. This microsensor, which is a type of magnetic transistor, comprises four identical magnetic sensing elements, each featuring an emitter, a base, two collectors, and an additional collector. The magnetic transistor operates on the principles of the Lorentz force. This force is employed to modulate the electrical properties of the transistor, responding to changes in the surrounding MF. The MF microsensor chip is fabricated using the commercial CMOS process. Upon completing the CMOS process, post-processing is employed to etch the silicon substrate of the microsensor chip, generating isolated cavities on the silicon substrate. These isolated cavities effectively mitigate substrate leakage current, enhancing the sensitivity of the MF microsensor. The experimental results reveal that the sensitivity of the microsensor without isolated cavities is 60 mV T−1. In contrast, the microsensor with isolated cavities exhibits a sensitivity of 121 mV T−1. A comparison between microsensors with and without isolated cavities depicts that the sensitivity of the MF microsensor with isolated cavities doubled.

Reconfigurable Sensing‐Memory‐Processing and Logical Integration Within 2D Ferroelectric Optoelectronic Transistor for CMOS‐Compatible Bionic Vision

AbstractNeuromorphic ferroelectric transistors integrating sensing and memory capabilities for photoelectric stimuli have provided a remarkable platform for multifunctional bionic vision. However, most hardware demonstrations utilizing ferroelectric transistors cannot implement multiple bio‐visual functions simultaneously under a small operating voltage with scalable material systems, which reduces the compatibility with complementary metal‐oxide‐semiconductor (CMOS) technology and blocks further bio‐visual applications. Herein, an optoelectronic transistor gated is constructed with ferroelectric LiNbO3, which exhibits sensing‐memory‐processing functions and logic integration simultaneously under a low operating voltage (≈1.5 V). Benefiting from the programmable photoinduction and strong ferroelectric polarization, the reliable and highly controllable synaptic characteristics and the bio‐visual selective learning behavior are successfully demonstrated. A high recognition accuracy (≈94.5%) in simulations is also achieved due to the unique linear synaptic plasticity. Furthermore, based on dual‐wavelength modulation, the full‐optical logics “AND” and “OR” are established within the same device. This work provides novel opportunities for the complex multifunctional bionic vision and toward large‐scale integration compatible with silicon‐based CMOS processes.

Organic-Inorganic Hybrid Synaptic Transistors: Methyl-Silsesquioxanes-Based Electric Double Layer for Enhanced Synaptic Functionality and CMOS Compatibility.

Electrical double-layer (EDL) synaptic transistors based on organic materials exhibit low thermal and chemical stability and are thus incompatible with complementary metal oxide semiconductor (CMOS) processes involving high-temperature operations. This paper proposes organic-inorganic hybrid synaptic transistors using methyl silsesquioxane (MSQ) as the electrolyte. MSQ, derived from the combination of inorganic silsesquioxanes and the organic methyl (-CH3) group, exhibits exceptional thermal and chemical stability, thus ensuring compatibility with CMOS processes. We fabricated Al/MSQ electrolyte/Pt capacitors, exhibiting a substantial capacitance of 1.89 µF/cm2 at 10 Hz. MSQ-based EDL synaptic transistors demonstrated various synaptic behaviors, such as excitatory post-synaptic current, paired-pulse facilitation, signal pass filtering, and spike-number-dependent plasticity. Additionally, we validated synaptic functions such as information storage and synapse weight adjustment, simulating brain synaptic operations through potentiation and depression. Notably, these synaptic operations demonstrated stability over five continuous operation cycles. Lastly, we trained a multi-layer artificial deep neural network (DNN) using a handwritten Modified National Institute of Standards and Technology image dataset. The DNN achieved an impressive recognition rate of 92.28%. The prepared MSQ-based EDL synaptic transistors, with excellent thermal/chemical stability, synaptic functionality, and compatibility with CMOS processes, harbor tremendous potential as materials for next-generation artificial synapse components.

A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA.

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter-amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta-sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.

Effect of boron concentration on local structure and spontaneous polarization in AlBN thin films

The discovery of ferroelectricity in polar wurtzite-based ternary materials, such as Al1−xBxN, has attracted attention due to their compatibility with complementary metal–oxide–semiconductor processes and potential use in integrated non-volatile memory devices. However, the origin of ferroelectricity and the fundamental control of the polarization switching in these materials are still under intensive investigation but appear to be related to local disorder induced from the alloying. In this work, we report the effect of boron alloying on the local structure of Al1−xBxN films deposited by magnetron sputtering. Our results reveal a diminished crystalline order as a function of boron concentration, accompanied by a reduction in the spontaneous polarization. The film disorder is primarily associated with the dissimilar bond lengths between Al–N and B–N and the formation of threading dislocations induced by B incorporation in the structure.

Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic Circuits.

Multivalued logic (MVL) technology is a promising solution for improving data density and reducing power consumption in comparison to complementary metal-oxide-semiconductor (CMOS) technology. Currently, heterojunction transistors (TRs) with negative differential transconductance (NDT) characteristics, which play an important role in the function of MVL circuits, adopt organic or 2D semiconductors as active layers, but it is still difficult to apply conventional CMOS processes. Herein, we demonstrate an oxide semiconductor (OS) heterojunction TR with NDT characteristics composed of p-type copper(I) oxide (Cu2O) and n-type indium gallium zinc oxide (IGZO) using the conventional CMOS manufacturing processes. The electrical characteristics of the fabricated device exhibit a high Ion/Ioff ratio (∼3 × 103), wide NDT ranges (∼29 V), and high peak-to-valley current ratios (PVCR ≈ 25). The electrical properties of 15 devices were measured, confirming uniform performance in the PVCR, NDT range, and Ion/Ioff ratio. We analyze the device operation by varying the source/drain (S/D) position and changing the device geometry and the thickness of the Cu2O layer. Additionally, we demonstrate heterojunction ambipolar TR to elucidate the transport mechanism of NDT devices at a high gate voltage (VGS). To confirm the feasibility of the MVL circuit, we present a ternary inverter with three clearly expressed logic states that have a long intermediate state and greater margin of error induced by wide NDT regions and high PVCR.

Recent progress in plasma modification of 2D metal chalcogenides for electronic devices and optoelectronic devices.

Two-dimensional metal chalcogenides (2D MCs) present a great opportunity for overcoming the size limitation of traditional silicon-based complementary metal-oxide-semiconductor (CMOS) devices. Controllable modulation compatible with CMOS processes is essential for the improvement of performance and the large-scale applications of 2D MCs. In this review, we summarize the recent progress in plasma modification of 2D MCs, including substitutional doping, defect engineering, surface charge transfer, interlayer coupling modulation, thickness control, and nano-array pattern etching in the fields of electronic devices and optoelectronic devices. Finally, challenges and outlooks for plasma modulation of 2D MCs are presented to offer valuable references for future studies.

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

K‐band CMOS voltage‐controlled oscillator using switched self‐biasing technique

AbstractA complementary metal oxide semiconductor (CMOS) voltage‐controlled oscillator (VCO) using a tail current source modulated with the output frequency is presented to achieve low phase noise with low power consumption at the K‐band. Differentially modulated current sources, which reduce flicker noise by the feedback of the VCO outputs, contribute to an overall reduction in the phase noise of the VCO using the electromagnetic‐based fully symmetrical design. The proposed LC VCO with a 3‐bit switched capacitor bank for a wide tuning range was fabricated on the size of 0.4 × 0.57 mm2 using a 65‐nm CMOS process. The measurement results of the proposed VCO showed a frequency tuning range from 22.57 to 25.3 GHz, and a phase noise of −108.48 dBc/Hz at a 1‐MHz offset frequency with a power consumption of 8.27 mW at a supply voltage of 1.2 V. The calculated figure of merit (FoM) and FoM with the tuning range were −186.48 and −187.67 dBc/Hz, respectively.

Analog HfxZr1‐xO2 Memristors with Tunable Linearity for Implementation in a Self‐Organizing Map Neural Network

AbstractDoped‐metal oxide‐based memristors, with the potential for improved switching performance and capability for multi‐bit information storage, are attractive candidates in the implementation of artificial neural network (ANN) hardware systems. However, performance and process considerations such as switching behavior and complementary‐metal‐oxide‐semiconductor (CMOS) process compatibility remain a challenge. This study shows that amorphous Zr‐doped HfO2 (HZO) memristors fabricated via a co‐sputtering approach improve the switching performance by providing a controllable knob to modulate defects in the switching layer. At the same time, it satisfies the CMOS process compatibility requirements for industry adoption. HZO memristors with optimized stoichiometry exhibit 30% reduced switching voltages and 50% faster switching as compared to control HfO2 memristors. Concurrently, this study shows that high linearity analog states tuning is achievable via a programming scheme that utilizes voltage pulses with increasing amplitudes. This study further shows via simulation evaluation that HZO memristors implemented in a self‐organizing‐map (SOM) network for Fashion MNIST database classification, achieve an accuracy of 92% with short training cycles. The results thus pave a potential pathway for further development of CMOS process compatible HZO memristors for use in future storage and computing applications.

Impedance-based polymer microneedle patch sensor for continuous interstitial fluid glucose monitoring

Early detection and effective blood glucose control are critical for preventing and managing diabetes-related complications. Conventional glucometers provide point-in-time measurements but are painful and cannot facilitate continuous monitoring. Continuous glucose monitoring systems are comfortable but face challenges in terms of accuracy, cost, and sensor lifespan. This study aimed to develop a microneedle-based sensor patch for minimally invasive, painless, and continuous glucose monitoring in the interstitial fluid to address these limitations. Experimental results confirm painless and minimally invasive penetration of the skin tissue with cylindrical microneedles (3 × 3 array) to a depth of approximately 520 μm with minimal loading. The microneedle sensors fabricated with precision using the complementary metal-oxide semiconductor process were immobilized with glucose oxidase, as confirmed through phase angle analysis. Long-term tests confirmed the effective operation of the sensor for up to seven days. Glucose concentrations determined from the fitted concentration–impedance curves correlated well with those measured using commercial glucometers, indicating the reliability and precision of the microneedle sensor. The flexible and minimally invasive sensor developed in this study facilitates painless and continuous glucose monitoring.

Design and Implementation of Temperature Sensor Based on Dynamic Current Gain Compensation Technology

Complementary metal oxide semiconductor (CMOS) temperature sensors are widely used in on-chip systems for their low cost, high integration and low power consumption. A temperature sensor based on parasitic transistor front-end and dynamic current compensation technology is proposed in this paper, which is used to detect temperature in CMOS bipolar junction transistor. In this paper, the parasitic bipolar junction transistor (BJT) device in CMOS process and its temperature sensing principle are introduced, and a temperature sensor based on BJT temperature sensing front-end and dynamic current compensation technology is proposed. In this scheme, the high-resolution current comparator dynamic current compensation technology is used instead of the large capacitance which is necessary in the traditional current domain temperature sensor, which not only ensures the accuracy of the temperature sensor, but also ensures the accuracy of the temperature sensor, it also saves area and power consumption. The sensor’s control circuit uses a novel bucket search algorithm that allows current measured temperature values to be obtained by comparing as few times as possible. In addition, threshold setting technology is adopted to further improve the temperature sensing accuracy with lower power consumption and area cost. In the end, the test results and analysis are introduced. The CMOS temperature sensor proposed in this paper has been used in the standard 55 nm CMOS process. The test results show that the temperature range from −15 °C to 90 °C, the temperature measurement error is ± 0.5 °C and the area is only 0.021 mm2 after single point calibration.

A High-Precision Voltage-Quantization-Based Current-Mode Computing-in-Memory SRAM.

Non-linear distortion of signals is a serious problem in computing-in-memory SRAM (CIM-SRAM) circuits in current mode. This problem greatly limits the performance of calculations and directly affects the computing power of the CIM-SRAM. In this study, the causes of non-linearity and inconsistency were investigated. Based on detailed analyses, we proposed a high-precision, fully dynamic range IV (HFIV) conversion circuit. The HFIV circuit was added to each bit line (BL) for voltage clamping and proportionally mirroring the read current. We applied the structure to numerous prior studies and evaluated them using the 55 nm complementary metal-oxide semiconductor process. The results showed the proposed HFIV circuit could increase the CIM-SRAM's calculation linearity to 99.92% (8~32 SRAM bit-cells) and 99.8% (32~64 SRAM bit-cells) with a 1.2 V supply.

An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications

This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications. The PS-nGC leverages a two-transistor (2T) gain cell and employs an n-type pseudo-static leakage compensation (n-type PSLC) circuit to significantly extend the eDRAM’s retention time. The implementation of a homogeneous NMOS-based 2T gain cell not only reduces write access times but also benefits from a boosted write wordline technique. In a comparison with the previous pseudo-static gain cell design, the proposed PS-nGC exhibits improvements in write and read access times, achieving 3.27 times and 1.81 times reductions in write access time and read access time, respectively. Furthermore, the PS-nGC demonstrates versatility by accommodating a wide supply voltage range, spanning from 0.7 to 1.2 V, while maintaining an operating frequency of 667 MHz. Fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process, the prototype features an efficient active area, occupying a mere 0.284 µm2 per bitcell for the 4 kb eDRAM macro. Under various operational conditions, including different processes, voltages, and temperatures, the proposed PS-nGC of eDRAM consistently provides speedy and reliable read and write operations.

Mid-wavelength infrared photoconductive film synthesized from PbSe molecular ink

Metal chalcogenide thin films are used in a wide range of modern technological applications. While vacuum deposition methods are commonly utilized to fabricate the film, solution-based approaches have garnered an increasing interest due to their potential for low-cost, high-throughput manufacturing, and compatibility with silicon complementary metal–oxide–semiconductor processing. Here, we report a general strategy for preparing mid-wavelength infrared (MWIR = 3–5 μm) photoconductive film using a PbSe molecular ink. This ethylenediamine-based ink solution is synthesized using a simple diphenyl dichalcogenide route, and the deposited film, after the sensitization annealing, exhibits a specific detectivity of 109 Jones at 3.5 μm at room temperature. This work represents the demonstration of MWIR-photosensitive semiconductor films prepared using an emerging alkahest-based approach, highlighting a significant research avenue in the pursuit toward low SWAP-C (size, weight, power consumption, and cost) infrared imager development.