Complementary Metal Oxide Semiconductor Low Noise Amplifier Research Articles

Multi-objective optimization of CMOS low noise amplifier through nature-inspired swarm intelligence

This paper presents the application of two swarm intelligence techniques, multi-objective artificial bee colony (MOABC) and multi-objective particle swarm optimization (MOPSO), to the optimal design of a complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) cascode with inductive source degeneration. The aim is to achieve a balanced trade-off between voltage gain and noise figure. The optimized LNA circuit operates at 2.4 GHz with a 1.8 V power supply and is implemented in a 180 nm CMOS process. Both optimization algorithms were implemented in MATLAB and evaluated using the ZDT1, ZDT2, and ZDT3 test functions. The optimized designs were then simulated using the advance design system (ADS) simulator. The results showed that the MOABC and MOPSO techniques are practical and effective in optimizing LNA design, resulting in better performance than previously published works, with a gain of 21.2 dB and a noise figure of 0.848 dB.

Ultralow-Noise Figure and High Gain Ku-Band Bulk CMOS Low-Noise Amplifier With Large-Size Transistor

This letter presents a fully integrated Ku-band low-noise amplifier (LNA) with a large-size transistor using 65-nm bulk complementary metal-oxide-semiconductor (CMOS) technology. To achieve an ultralow-noise figure, an optimization methodology balancing the ON-chip gate inductor and the parasitic capacitance of the large-size device is introduced. Using a voltage supply of 1 V, the proposed LNA has a 1.66-dB noise figure and 32.48-dB gain and, thus, outperforms other reported Ku-band bulk CMOS LNAs in these two respects. The LNA achieves the highest figure of merit I among reported Ku-band CMOS, silicon germanium, and gallium arsenide heterojunction bipolar transistor LNAs. The LNA consumes a dc power of 22 mW and occupies a core area of 0.58 × 0.43 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

3‐5 GHz multifinger CMOS LNA using a simultaneous noise and impedance matching technique by a significant reduction of broadband impedance variation of metal–oxide–semiconductor field effect transistor

This work provides a new simultaneous noise and impedance matching (SNIM) methodology for designing a 3–5 GHz ultrawideband low-noise amplifier (LNA) in 0.18 μm complementary metal–oxide–semiconductor (CMOS) process using the advanced design system platform. To justify the proposed method, common gate (CG)- and common source (CS)-input-matched LNAs are designed where the variation of input impedance over the whole operating band is significantly reduced by applying the multifinger layout technique and employing shunt passive elements for the input device without degenerating the structure, respectively. As part of the proposed SNIM method, a two-dimensional contour plot-based process variation tolerant bias voltage set up protocol is developed which can optimise forward gain (S21), noise figure (NF) and stability factor simultaneously. The regulation of amplifier port parameters with bias settling contour plots and finger parameters results in the proposed SNIM technique. For the CG-input-matched LNA, the post-layout electromagnetic simulated NF is between 3.08 and 4.1 dB, the average power gain of 25.52 dB with a power consumption of 20.19 mW and the CS-input-matched LNA achieves an NF in between 2.772 and 3.04 dB, the average power gain of 17.98 dB while the dissipated power is 20.73 mW.

A 180-nm X-Band Cryogenic CMOS LNA

This letter presents the measurement results of a 180-nm complementary metal–oxide–semiconductor (CMOS) $X$ -band low-noise amplifier (LNA) at both 77 and 300 K. The designed LNA provides $S_{11}$ and $S_{22}$ below −10 dB at both temperatures within 6.4–7.4 GHz band. At 300 K, the voltage gain of the designed LNA is higher than 12.5 dB, and it provides an average noise temperature of 275 K, as well as −1 dBm IIP3. At 77 K, the LNA has approximately an 18-dB voltage gain, 78-K noise figure (NF), and −3 dBm IIP3. The presented work is the first implemented $X$ -band cryogenic CMOS LNA in the literature.

Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

SummaryA complementary metal‐oxide‐semiconductor (CMOS) dual‐band low‐noise amplifier (LNA) for 2G/3G/4G mobile communications is presented. It operates at 0.9 and 2.3 GHz of frequencies. The dual‐band operation is achieved by adding a modified notch‐filtering path in the wideband LNA. The modified notch‐filtering path does not require additional power to cancel the signals of the stop band frequency. The impact of the filtering path in the proposed LNA is analyzed. Improved results are observed in dual bands of frequency. Sustainability of the LNA under process corner variation and temperature variation are examined, and it is found to be suitable for the application. The proposed LNA is designed at 90‐nm technology in Cadence Virtuoso with 0.5 and 0.6‐V supply. The post‐layout simulation shows 22 dB of gain (S21), 2 dB of Noise Figure (NF), and −5.5 dBm of IIP3 at the high band. In the low band, 24 dB of S21, 2.7 dB of NF, and −6.65 dBm of IIP3 are reached. The circuit consumes 5.2 mW of power and 0.0918 mm2 of area. The efficiency of the LNA is estimated by the figure of merit, and comparable results are secured in the proposed work.

915-MHz Continuous-Wave Doppler Radar Sensor for Detection of Vital Signs

A miniaturized continuous-wave Doppler radar sensor operating at 915 MHz to remotely detect both respiration and heart rate (beats per minute) is presented. The proposed radar sensor comprises a front-end module including an implemented complementary metal-oxide semiconductor low-noise amplifier (LNA) and fractal-slot patch antennas, whose area was reduced by 15.2%. The two-stage inverter-based LNA was designed with an interstage capacitor and a feedback resistor to acquire ultrawide bandwidth. Two operating frequencies, 915 MHz and 2.45 GHz, were analyzed with regard to path loss for efficient operation because frequency affects detection sensitivity, reflected signal power from the human body, and measurement distance in a far-field condition. Path-loss calculation based on the simplified layer model indicates that the reflected power of the 915 MHz radar could be higher than that of the 2.45 GHz radar. The implemented radar front-end module excluding the LNA occupies 35 × 55 mm2. Vital signs were obtained via a fast Fourier transform and digital filtering using raw signals. In an experiment with six subjects, the respiration and heart rate obtained at 0.8 m using the proposed radar sensor exhibited mean accuracies of 99.4% and 97.6% with respect to commercialized reference sensors, respectively.

Optimal design of a 5.5-GHz low-power high-gain CMOS LNA using the flower pollination algorithm

The design of a low-power, high-gain, highly linear complementary metal–oxide–semiconductor (CMOS) cascode low-noise amplifier (LNA) with an inductive source degeneration circuit for use at 5.5 GHz frequency is optimized using a flower pollination algorithm (FPA) as an evolutionary technique. The FPA is applied to optimize the noise figure (NF) while validating all the design constraints, e.g., on the gain, power dissipation, linearity, stability, and input and output matching. Optimal sizing of the MOS transistors present in the LNA circuit is achieved by using the FPA. Moreover, the FPA helps to estimate the optimal values of the other elements in the LNA circuit. The FPA-based optimal design parameters are used to implement the CMOS LNA circuit in CADENCE IC 6.1.6 software at the UMC 180-nm technology node with a supply voltage of 1.8 V. The designed LNA achieves an input third-order intercept point (IIP3) of 1.77 dBm, power dissipation of 4.29 mW, NF of 0.686 dB, and gain of 24.42 dB at 5.5 GHz. The FPA-based optimal design for the CMOS cascode LNA yields remarkably improved results compared with those in previous literature in terms of the gain, noise figure, power dissipation, and area.

On the Use of 6th-Order Tunable Complementary Metal-Oxide-Semiconductor Varactor based Filter in Ultra-Wideband Low Noise Amplifier

Background:The plethora of the emerged radio frequency applications makes the frequency spectrum crowded by many applications and hence the ability to detect specific application’s frequency without distortion is a difficult task to achieve.Objective:The goal is to achieve a method to mitigate the highest interferer power in the frequency spectrum in order to eliminate the distortion.Method:This paper presents the application of the proposed tunable 6th-order notch filter on Ultra-Wideband (UWB) Complementary Metal-Oxide-Semiconductor (CMOS) Low Noise Amplifier (LNA) utilising self-forward body bias (SFBB).Results:The proposed filter presents 23.5dBm minimum interferer rejection (IR) and attenuates the interferer signal from -43dBm to -67dBm at frequency 5.17GHz. In addition, the maximum IR is 40dBm and attenuates the interferer signal from -41dBm to -81dBm at frequency 5.785GHz. The proposed filter provides coarse tuning with frequency spacing (10MHz) and soft tuning with frequency spacing (1MHz). The UWB CMOS LNA consumes only 5.22mW from a supply voltage of 1.2V and presents a maximum gain of 14dB at frequency 6.25GHz in the -3dB bandwidth from 4.75GHz to 7.5GHz. In addition, the average noise figure is 3.1dB and the input insertion losses (S11) is less than -12dB along the designed bandwidth. The simulation is performed in Advanced Design System (ADS2016.01) software utilising 180nm Taiwan Semiconductor Manufacturing Company (TSMC) Berkeley Short-channel Insulated Gate Field Effect Model (BSIM3v3) model files.Conclusion:The proposed method achieves high interferer power rejection with both soft and coarse tuning.

A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.

A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

21-dB gain ultra-wideband complementary metal–oxide semiconductor low-noise amplifier with current-reuse technique

A high-gain and wideband low-noise amplifier (LNA) employing a current-reuse technique is proposed. The current-reuse technique adopted at the first stage yields an exceptionally high gain due to the summation of n-type metal–oxide semiconductor (MOS) and p-type MOS transconductances, showing wide input matching with the aid of source inductors and load effects. The proposed LNA achieves better than 10 dB input return loss from 3.0 to 9.2 GHz, a minimum noise figure of 2.9 dB, a maximum power gain of 21 dB, a gain-bandwidth product of 554 GHz and a figure of merit of 31.8 GHz/mW while consuming 12.8 mW from 7.1 mA and 1.8 V. The proposed LNA is fabricated using a 0.18-µm complementary MOS process.

Design of a fully differential CMOS LNA for 3.1–10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) for 3.1–10.6 GHz ultra-wideband (UWB) communication systems is presented. The LNA adopts capacitive cross-coupling common-gate (CG) topology to achieve wideband input matching and low noise figure (NF). Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1–10.6 GHz band. Designed in 0.18 μm CMOS technology, the LNA achieves an NF of 3.1–4.7 dB, an S11 of less than −10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point (IIP3) of −5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm, a.

Micromachined CMOS LNA and VCO by CMOS-compatible ICP deep trench technology

Selective removal of the silicon underneath the inductors in RF integrated circuits based on inductively coupled plasma (ICP) deep trench technology is demonstrated by a complementary metal-oxide-semiconductor (CMOS) 5-GHz low-noise amplifier (LNA) and a 4-GHz voltage-controlled oscillator (VCO). Design principles of a multistandard LNA with flat and low noise figures (NFs) within a specific frequency range are also presented. A 2-dB increase in peak gain (from 21 to 23 dB) and a 0.5-dB (from 2.28 to 1.78 dB) decrease in minimum NF are achieved in the LNA while a 3-dB suppression of phase noise is obtained in the VCO after the ICP backside dry etching. These results show that the CMOS-process-compatible backside ICP etching technique is very promising for system-on-a-chip applications.