Abstract

This letter presents a fully integrated Ku-band low-noise amplifier (LNA) with a large-size transistor using 65-nm bulk complementary metal-oxide-semiconductor (CMOS) technology. To achieve an ultralow-noise figure, an optimization methodology balancing the ON-chip gate inductor and the parasitic capacitance of the large-size device is introduced. Using a voltage supply of 1 V, the proposed LNA has a 1.66-dB noise figure and 32.48-dB gain and, thus, outperforms other reported Ku-band bulk CMOS LNAs in these two respects. The LNA achieves the highest figure of merit I among reported Ku-band CMOS, silicon germanium, and gallium arsenide heterojunction bipolar transistor LNAs. The LNA consumes a dc power of 22 mW and occupies a core area of 0.58 × 0.43 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

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