Complementary Metal Oxide Semiconductor Field-Effect Research Articles

Highly Sensitive DNA Detection Beyond the Debye Screening Length Using CMOS Field Effect Transistors

Field effect transistors are considered one of the key technologies to provide real-time and label-free biodetection. Direct detection in physiological solutions is, however, severely limited by the Debye charge-screening effect of the electrical double layer. Most measurements are therefore performed indirectly in diluted ionic-strength solutions. This study proposes a general technique based on modulation of the surface electric field of the CMOS (complementary metal oxide semiconductor) extended-gate field effect transistors (EGFETs) to investigate the screening effect on hybridized DNA (deoxyribonucleic acid) signals from 1 MHz to 15 MHz. The 32 EGFET sensor array exhibited a floating-gate potential change of 17.4 mV/log[DNA] from 1 fM to 100 pM with a near picomolar-level resolution and a response time below 8 minutes.

Design and development of ultrasonic bipolar square-wave pulser for non-destructive testing of concrete structures.

This paper provides design and development details of the generation of bipolar High Voltage (HV) square wave pulses for the excitation of low frequency ultrasonic transducers. Such a circuit is required for the purpose of ultrasonic inspection of components, particularly where high energy is required to insonify the attenuative medium, such as concrete. A HV (±350 V) square wave pulse has been generated by an ultrafast complementary Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) pair, which is driven by high speed MOSFET drivers. The generated bipolar square wave pulse has been utilized to energize a 108 kHz ultrasonic transducer to operate in the pulse-echo mode for the evaluation of a concrete test block. The receiver amplifier filters the received low-amplitude echo signals, which are reflected back from a discontinuity, and amplifies further for signal to noise ratio enhancement. The pulser board designed has been tested and evaluated for its functionality to measure ultrasonic velocity in the highly attenuative concrete medium up to a depth of 1 m. The measured value of acoustic velocity was compared with the value obtained from the commercially available ultrasonic pulse velocity instrument, and the values obtained are within ±5%.

Label free electrical detection of prostate specific antigen with millimeter grade biomolecule-gated AlGaN/GaN high electron mobility transistors

AlGaN/GaN high electron mobility transistor (HEMT) was successfully fabricated by complementary metal-oxide semiconductor field effect transistor-compatible fabrication method, and the label-free, electrical detection of prostate specific antigen in real time using the biomolecule-gate AlGaN/GaN HEMT sensor was presented. It shows a rapid response when target prostate biomarker in buffer solution was added to the antibody-immobilized sensing area. The linear range for target prostate specific antigen detection has been demonstrated from 0.1 pg/ml to 10.269 ng/ml and a low detection below 0.1 pg/ml level is estimated, which is the best result of AlGaN/GaN HEMT biosensor for prostate specific antigen (PSA) detection till now. The sensitivity of 0.027 % is determined for 0.1 pg/ml prostate specific antigen solution. The electrical result of the biomolecule-gated AlGaN/GaN HEMT biosensor suggested that this biosensor might be a useful tool for the prostate cancer screening.

Improvement of metal gate/high-k dielectric CMOSFETs characteristics by neutral beam etching of metal gate

For the metal gate patterning of metal gate/high-k dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for RIE. Improved device characteristics such as the mobility, the transconductance, subthreshold slope, and drain current could be observed. Particularly, the application of the NBE to PMOSFET was more effective than that to NMOSFET. This improvement was related to the decreased interface trap density at the gate dielectric of CMOSFEETs.

Channel Strain Measurement in 32-nm-Node Complementary Metal–Oxide–Semiconductor Field-Effect Transistor by Raman Spectroscopy

Channel Strain Measurement in 32-nm-Node Complementary Metal–Oxide–Semiconductor Field-Effect Transistor by Raman Spectroscopy

Channel Strain Measurement in 32-nm-Node Complementary Metal–Oxide–Semiconductor Field-Effect Transistor by Raman Spectroscopy

We performed a strain analysis of a 32-nm-node microprocessing unit by Raman spectroscopy in conjunction with transmission electron microscopy. The channel surface was exposed by chemical etching and mechanical polishing for Raman spectroscopy. Some defects and Ge concentration variation were observed in embedded SiGe of a p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET). Uniform defects lying at the same angle were observed in the source and drain regions of an n-channel MOSFET (nMOSFET). From the Raman measurement, the Raman peak from strained Si in the pMOSFET shifted toward a higher frequency at approximately 7.5 cm-1, which corresponds to -3.75 GPa (compressive) under the assumption of uniaxial stress along the channel direction. On the other hand, the Raman peak shift from strained Si in the nMOSFET was -1.7 cm-1 corresponding to 0.85 GPa (tensile) under the assumption of uniaxial stress. From the nanobeam diffraction measurements, the compressive strain at the channel edge was larger than that at the channel center in the pMOSFET. On the other hand, the tensile strain in the nMOSFET was induced uniformly in the channel region. We think that understanding and control of channel strain introduction are indispensable in the state-of-the-art complementary MOSFET technology.

Dual Metal/High-kGate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

Dual Metal/High-k Gate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

An Efficient Threshold Voltage Control in Complementary Metal–Oxide–Semiconductor Field Effect Transistor Using Spacer Stress Engineering

In this work, we have demonstrated an efficient method to control threshold voltage in complementary metal–oxide–semiconductor field effect transistor (CMOSFET) using spacer stress technology compatible with a very-large-scale integration (VLSI) process. Consequently, the threshold voltage of the device could be shifted by 180 mV for n-type FETs (n-FETs) with a tensile-stressed SiN spacer and by 20 mV for p-type FETs (p-FETs) with a compressively stressed oxide spacer. From a theoretical thermodynamics model as well as reported experimental data, we demonstrated that spacer stress could play an important role on threshold voltage control due to altering the diffusivities of dopants in silicon.

Sub-30-nm Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with Pt-Incorporated Fully Ni-Silicide/SiON Gate Stack

We demonstrated an ideal scaling of inversion gate dielectric thickness (Tinv) without the decrease in the channel strain of a short-channel planar transistor using a Pt-incorporated fully Ni-silicide (Ni-FUSI)/SiON gate stack. We have achieved drive currents of 1.1/0.65 mA/µm at an off-leakage current of 50 nA/µm for the sub-30-nm n- and p-metal–oxide–semiconductor field effect transistors (MOSFETs). Because the decrease in gate length was larger than the Tinv scaling while maintaining a high drive current, the Ni-FUSI/SiON gate stack improved the intrinsic delay of the scaled inverter.

Atomic Layer Control for Suppressing Extrinsic Defects in Ultrathin SiON Gate Insulator of Advanced Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

By measuring the minimum supply voltage for normal operation of test random access memories, we detected low-density extrinsic defects in silicon-oxynitride (SiON) gate insulators that were formed by state-of-the-art technologies. The density of the detected defects had a strong correlation with optical thickness dopt, which was ellipsometrically measured, regardless of the processing conditions of the SiON films. We propose to maintain the dopt above a threshold value of 1.7 nm to suppress the problems caused by the defects. The optimization of post nitridation annealing (PNA) condition is promising for meeting the criterion without sacrificing device performance. By elaborate investigations based on the Clausius–Mosotti relation, we found that the optical thickness of SiON films is approximately proportional to the atomic area density in the films. On the basis of this finding, we developed a model, which is an extension of the conventional analytical cell-based model, to figure out the physical process of the extrinsic-defect formation. The results analyzed using the model revealed that the extrinsic defects are formed in the SiON films in the case when the number of normal cells in a vertical arrangement becomes equal to or smaller than the threshold value of 3 or 4.

Label-Free Electrical Detection of Cardiac Biomarker with Complementary Metal-Oxide Semiconductor-Compatible Silicon Nanowire Sensor Arrays

Arrays of highly ordered silicon nanowire (SiNW) clusters are fabricated using complementary metal-oxide semiconductor (CMOS) field effect transistor-compatible technology, and the ultrasensitive, label-free, electrical detection of cardiac biomarker in real time using the array sensor is presented. The successful detection of human cardiac troponin-T (cTnT) has been demonstrated in an assay buffer solution of concentration down to 1 fg/mL, as well as in an undiluted human serum environment of concentration as low as 30 fg/mL. The high specificity, selectivity, and swift response time of the SiNWs to the presence of ultralow concentrations of a target protein in a biological analyte solution, even in the presence of a high total protein concentration, paves the way for the development of a medical diagnostic system for point-of-care application that is able to provide an early and accurate indication of cardiac cellular necrosis.

Effects of Strained Silicon Layer on Nickel (Germano)silicide for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transistor Device

The effects of a strained silicon layer on the thermal stability of nickel (germano)silicide for nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET) devices are discussed in this study. Three different thicknesses, 5, 13, and 40 nm, of silicon layers on silicon germanium (SiGe) were prepared for this experiment. The effects of the silicidation rapid thermal annealing (RTA) temperature and postsilicidation annealing temperature for the different silicon layer thicknesses were studied. For comparison, a bulk silicon substrate and a SiGe substrate were also used. Silicides with the thin strained silicon layers (5 and 13 nm) on SiGe showed good thermal stability in this study. However, the other silicides using bulk silicon, 40-nm-thick silicon on SiGe, and the SiGe substrate underwent degradation due to silicide agglomeration during annealing. A SiO2 layer was found on the silicide using the SiGe substrate. In this study, several analysis methods such as four-point probe measurement, field-emission scanning electron microscopy (FE-SEM), atomic force microscopy (AFM), and Auger electron spectroscopy (AES) were used for detailed study.

Channel Strain in Advanced Complementary Metal–Oxide–Semiconductor Field Effect Transistors Measured Using Nano-Beam Electron Diffraction

Using high-precision nano-beam electron diffraction (NBD), we clarified the influences of stress liner and the stress of shallow trench isolation on channel strain in advanced metal–oxide–semiconductor field effect transistors (MOSFETs). For systematic strain measurements, we improved the precision of NBD by observing large reciprocal lattice vectors under appropriate diffraction conditions. The absolute value of the channel strain increases by stress liner as gate length decreases, although the drive current increase due to stress liner saturates at a shorter channel length. The normal strain in the gate length direction is inversely proportional to the distance from the gate electrode to the shallow trench isolation (STI). Furthermore, the relationship between measured channel strain induced by STI and drive current change was shown. The drive current of n- and p-MOSFET changes about 5% with 2×10-3 channel strain variation. This result suggests that reducing the shallow trench isolation stress is effective for controlling the drive current change, depending on the active region layout. We conclude that the experimental measurement of channel strain is necessary for device and circuit design.

Silicon Complementary Metal–Oxide–Semiconductor Field-Effect Transistors with Dual Work Function Gate

This paper discusses silicon complementary metal–oxide–semiconductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (gm) and drain conductance (gds) characteristics. For a n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) device, the polycrystalline silicon (poly-Si) gate on the source and drain side are doped p+ and n+, respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-Si gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved gm and gds over conventional single work function gate devices.

Characterizing the Channel Backscattering Behavior in Nanoscale Strained Complementary Metal Oxide Semiconductor Field-Effect Transistors

This work investigates the impact of different uniaxial strain polarities on channel backscattering in nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET). Two carrier statistics, nondegenerate and degenerate-limited, are employed to extract the channel backscattering ratio, ballistic efficiency, and related backscattering factors. While the channel length scales down and the channel stress level increases further, the modulation of channel backscattering ratio, i.e., improved (degraded) by uniaxial tensile (compressive) strain, becomes more prominent. This observation holds true under both carrier statistics, which implies that the nondegenerate case with simple mathematics can be fairly used for evaluation. In addition, the correlation between strain-enhanced mobility gain and drain current improvement is found to be predicted well by the ballistic efficiency deduced with the nondegenerate carrier statistics.

Design of high speed Si/SiGe heterojunction complementary metal–oxide–semiconductor field effect transistors with reduced short-channel effects

By taking advantages of higher carrier mobility and bandgap engineering in the Si/SiGe system, we explore the channel and source/drain (S/D) designs for Si/SiGe heterojunction complementary metal–oxide–semiconductor field effect transistors (CMOSFETs). A planar CMOS structure is proposed in which a strained SiGe layer (the hole channel) and a strained Si layer (the electron channel) grown on relaxed SiGe wells are designed for p- and n-MOSFETs, respectively, to provide better current drive capability. On the other hand, a strained-SiGe S/D heterojunction is also included in the CMOSFET device structure in that the band offset between S/D and the channel is found to be very effective in suppressing short-channel effects such as drain-induced barrier lowering/bulk punchthrough and drain leakage. With proper structure design, the near symmetrical n-MOS/p-MOS VT, enhanced current-drive capability and reduced short channel effects are achievable within the proposed planar structure.