Complementary Metal Oxide Semiconductor Applications Research Articles

Investigation on Germanium Transistors with HfOx-Based Gate Stacks for CMOS Operations

Germanium (Ge) FinFETs with HfOx-based gate stacks are fabricated to study the CMOS applications. To evaluate the logic circuit operation, the associated CMOS inverters are characterized. Compared to the HfO2, the Hf0.5Zr0.5Ox (HZO) gate stack provides higher drive currents and more symmetric Vth behaviors, which should be associated with the polarization effect. Through cyclic voltage transfer characteristic (VTC) operation and systematical analysis, it is found that both polarization and charge trapping in the gate stack impact the device characteristics. The HZO devices show a negative VTC shift with cycling, while the HfO2 devices reveal a positive shift. This opposite VTC behavior for both gate stack schemes indicates that the interaction of interface states and dipoles significantly influences the device operation. The results revealed in this work present a comprehensive understanding of HfOx-based device optimization.

Solution-Processed 2D Transition Metal Dichalcogenides: Materials to CMOS Electronics

ConspectusTwo-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) have demonstrated exceptional potential as materials for future complementary metal-oxide-semiconductor (CMOS) technology. This is primarily because of their atomic thickness and excellent electrical and mechanical properties. With advancements in fabrication technology, electronic devices based on 2D TMD materials have rapidly progressed from isolated units for scientific experimentation to integrated circuits with practical applications. Among the different production methods, the solution-processing of 2D TMD nanomaterial dispersions offers the distinct advantages of low-temperature processing and cost-effective manufacturing for large-scale flexible and wearable electronics. A wide range of 2D nanoflake inks with versatile electronic properties can be assembled into atomic-thick thin films with dangling-bond-free van der Waals interfaces between adjacent nanoflakes. Furthermore, direct printing techniques can easily integrate multifunctional devices, such as n-type and p-type transistors, into CMOS devices and more complex integrated circuits. Despite these benefits and previous accomplishments, the field of solution-processed CMOS electronics using 2D TMD semiconducting materials is in its early stages of development and requires further research. One of the current challenges is the production of scalable and high-purity 2D semiconductor mono- and few layers with large lateral sizes and narrow thickness distribution. The field-effect mobility of solution-processed 2D TMD transistors remains lower than that of the transistors manufactured using mechanical exfoliation and chemical vapor deposition methods. In particular, limited research has been conducted on solution-processed p-type 2D TMD transistors. As a result, solution-processed CMOS devices using n-type and p-type 2D TMD transistors are scarce. In this Account, we provide an overview of the recent progress in the field of solution-processed CMOS electronics employing 2D TMD materials. First, we introduce the basic liquid exfoliation methods, such as sonication-assisted exfoliation and molecular intercalation methods, that are commonly utilized to prepare 2D TMD dispersions. In addition, we discuss the production of monolayer 2D materials, which serve as the building blocks for fabricating atomic-thick thin films. Subsequently, we review the typical techniques for depositing 2D inks, including spin coating, drop casting, and inkjet printing. Furthermore, we outline the thin-film patterning process for each technique, which is crucial for integrating multifunctional materials in CMOS devices. Subsequently, we focus on the recent advancements in solution-processed 2D TMD transistors. Furthermore, we explore the various factors that can improve the performance of the devices with regard to charge transport and charge traps. Afterward, we highlight notable applications of solution-processed CMOS technology, such as logic circuits and ring oscillators. Finally, we provide an overview of the challenges and opportunities in the development of solution-processed 2D materials and the integration of multifunctional devices for the advancement of CMOS electronics. This Account aims to provide a comprehensive guide for readers, offering both a broad overview and an in-depth insight into solution-processed 2D material-based electronics, covering a wide range of topics from the preparation of 2D TMD ink to device fabrication and CMOS applications. Therefore, this Account is expected to drive further progress and advancements in this field and promote the realization of practical applications.

Rhombohedral-stacked bilayer transition metal dichalcogenides for high-performance atomically thin CMOS devices.

Van der Waals coupling with different stacking configurations is emerging as a powerful method to tune the optical and electronic properties of atomically thin two-dimensional materials. Here, we investigate 3R-stacked transition-metal dichalcogenides as a possible option for high-performance atomically thin field-effect transistors (FETs). We report that the effective mobility of 3R bilayer WS2 (WSe2) is 65% (50%) higher than that of 2H WS2 (WSe2). The 3R bilayer WS2 n-type FET exhibits a high on-state current of 480 μA/μm at Vds=1 V and an ultralow on-state resistance of 1 kilohm·μm. Our observations, together with multiscale simulations, reveal that these improvements originate from the strong interlayer coupling in the 3R stacking, which is reflected in a higher conductance compared to the 2H stacking. Our method provides a general and scalable route toward advanced channel materials in future electronic devices for ultimate scaling, especially for complementary metal oxide semiconductor applications.

Dual-Channel WS2/WSe2 Heterostructure with Tunable Graphene Electrodes

Two-dimensional semiconductor heterostructures provide significant research potential for electronic and optoelectronic applications because of their scaled thickness, pristine heterostructure interface, and ultrafast carrier transport. Herein, we report a dual-channel field-effect transistor based on n-type WS2 and p-type WSe2 layered heterostructure using multilayered graphene as electrodes to enable electron-dominated ambipolar electrical transport. WS2 exhibits mobility of 20 cm2 V–1 s–1 and an on/off ratio of 105, whereas WSe2 exhibits mobility of 5 cm2 V–1 s–1 and an on/off ratio of 104. Furthermore, our results show negative Schottky barrier heights between dual-channel heterostructure and multilayered graphene. The proposed design reduces complications in the fabrication of devices with integrated heterostructures, particularly for complementary metal-oxide semiconductor inverter applications.

Investigation of radiation response for III-V binary compound semiconductors due to protons using Geant4

The III-V binary compound semiconductor is considered to be an appealing candidate for future complementary metal oxide semiconductor applications and the most promising silicon substitute in terms of high electron mobility. In this study, the authors used the Monte Carlo simulation software Geant4 and the data analysis tool Python to comprehensively examine the interaction between protons with a wide range of energy and III-V binary compound semiconductors. This work focus on the radiation responses of 11 kinds of III-V materials—AlAs, AlP, AlSb, GaAs, GaN, GaP, GaSb, InAs, InN, InP, and InSb—with silicon as a reference. Energy straggling, secondary ion generation, and energy distribution in the sensitive layer were represented in each simulation of the incident protons. Information about the distributions of the linear energy transfer of the secondary ions and energy deposition was acquired through data analysis. Finally, the impact of the material species on the single-event upset responses triggered by the direct ionization and the nuclear reaction mechanisms at different critical charges were investigated.

Enhanced performance of p-type SnO x thin film transistors through defect compensation

Due to the unique outermost orbitals of Sn, hole carriers in tin monoxide (SnO) possess small effective mass and high mobility among oxide semiconductors, making it a promising p-channel material for thin film field-effect transistors (TFTs). However, the Sn vacancy induced field-effect mobility deterioration and threshold voltage (V th) shift in experiments greatly limit its application in complementary metal-oxide-semiconductor (CMOS) transistors. In this study, the internal mechanism of vacancy defect compensation by aluminum (Al) doping in SnO x film is studied combining experiments with the density functional theory (DFT). The doping is achieved by an argon (Ar) plasma treatment of Al2O3 deposited onto the SnO x film, in which the Al2O3 provides both the surface passivation and Al doping source. Experimental results show a wide V th modulation range (6.08 to −19.77 V) and notable mobility enhancement (11.56 cm2V−1s−1) in the SnO x TFTs after the Al doping by Ar plasma. DFT results reveal that the most possible positions of Al in SnO and SnO2 segments are the compensation to Sn vacancy and interstitial. The compensation will create an n-type doping effect and improve the hole carrier transport by reducing the hole effective mass (m h*), which is responsible for the device performance variation, while the interstitial in the SnO2 segment can hardly affect the valence transport of the film. The defect compensation is suitable for the electronic property modulation of SnO towards the high-performance CMOS application.

A high speed processor for elliptic curve cryptography over NIST prime field

Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three-clock cycle, divide-and-conquer multiplication algorithm which greatly reduces the number of execution cycles of multiplication. We then propose a dedicated multiplication hardware structure which reuses the multiplier and optimizes data path delay. To keep multiplication running in non-idle status and executing in parallel with other modular operations, the operation scheduling of point addition and point doubling has been re-designed and optimized based on an effective segmentation and pipeline strategy. Finally, under the premise of similar computing and hardware overhead, we propose an improved high-security SM algorithm which involves random points to resist side-channel attacks. On a 55 nm complementary metal oxide semiconductor application specific integrated circuit platform, the processor costs 463k gates and requires 0.028 ms for one SM. Our results indicate that the ECC processor is superior to other state-of-the-art designs reported in the literature in terms of speed and area-time product metrics.

Molecular Approach to Engineer Two-Dimensional Devices for CMOS and beyond-CMOS Applications.

Two-dimensional materials (2DMs) have attracted tremendous research interest over the last two decades. Their unique optical, electronic, thermal, and mechanical properties make 2DMs key building blocks for the fabrication of novel complementary metal-oxide-semiconductor (CMOS) and beyond-CMOS devices. Major advances in device functionality and performance have been made by the covalent or noncovalent functionalization of 2DMs with molecules: while the molecular coating of metal electrodes and dielectrics allows for more efficient charge injection and transport through the 2DMs, the combination of dynamic molecular systems, capable to respond to external stimuli, with 2DMs makes it possible to generate hybrid systems possessing new properties by realizing stimuli-responsive functional devices and thereby enabling functional diversification in More-than-Moore technologies. In this review, we first introduce emerging 2DMs, various classes of (macro)molecules, and molecular switches and discuss their relevant properties. We then turn to 2DM/molecule hybrid systems and the various physical and chemical strategies used to synthesize them. Next, we discuss the use of molecules and assemblies thereof to boost the performance of 2D transistors for CMOS applications and to impart diverse functionalities in beyond-CMOS devices. Finally, we present the challenges, opportunities, and long-term perspectives in this technologically promising field.

Epitaxial Ge-Gd[formula omitted]O[formula omitted] on Si(111) substrate by sputtering for germanium-on-insulator applications

Germanium-on-insulator (GeOI) technology is a potential-alternative to the bulk-silicon based devices for radio-frequency (RF), and complementary metal oxide semiconductor applications at advanced technology nodes. A thin germanium channel is the key enabler of high mobility transistors and group-IV photonic devices. A prohibitive cost of GeOI wafers may discourage high volume manufacturing (HVM) despite promising performance. Here, we demonstrate epitaxial Gd2O3-Ge-Gd2O3 thin film growth on Si(111) substrate in an HVM platform - RF magnetron sputter system, where, the first Gd2O3 layer acts as buried-oxide (BOX) in the GeOI wafer. The second Gd2O3 layer is used as a cap-layer to be removed later using wet etching. Both the Gd2O3 layer is grown epitaxially at 750∘C, while the germanium layer is grown at room temperature and crystallised later by solid phase epitaxy (SPE) technique. The entire growth is performed without vacuum-break, to enable high throughput and excellent interface control. To compare the quality of the heterostructure, this sputter based SPE is performed on: (1) in-situ sputter grown, versus (2) ex-situ molecular-beam-epitaxy (MBE) grown epitaxial Gd2O3 BOX layer. The x-ray diffraction analysis confirms the formation of twin-free epitaxial Ge layer in the case of in-situ sputtered Gd2O3 while twinned Ge layer is observed in the case of ex-situ MBE grown Gd2O3. The twinning of the Ge layer in the ex-situ process is further supported by transmission electron microscopy analysis. Finally, we have performed an experiment to study the impact of Gd2O3 BOX layer thickness on the crystal quality of Ge layer and show that the Ge layer crystal quality remains intact irrespective of BOX layer thickness. Therefore, we have achieved twin free Ge epitaxy in RF magnetron sputter system, equivalent to in-situ All-MBE SPE process. Such a process enables low-cost GeOI wafer manufacturing for cost-effective RF transistors.

Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Study of selective graphene growth on non-catalytic hetero-substrates

To incorporate graphene layers into a complementary metal oxide semiconductor (CMOS), various growth techniques are needed, such as direct and selective growth at a low temperature. The selective growth on a heterogeneous substrate is the key technology for the realistic synthesis of various structures, including graphene. In this study, we addressed the origin of selective growth of graphene on a semiconductor over the dielectric materials. Based on ab initio simulations, we found that the adsorption energy of CH4 on SiO2 is much higher than that on Si and Ge. The growth differences of graphene on Ge and SiO2 were also experimentally confirmed. While a continuous graphene layer was formed on the Ge surface at the initial growth stage that became thicker at increasing growth times, an incubation time was required for the nucleation of graphene on SiO2. The analysis of the interface between graphene and SiO2 indicated that the initially incorporated carbons could not contribute to the graphene growth because they reduced SiO2 by forming CO as a by-product. Finally, 3.0 nm-thick graphene layers were selectively grown on a SiO2-patterned Ge/Si(0 0 1) substrate. The selective growth of graphene on patterned semiconductor substrates will help broaden CMOS applications.

First principles investigation of Y2O3-doped HfO2

First-principles calculations based on a truncated Coulomb hybrid functional were used to elucidate Y2O3 doping of HfO2. We calculated the formation enthalpies as well as density of states of nearly 1200 defective structures of two phases of HfO2: room-temperature monoclinic and high-temperature cubic structures. For dilute doping, the monoclinic phase is retained and electron trapping states are introduced near the conduction band minimum. For doping concentrations near to 12.5 at. %, the cubic phase is stabilized and the gap is free from charge trapping defect states, making it a suitable high-dielectric constant material for complementary metal-oxide semiconductor applications.

Direct Growth of Graphene on a SiGe Alloy Surface by Chemical Vapor Deposition

Integration of graphene with Si-based semiconductor materials, which are core-materials in complementary metal oxide semiconductor (CMOS) technology, is desirable. To date, the synergistic effects of various graphene-semiconductor hybrid systems have been shown to overcome various physical limitations of graphene and semiconductors. However, the graphene utilized in most previous studies was synthesized over a metal catalyst and required additional transfer processes that could generate irreversible physical defects and chemical contamination. Although direct synthesis of graphene on Si or Ge has been developed, research into graphene growth using silicon-germanium (SiGe) as a catalyst remains in its infancy. This is despite expectations that this method would be highly applicable to next-generation CMOS applications. Herein, we demonstrate the direct growth of graphene on a SiGe surface using a conventional chemical vapor deposition method. Optical microscopy, electron microscopy, and Raman spectroscopy were used to confirmed that the graphene was uniformly synthesized over the entire substrate. The advantages of CMOS-compatible graphene growth and high crystallinity of the synthesized graphene will provide opportunities for novel graphene-SiGe hybrid system development and next-generation CMOS technology.

Entirely relaxed lattice-mismatched GaSb/GaAs/Si(001) heterostructure grown via metalorganic chemical vapor deposition

A GaSb epilayer is grown on a GaAs/Si(001) epitaxial substrate via metalorganic chemical vapor deposition. High-resolution transmission electron microscopy micrographs and high-resolution X-ray reciprocal space mapping indicate an entirely relaxed interfacial misfit (IMF) array GaSb epilayer. The valence-band offset and conduction-band offset of the Al2O3/GaSb/GaAs/Si structure are estimated to be 2.39 and 3.65 eV, respectively. The fabricated Al2O3/p-GaSb/GaAs/Si MOS capacitors exhibited good capacitance–voltage characteristics with a small accumulation frequency dispersion of approximately 1.05% per decade. These results imply that the GaSb epilayer grown on the GaAs/Si platform in the IMF mode can be used for future complementary metal–oxide semiconductor applications.

Growth of high-quality In0.28Ga0.72Sb/AlSb/GaSb/GaAs heterostructure by metalorganic chemical vapor deposition for single-channel Sb-based complementary metal–oxide–semiconductor applications

The growth of high-quality In0.28Ga0.72Sb epilayer on an AlSb/GaSb/GaAs heterostructure by metalorganic chemical vapor deposition is demonstrated. The In0.28Ga0.72Sb epilayer has a fully relaxed surface roughness of ∼1.0 nm and a low threading dislocation density of ∼6.2 × 106 cm−2. The valence band offset (VBO) of 3.11 eV and conduction band offset (CBO) of 3.21 eV for an Al2O3/In0.28Ga0.72Sb interface extracted from X-ray photoemission spectroscopy data highlight its suitability for use in single-channel InGaSb-based complementary metal–oxide–semiconductor (CMOS) applications. The type-I straddling gap of an In0.28Ga0.72Sb/AlSb heterojunction with a VBO of 0.47 eV and CBO of 0.65 eV is also sufficient to prevent both electron and hole leakage currents in CMOS devices.

MBE growth and digital etch of GaSb/InAs nanowires on Si for logic applications

The 6.1 Å III–V “high-mobility” semiconductor family includes materials with beneficial transport properties of both electrons and holes (InAs, GaSb), which are appealing for fast and low-power complementary metal–oxide–semiconductor applications. Yet their large lattice mismatch with Si (∼12%) results in three dimensional island nucleation and therefore growth defects. The solution for deposition of this high mismatch material is the growth of the entire device from a single nucleus, such as in vertical nanowires. Two types of GaSb nanowires (NWs) are demonstrated on a Si(111) substrate: vertically stacked InAs/GaSb NWs and coaxial core/shell NWs. This paper summarizes surface preparation, growth conditions, and postprocessing steps which can be used to create nanowires with small enough diameters for use as logic devices.

(Invited) Fabrication of High-Quality Ge-on-Insulator Structures by Lateral Liquid Phase Epitaxy

Germanium (Ge) has been considered as a key material for next-generation electronic–photonic integration in large-scale integrated circuits on Si substrates. Ge-based electronic device is beneficial for high-performance complementary metal-oxide semiconductor application compatible with Si technology because Ge is a Group IV element and the electron and hole mobilities are 2.5-4 times higher than those of Si. Ge metal-oxide-semiconductor field-effect transistors (MOSFETs) might suffer from the large off-leakage current caused by the small bandgap, however Ge-on-insulator (GOI) structure has a great potential to overcome this obstacle. Ge is also expected as light emission and absorption material in the photonic devices. Although Ge has the electronic band structure of indirect band gap, the direct bandgap at Γ valley is 0.8 eV, corresponding to 1550-nm wavelength, same as used in optical communication, and the energy difference between Γ and L valley is only 136 meV. Furthermore, inducing lattice strain and Tin (Sn) incorporation into Ge enhance the carrier mobility and modulate the band structure from the indirect to the direct band structure, resulting in the enhancement of electronic device performance and the increase of light emission and absorption efficiency in photonic devices, respectively. Therefore, a lot of studies have been extensively carried out in order to realize Ge-based electronic–photonic integration. One of the critical challenges for the realization is to fabricate GOI structures with high-crystalline-quality Ge layers. Among various methods of GOI fabrication, layer transfer and Ge condensation are the ones most widely used. However, the former requires complex processing and the latter has difficulties in achieving high-quality GOI layers. Recently, rapid melt growth, in other words, the lateral liquid-phase epitaxy (LLPE) method, was developed for producing local GOI structures on Si substrates [1,2]. In this method amorphous Ge wires connected to the Si substrate at seed area are annealed above the melting point of Ge and lateral epitaxial growth from the seed area along the Ge wires occurs during cooling. This method has the remarkable advantage for heteroepitaxial growth containing large lattice mismatch, where misfit dislocations frequently generate at the interface between the epitaxial layer and the substrate. In the fabrication of GOI structures by this method crystallographic defects generate at the Si seed region because the lattice mismatch between Ge and Si is 4.2%. However, they quickly move out of the thin wires, similar to necking in the Czochralski crystal-growth process, resulting in single-crystalline Ge wires containing no dislocations or stacking faults. This method has another advantage to induce tensile strain in GOI layers. The lattice spacing of Ge is larger than that of Si, so that compressive strain is typically induced in the Ge layer epitaxially grown on the Si substrate. Insertion of low-temperature-grown buffer layer and following high temperature growth allow 0.2% tensile strain in the Ge layer originating from the difference in the thermal-expansion coefficients of the Ge layer with respect to the Si substrate [3]. In the case of the LLPE method, tensile strain of 0.35% is expected because Ge wires are stress free at the melting point (938°C) and cooled down to room temperature, where the difference in the thermal-expansion coefficients is most effectively utilized to induce tensile strain. In this paper, we report the electrical and photonic properties of the LLPE-grown Ge wires. We have investigated the electrical properties of the Ge wires by the back-gate GOI MOSFETs [4,5]. We confirmed a high on/off source-drain current ratio of 106 and high hole mobility of 480 cm2/Vs, which is 2.8 times higher than that of the reference SOI device. We have also examined direct band gap shrinkage in the LLPE-grown Ge wires by means of micro (μ)-photoluminescence (PL) and μ-Raman spectroscopy [6]. Strain analysis and temperature dependent PL spectra indicated that a direct band gap shrinkage amounting to 45 meV was mainly due to a tensile strain of about 0.4% induced by rapid crystallization from the Ge melting point during the LLPE process. [1] Y. Liu et al., Appl. Phys. Lett. 84, 2563 (2004). [2] T. Hashimoto et al., Appl. Phys. Express 2, 066502 (2009). [3] Y. Ishikawa et al., Appl. Phys. Lett. 82, 2044 (2003). [4] Y. Suzuki et al., Appl. Phys. Lett. 101, 202105 (2012). [5] T. Hosoi et al., Appl. Phys. Lett. 105, 173502 (2014). [6] M. Matsue et al., Appl. Phys. Lett. 104, 031106 (2014).

Heteroepitaxial Ge MOS Devices on Si Using Composite AlAs/GaAs Buffer

Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, $V_{FB}$ , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density $(D_{it} )$ from $8.55 \times 10^{11} $ to $1.09 \times 10^{12}~ {\rm cm}^{-2} ~{\rm eV}^{-1} $ is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.

Structural, optical and microwave dielectric studies of Co doped MgTiO3 thin films fabricated by RF magnetron sputtering

We report the structural, optical, and microwave dielectric characteristics of (Mg0.95Co0.05)TiO3 (MCT) thin films deposited onto amorphous SiO2 (a-SiO2) substrates by RF magnetron sputtering for the first time. The role of the oxygen mixing percentage (OMP) on the growth, morphology, optical, and microwave dielectric properties of MCT thin films has been investigated. The as-deposited MCT films were x-ray amorphous and crystallined after annealing at 700 °C for 1 h in air. A preferred orientation of grains along the (110) direction has been observed with increasing OMP. Such a textured growth is explained by calculating the orientation factors from the Lotgering model. The dispersion in a refractive index with wavelength has been explained using a single oscillator dispersion model. Both the refractive index and bandgap of the films increases on annealing. The annealed films exhibit refractive indices in the range of 1.88–2.08 at 600 nm with an optical bandgap value between 3.95–4.16 eV. The increase in the refractive index is attributed to the improvement in packing density and crystallinity, and decrease in the porosity ratio, whereas the increase in bandgap is due to the decrease in intermediary energy levels within the optical bandgap. (Mg0.95Co0.05)TiO3 thin films exhibited a progressive increase in the dielectric properties with OMP and a maximum dielectric constant of ϵr = 17.3 and low loss (tanδ ∼ 1.1 × 10−3) at a spot frequency of 10 GHz for the films deposited at 75% OMP, beyond which they decreased. The improvement in dielectric properties with an increase in OMP has been correlated to the preferred orientation growth, reduction in oxygen vacancies, and strain. The prepared MCT thin films are suitable candidates for anti-reflection coatings and complementary metal-oxide semiconductor (CMOS) applications.

III–V compound semiconductor transistors—from planar to nanowire structures

Abstract