Complementary Junction Field-effect Transistors Research Articles

SiC Complementary Junction Field-Effect Transistor Logic Gate Operation at 623 K

Here, we show that silicon carbide (SiC) complementary logic gates composed of p- and n-channel junction field-effect transistors (JFETs) fabricated by ion implantation operate at 623 K with a supply voltage as low as 1.4 V. The logic threshold voltage shift of the complementary JFET (CJFET) inverter is only 0.2 V from 300 to 623 K. Furthermore, temperature dependencies of the static and dynamic characteristics of the CJFET inverter are well explained by a simple analytical model of SiC JFETs.

Technological and devices modeling of complementary JFETs over a wide temperature range

The article presents the results of process and device modeling results of complementary junction field-effect transistors (JFET). The models necessary for calculating the JFET in the temperature range down to cryogenic were described: the Klaassen model of the carriers mobility (Phillips company model) and Shockley-Read-Hall recombination model, taking into account the doping dependence, Lackner's model of avalanche multiplication, Fermi-Dirac statistics, Slotboom model, designed to describe the dependence of the band gap on the doping concentration. These models take into account the effect of temperature. We have described in detail the model of incomplete ionization of an impurity, which determines the concentration of charge carriers at cryogenic temperatures. The TCAD-based JFET self-heating effect is simulated using a simplified model that significantly reduces the calculation time compared to the thermodynamic model. Studies on the selection of an algorithm for calculating a system of differential equations in the temperature region are carried out. It is shown that the SLIP90 algorithm provides calculations in the entire temperature range down to T = 25 K. The article shows that modification of the design can significantly affect the choice of calculation algorithm. The dependences of the main JFET parameters are analyzed taking into account the selected models on temperature and constructive and technological solutions are proposed to reduce the influence of ultra-low temperatures on the parameters of complementary JFETs.The research results showed that reducing the cut-off voltage reduces the influence of temperature on the shorted-gate drain current JFET in the temperature range. At the same time, n-channel transistors have advantages in terms of a smaller change in parameters over the temperature range down to the temperatures at which the “freezing out” of the impurity charge carriers begins. Several types of transistor topologies were simulated in the temperature range, which showed that the value of the shorted-gate drain current increases linearly with the number of gates. However, there are differences in the dependence of the main parameters in the temperature range depending on the design of the layers of complementary JFETs. Using the emitter region as the top gate weakly affects the parameters of the n-channel JFET in the case of the formation of complementary JFETs in the microwave complementary bipolar technological process, and for the p-channel JFET the temperature stability of the parameters deteriorates. For the p-channel transistor with a gate based on the base region, the temperature stability over the range ΔT = 150–330 K of the shorted-gate drain current is higher than for the transistor with a gate based on the emitter. For the n-channel transistor, the dependence is inverse. Over the range ΔT = 150–77 K, the dependence of the parameters of the transistors for two structures does not differ. In principle, the results show that the change in the ambient temperature has a greater effect on the p-channel transistor than on the n-channel.

Исследования высоковольтных комплементарных полевых транзисторов с управляющим p-n переходом в диапазоне температур с помощью методов приборно-технологического моделирования

Исследования высоковольтных комплементарных полевых транзисторов с управляющим p-n переходом в диапазоне температур с помощью методов приборно-технологического моделирования

SiC Vertical-Channel n- and p-JFETs Fully Fabricated by Ion Implantation

Silicon carbide (SiC) n-and p-channel junction field effect transistors (JFETs) with vertical channels were fabricated by direct ion implantation into a high-purity semi-insulating 4H-SiC substrate in order to further develop the path towards complementary JFET integrated circuits for applications in harsh environments. Compared with the conventional structure (lateral channel), the proposed structure is suitable for integration and inherently has a high transconductance owing to the double-gate configuration. The threshold voltage (Vth) can be controlled by mask design, while Vth in the conventional structure is solely determined by the ion implantation conditions. We demonstrate the transistor operation of the vertical-channel n-and p-channel JFETs fully fabricated by ion implantation.

Complementary logic with 60 nm poly gate JFET for 0.5 V operation

Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n- and p-channel JFET transistors built on bulk silicon and SOI with 60 nm gate length operating at 0.5 V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16 nm.

Radiation-hardened silicon-on-insulator complementary junction field-effect transistors

The effects of total-dose radiation have been investigated for complementary junction field-effect transistors fabricated in zone-melting recrystallized Si films on SiO 2 -coated Si substrates. With a - 5-V bias applied to the Si substrate during irradiation and device operation, both n- and p-channel devices show low threshold-voltage shift (<-0.09 and <-0.12 V, respectively), low leakage currents (<- 1- and <3-pA/µm channel width, respectively) and small transconductance degradation (<15 percent) for total doses up to 108rad (Si).

Double-implanted GaAs complementary JFET's

The fabrication and performance characteristics of double-implanted GaAs complementary junction field-effect transistors (JFET's) suitable for low-power digital integrated circuit applications are described. Effective mobilities for the n-channel enhancement-mode JFET are 3500 cm2/V.s and for the p-channel 300 cm2/V.s. Experimental results of an ultra-low-power static RAM are presented.