Germanium (Ge) has been considered as a key material for next-generation electronic–photonic integration in large-scale integrated circuits on Si substrates. Ge-based electronic device is beneficial for high-performance complementary metal-oxide semiconductor application compatible with Si technology because Ge is a Group IV element and the electron and hole mobilities are 2.5-4 times higher than those of Si. Ge metal-oxide-semiconductor field-effect transistors (MOSFETs) might suffer from the large off-leakage current caused by the small bandgap, however Ge-on-insulator (GOI) structure has a great potential to overcome this obstacle. Ge is also expected as light emission and absorption material in the photonic devices. Although Ge has the electronic band structure of indirect band gap, the direct bandgap at Γ valley is 0.8 eV, corresponding to 1550-nm wavelength, same as used in optical communication, and the energy difference between Γ and L valley is only 136 meV. Furthermore, inducing lattice strain and Tin (Sn) incorporation into Ge enhance the carrier mobility and modulate the band structure from the indirect to the direct band structure, resulting in the enhancement of electronic device performance and the increase of light emission and absorption efficiency in photonic devices, respectively. Therefore, a lot of studies have been extensively carried out in order to realize Ge-based electronic–photonic integration. One of the critical challenges for the realization is to fabricate GOI structures with high-crystalline-quality Ge layers. Among various methods of GOI fabrication, layer transfer and Ge condensation are the ones most widely used. However, the former requires complex processing and the latter has difficulties in achieving high-quality GOI layers. Recently, rapid melt growth, in other words, the lateral liquid-phase epitaxy (LLPE) method, was developed for producing local GOI structures on Si substrates [1,2]. In this method amorphous Ge wires connected to the Si substrate at seed area are annealed above the melting point of Ge and lateral epitaxial growth from the seed area along the Ge wires occurs during cooling. This method has the remarkable advantage for heteroepitaxial growth containing large lattice mismatch, where misfit dislocations frequently generate at the interface between the epitaxial layer and the substrate. In the fabrication of GOI structures by this method crystallographic defects generate at the Si seed region because the lattice mismatch between Ge and Si is 4.2%. However, they quickly move out of the thin wires, similar to necking in the Czochralski crystal-growth process, resulting in single-crystalline Ge wires containing no dislocations or stacking faults. This method has another advantage to induce tensile strain in GOI layers. The lattice spacing of Ge is larger than that of Si, so that compressive strain is typically induced in the Ge layer epitaxially grown on the Si substrate. Insertion of low-temperature-grown buffer layer and following high temperature growth allow 0.2% tensile strain in the Ge layer originating from the difference in the thermal-expansion coefficients of the Ge layer with respect to the Si substrate [3]. In the case of the LLPE method, tensile strain of 0.35% is expected because Ge wires are stress free at the melting point (938°C) and cooled down to room temperature, where the difference in the thermal-expansion coefficients is most effectively utilized to induce tensile strain. In this paper, we report the electrical and photonic properties of the LLPE-grown Ge wires. We have investigated the electrical properties of the Ge wires by the back-gate GOI MOSFETs [4,5]. We confirmed a high on/off source-drain current ratio of 106 and high hole mobility of 480 cm2/Vs, which is 2.8 times higher than that of the reference SOI device. We have also examined direct band gap shrinkage in the LLPE-grown Ge wires by means of micro (μ)-photoluminescence (PL) and μ-Raman spectroscopy [6]. Strain analysis and temperature dependent PL spectra indicated that a direct band gap shrinkage amounting to 45 meV was mainly due to a tensile strain of about 0.4% induced by rapid crystallization from the Ge melting point during the LLPE process. [1] Y. Liu et al., Appl. Phys. Lett. 84, 2563 (2004). [2] T. Hashimoto et al., Appl. Phys. Express 2, 066502 (2009). [3] Y. Ishikawa et al., Appl. Phys. Lett. 82, 2044 (2003). [4] Y. Suzuki et al., Appl. Phys. Lett. 101, 202105 (2012). [5] T. Hosoi et al., Appl. Phys. Lett. 105, 173502 (2014). [6] M. Matsue et al., Appl. Phys. Lett. 104, 031106 (2014).
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May 9, 2016
Y Katagiri + 11
Open Access
