High-level Language Compilers Research Articles

Copy-and-patch compilation: a fast compilation algorithm for high-level languages and bytecode

Fast compilation is important when compilation occurs at runtime, such as query compilers in modern database systems and WebAssembly virtual machines in modern browsers. We present copy-and-patch, an extremely fast compilation technique that also produces good quality code. It is capable of lowering both high-level languages and low-level bytecode programs to binary code, by stitching together code from a large library of binary implementation variants. We call these binary implementations stencils because they have holes where missing values must be inserted during code generation. We show how to construct a stencil library and describe the copy-and-patch algorithm that generates optimized binary code. We demonstrate two use cases of copy-and-patch: a compiler for a high-level C-like language intended for metaprogramming and a compiler for WebAssembly. Our high-level language compiler has negligible compilation cost: it produces code from an AST in less time than it takes to construct the AST. We have implemented an SQL database query compiler on top of this metaprogramming system and show that on TPC-H database benchmarks, copy-and-patch generates code two orders of magnitude faster than LLVM -O0 and three orders of magnitude faster than higher optimization levels. The generated code runs an order of magnitude faster than interpretation and 14% faster than LLVM -O0. Our WebAssembly compiler generates code 4.9X-6.5X faster than Liftoff, the WebAssembly baseline compiler in Google Chrome. The generated code also outperforms Liftoff's by 39%-63% on the Coremark and PolyBenchC WebAssembly benchmarks.

An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms

We propose PROMISE, the first end-to-end design of a PROgrammable MIxed-Signal accElerator from Instruction Set Architecture to high-level language compiler for acceleration of diverse machine learning algorithms by exploiting the advantage of the superior energy efficiency from analog/mixed-signal processing.

Compiling with Continuations and LLVM

LLVM is an infrastructure for code generation and low-level optimizations, which has been gaining popularity as a backend for both research and industrial compilers, including many compilers for functional languages. While LLVM provides a relatively easy path to high-quality native code, its design is based on a traditional runtime model which is not well suited to alternative compilation strategies used in high-level language compilers, such as the use of heap-allocated continuation closures. This paper describes a new LLVM-based backend that supports heap-allocated continuation closures, which enables constant-time callcc and very-lightweight multithreading. The backend has been implemented in the Parallel ML compiler, which is part of the Manticore system, but the results should be useful for other compilers, such as Standard ML of New Jersey, that use heap-allocated continuation closures.

Semantic languages for developing correct language translations

The development and validation of language translators (e.g. port programs, language preprocessors, high-level software language compilers, etc.) are time-consuming and error-prone: language engineers need to master both the source and target languages’ syntactic constructs; and most importantly their semantics. In this paper, we present an innovative approach for developing and validating such language translators based on two languages: With the first, we specify a language translation using a syntax-to-syntax mapping; and with the second, we define the semantics of both of the source and target languages. After showing how such specifications can be combined to validate and generate language translators automatically, we demonstrate the feasibility of the approach on a particular modelling language translation.

Accelerated Thomas Solver for (Quasi-)Block-Tridiagonal Linear Algebraic Equation Systems, Using SSE/AVX Instruction Sets for Vectorizing Dense Block Operations

Streaming SIMD Extensions (SSE) and Advanced Vector Extensions (AVX) are additional processor instruction sets available in contemporary personal computers, designed for vectorized floating point calculations. Unfortunately, in order to utilize the advantages of these instructions, one cannot rely on automatic options of high level language compilers. Instead, handwritten assembly language or intrinsic function call insertions are necessary. By using this idea an accelerated C[Formula: see text] code is devised, for solving (quasi-) block-tridiagonal linear algebraic equation systems by means of an extended Thomas algorithm. Speedups reaching 3.5 and 3 (relative to C[Formula: see text] without using SSE/AVX) are demonstrated for single and double precision calculations, respectively.

A Linda-based platform for the parallel execution of out-place model transformations

ContextThe performance and scalability of model transformations is gaining interest as industry is progressively adopting model-driven techniques and multicore computers are becoming commonplace. However, existing model transformation engines are mostly based on sequential and in-memory execution strategies, and thus their capabilities to transform large models in parallel and distributed environments are limited. ObjectiveThis paper presents a solution that provides concurrency and distribution to model transformations. MethodInspired by the concepts and principles of the Linda coordination language, and the use of data parallelism to achieve parallelization, a novel Java-based execution platform is introduced. It offers a set of core features for the parallel execution of out-place transformations that can be used as a target for high-level transformation language compilers. ResultsSignificant gains in performance and scalability of this platform are reported with regard to existing model transformation solutions. These results are demonstrated by running a model transformation test suite, and by its comparison against several state-of-the-art model transformation engines. ConclusionOur Linda-based approach to the concurrent execution of model transformations can serve as a platform for their scalable and efficient implementation in parallel and distributed environments.

Fast enumeration of words generated by Dyck grammars

The problem of enumerating and denumerating words generated by Dyck grammars arises in the work of compilers for high-level programming languages and a number of other applications. The present paper proposes an algorithm for the fast enumeration and denumeration of words of Dyck languages; the complexity of this algorithm per one symbol of enumerated words is O(log3n log log n) bit operations, provided that the Schonhage-Strassen multiplication and division algorithmis used. The well-knownmethods applied earlier possess complexityO(n) per one symbol of enumerated words. The construction of the proposed algorithm is based on the Ryabko method.

Compiler design: analysis and transformation

While compilers for high-level programming languages are large complex software systems, they have particular characteristics that differentiate them from other software systems. Their functionality is almost completely well-defined - ideally there exist complete precise descriptions of the source and target languages. Additional descriptions of the interfaces to the operating system, programming system and programming environment, and to other compilers and libraries are often available. The book deals with the optimization phase of compilers. In this phase, programs are transformed in order to increase their efficiency. To preserve the semantics of the programs in these transformations, the compiler has to meet the associated applicability conditions. These are checked using static analysis of the programs. In this book the authors systematically describe the analysis and transformation of imperative and functional programs. In addition to a detailed description of important efficiency-improving transformations, the book offers a concise introduction to the necessary concepts and methods, namely to operational semantics, lattices, and fixed-point algorithms. This book is intended for students of computer science. The book is supported throughout with examples, exercises and program fragments.

Software-programmable continuous-flow multi-purpose lab-on-a-chip

Current lab-on-a-chip (LoC) devices are assay-specific and are custom-built for each single experiment. Performing an experiment requires scientists or engineers to go through the time-consuming process of designing, fabricating, and testing a chip before conducting the actual experiment. This prolonged cycle can take months to complete, increasing effort and cost and reducing productivity. Similarly, minor modifications to an assay protocol re-incur the overheads of the design cycle. In this paper, we develop a multi-purpose, software-programmableLab-on-a-Chip (SPLoC), where the user simply writes or downloads a program for each experiment. We describe the components necessary to realize the SPLoC, which include a high-level programming language, an abstract instruction set, a runtime and control system, and a microfluidic device. We describe two key features of our high-level language compiler, and describe a novel variable-volume variable-ratio mixer. Finally, we demonstrate our SPLoC on four diverse, real-world assays.

Compiler design: virtual machines

While compilers for high-level programming languages are large complex software systems, they have particular characteristics that differentiate them from other software systems. Their functionality is almost completely well-defined ideally there exist complete precise descriptions of the source and target languages, while additional descriptions of the interfaces to the operating system, programming system and programming environment, and to other compilers and libraries are often available. The implementation of application systems directly in machine language is both difficult and error-prone, leading to programs that become obsolete as quickly as the computers for which they were developed. With the development of higher-level machine-independent programming languages came the need to offer compilers that were able to translate programs into machine language. Given this basic challenge, the different subtasks of compilation have been the subject of intensive research since the 1950s. This book is not intended to be a cookbook for compilers, instead the authors' presentation reflects the special characteristics of compiler design, especially the existence of precise specifications of the subtasks. They invest effort to understand these precisely and to provide adequate concepts for their systematic treatment. This is the first book in a multivolume set, and here the authors describe what a compiler does, i.e., what correspondence it establishes between a source and a target program. To achieve this the authors specify a suitable virtual machine (abstract machine) and exactly describe the compilation of programs of each source language into the language of the associated virtual machine for an imperative, functional, logic and object-oriented programming language. This book is intended for students of computer science. Knowledge of at least one imperative programming language is assumed, while for the chapters on the translation of functional and logic programming languages it would be helpful to know a modern functional language and Prolog. The book is supported throughout with examples, exercises and program fragments.

Transactional memories for multi-processor FPGA platforms

Programming efficiency of heterogeneous concurrent systems is limited by the use of lock-based synchronization mechanisms. Transactional memories can greatly improve the programming efficiency of such systems. In field-programmable computing machines, a conventional fixed transactional memory becomes inefficient use of the silicon. We propose configurable transactional memory (CTM) as a mechanism to implement application specific synchronization that utilizes the field-programmability of such devices to match with the requirements of an application. The proposed configurable transactional memory is targeted at embedded applications and is area efficient compared to conventional schemes that are implemented with cache-coherent protocols. In particular, the CTM is designed to be incorporated in to compilation and synthesis paths of either high-level languages or during system creation process using tools such as Xilinx EDK. The proposed system supports an OpenMP-based programming paradigm for the efficient use of transactional memories. In addition, the conflict detection scheme can be configured to work either in lazy or in eager mode, depending on the application requirements. We study the impact of deploying a CTM using both micro-benchmarks and real applications as compared to a lock-based synchronization scheme. We have implemented the proposed scheme in a Xilinx Virtex4 device and found that the CTM can provide both higher programming efficiency, lower energy consumption and higher speedup than a fine-grained lock-based scheme.

The semantics of power and ARM multiprocessor machine code (abstract only)

We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets. The semantics is mechanised in the HOL proof assistant. This should provide a good basis for informal reasoning and formal verification of low-level code for these weakly consistent architectures, and, together with our x86 semantics, for the design and compilation of high-level concurrent languages.

An embedded implementation of the Common Language Infrastructure

The Common Language Infrastructure provides a unified instruction set which may be targeted by a variety of high level language compilers. This unified instruction set simplifies the construction of compilers and gives application designers the ability to choose the high level programming language that best suits the problem being solved. While the Common Language Infrastructure solves many problems related to design of applications and compilers, it is not without its own problems. The Common Language Infrastructure is based upon a virtual machine, much like the Java Virtual Machine. This requires that all instructions being executed on the Common Language Infrastructure be translated to native machine instructions before they can be executed on the host processor. This leads to degradation in performance. In order to overcome this problem it is proposed that an embedded processor capable of natively executing the CLI instruction set be developed. The objective of this work is the design and implementation, using VHDL and simulation, of an embedded processor capable of natively executing the CLI instruction set. This processor provides a platform easily targeted by software developers.

Trading up [electronics 32bit

It's a tight project. You need to keep costs down and the timescale is demanding. So, do you reach for the familiar development tools and the 8bit processor? Or go instead for a 32bit processor, with powerful software and development tools? Until now, hardware cost in might have put a 32bit device out of reach, but with the launch of products based on the ARM Cortex-M3 family. 32bit processing has become more accessible, with sufficient memory to use with an operating system and a high-level language compiler.

OpenFPGA CoreLib core library interoperability effort

This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. This effort is contrasted with other IP reuse efforts. The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool. The CoreLib approach for standardizing this IP integration is proposed followed by an example that demonstrates its utility. Finally, the current state of the effort and future plans are presented.

Developing device models

Describes rapid implementation of semiconductor device models in SPICE using an MCAST compact model compiler. Device-model development is a vital component of circuit design and is traditionally a very challenging task. To overcome this challenge, it would be beneficial for model developers to use high-level behavioral language and model compilers. Implementations of MOS level-3 models and BSIMSOI models have demonstrated that this behavioral modeling approach is more efficient and practical than traditional C/FORTRAN methodologies and could save future model developers a significant amount of time and cost in implementation and maintenance. With the further enhancement and wider acceptance of this new approach, it is expected to promote more and better device models in the near future.

Customisable Hardware Compilation

Hardware compilers for high-level languages are increasingly recognised to be the key to reducing the productivity gap for advanced circuit development in general, and for reconfigurable designs in particular. This paper explains how customisable frameworks for hardware compilation can enable rapid design exploration, and reusable and extensible hardware optimisation. It describes such a framework, based on a parallel imperative language, which supports multiple levels of design abstraction, transformational development, optimisation by compiler passes, and metalanguage facilities. Our approach has been used in producing designs for applications such as signal and image processing, with different trade-offs in performance and resource usage.

An innovative low-power high-performance programmable signal processor for digital communications

We describe an innovative, low-power, high-performance, programmable signal processor (DSP) for digital communications. The architecture of this processor is characterized by its explicit design for low-power implementations, its innovative ability to jointly exploit instruction-level parallelism and data-level parallelism to achieve high performance, its suitability as a target for an optimizing high-level language compiler, and its explicit replacement of hardware resources by compile-time practices. We describe the methodology used in the development of the processor, highlighting the techniques deployed to enable application/architecture/compiler/implementation co-development, and the optimization approach and metric used for power-performance evaluation and tradeoff analysis. We summarize the salient features of the architecture, provide a brief description of the hardware organization, and discuss the compiler techniques used to exercise these features. We also summarize the simulation environment and associated software development tools. Coding examples from two representative kernels in the digital communications domain are also provided. The resulting methodology, architecture, and compiler represent an advance of the state of the art in the area of low-power, domain-specific microprocessors.

Reducibility between Classes of Port Graph Grammar

This paper introduces a general notion of static-port graph grammar (PGG) that encompasses existing formalisms that have been independently proposed, such as linear graph grammars, interaction nets and partial sharing graphs. These formalisms provide a computational framework for asynchronous computation that respects a very rigorous notion of local interaction, and have proven a suitable basis for the internal representation of program and data in the compilation of high-level programming languages for distributed execution. The general class of PGGs introduced in this paper provides a more expressive computational framework, still possessing asynchronous concurrency but which has a reduction mechanism that is complex and non-local. The increased expressiveness of this calculus is shown by means of a motivating example of concurrent pattern matching. However, the non-locality of the calculus renders it unsuitable for direct implementation. The paper introduces a class of simple PGGs, a local rewriting calculus suitable for distributed implementation. The central result of the paper is to show how the general class of PGGs may be reduced to the simple PGGs, in a manner that fully preserves all the potential for concurrent rewriting present in the original.

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.