OpenFPGA CoreLib core library interoperability effort

M Wirthlin,D Poznanovic,P Sundararajan,A Coppola,D Pellerin,W Najjar,R Bruce,M Babst,O Pritchard,P Palazzari,G Kuzmanov

doi:10.1016/j.parco.2008.03.004

OpenFPGA CoreLib core library interoperability effort

M Wirthlin, D Poznanovic + Show 9 more

https://doi.org/10.1016/j.parco.2008.03.004

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Journal: Parallel computing	Publication Date: Mar 29, 2008
Citations: 22

Affiliation: Brigham Young University, Xilinx (United States), Impulse Dynamics (United States), University of California, Riverside, Education Scotland, DSPlogic (United States), Altera (United States), National Agency for New Technologies, Energy and Sustainable Economic Development, Delft University of Technology

#Future Plans #High-level Programming Tools + Show 8 more

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Abstract

This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. This effort is contrasted with other IP reuse efforts. The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool. The CoreLib approach for standardizing this IP integration is proposed followed by an example that demonstrates its utility. Finally, the current state of the effort and future plans are presented.

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