High-level languages

Abstract

There are several interesting compilation tools on the market for synthesizing FPGA circuits from high level languages. These tools advertise the ability to generate high-quality FPGA circuits from a variety of specification formats such procedural languages (C, Fortran, etc.), modeling languages (SystemC), or from signal flow graphs. These tools claim significant improvements in design productivity by allowing the designer to operate at higher levels of abstraction than available with traditional RTL-level synthesis.Some claim that these high-level tools will completely change the way we design FPGAs. Those with this view believe that these tools will replace today's design approaches and VHDL/Verilog design will wither away like assembly language programming. They believe that the FPGA designer of the future will only need basic programming skills to create a high-quality FPGA designs. The arcane RTL design methodology used today will be a thing of the past. Others believe that these tools are just another fad in the long line of failed high-level design tools. They suggest that procedural languages like C are ill-suited to express the fine-grain parallelism available in hardware. Further, the synchronization/timing semantics needed to implement parallel hardware are not available. Perhaps of most concern to those in this camp is the lower quality circuits synthesized by these tools. What good is a high-level tool if it can't meet your timing or performance constraint? If high-level tools are successful, those with this view believe they will be limited to small niche markets with limited appeal to the average designer.What is the future of FPGA design? Will higher-level design tools finally provide the productivity and quality that has been promised? Or, are these tools just another passing fad? This panel will address these questions and discuss the future FPGA design. The panel will include experts from a variety of perspectives including representatives from high-level tool vendors, FPGA manufacturers, and experienced designers. Each panelist will give a brief summary of their views on this topic, followed by questions and lively debate. Audience participation is actively encouraged and audience members will have the opportunity for asking questions and making statements.