Compiler Support Research Articles

Compiler Support for the Fortran 2003, 2008, TS29113, and 2018 Standards Revision 24

This is a repeating article in Fortran Forum. The first version appeared in Fortran Forum in April 2007. The basis for the entries in the original list of features was a report by John Reid. An electronic version can be found at: ftp://ftp.nag.co.uk/sc22wg5/N1601-N1650/N1648.pdf If you are a compiler vendor and would like to be included in future versions of this table please email one of us with details and they will be added to the table and published in Fortran Forum.

Compiler Support for the Fortran 2003 and 2008 Standards Revision 22

column Share on Compiler Support for the Fortran 2003 and 2008 Standards Revision 22 Authors: Ian D. Chivers Rhymney Consulting, London Rhymney Consulting, LondonView Profile , Jane Sleightholme FortranPlus, London FortranPlus, LondonView Profile Authors Info & Claims ACM SIGPLAN Fortran ForumVolume 37Issue 1April 2018 pp 44–67https://doi.org/10.1145/3206214.3206216Published:09 April 2018Publication History 0citation62DownloadsMetricsTotal Citations0Total Downloads62Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Liquid Silicon-Monona

With the recent trend of promoting Field-Programmable Gate Arrays (FPGAs) to first-class citizens in accelerating compute-intensive applications in networking, cloud services and artificial intelligence, FPGAs face two major challenges in sustaining competitive advantages in performance and energy efficiency for diverse cloud workloads: 1) limited configuration capability for supporting light-weight computations/on-chip data storage to accelerate emerging search-/data-intensive applications. 2) lack of architectural support to hide reconfiguration overhead for assisting virtualization in a cloud computing environment. In this paper, we propose a reconfigurable memory-oriented computing fabric, namely Liquid Silicon-Monona (L-Si), enabled by emerging nonvolatile memory technology i.e. RRAM, to address these two challenges. Specifically, L-Si addresses the first challenge by virtue of a new architecture comprising a 2D array of physically identical but functionally-configurable building blocks. It, for the first time, extends the configuration capabilities of existing FPGAs from computation to the whole spectrum ranging from computation to data storage. It allows users to better customize hardware by flexibly partitioning hardware resources between computation and memory, greatly benefiting emerging search- and data-intensive applications. To address the second challenge, L-Si provides scalable multi-context architectural support to minimize reconfiguration overhead for assisting virtualization. In addition, we provide compiler support to facilitate the programming of applications written in high-level programming languages (e.g. OpenCL) and frameworks (e.g. TensorFlow, MapReduce) while fully exploiting the unique architectural capability of L-Si. Our evaluation results show L-Si achieves 99.6% area reduction, 1.43× throughput improvement and 94.0% power reduction on search-intensive benchmarks, as compared with the FPGA baseline. For neural network benchmarks, on average, L-Si achieves 52.3× speedup, 113.9× energy reduction and 81% area reduction over the FPGA baseline. In addition, the multi-context architecture of L-Si reduces the context switching time to - 10ns, compared with an off-the-shelf FPGA (∼100ms), greatly facilitating virtualization.

Contention free delayed keeper for high density large signal sensing memory compiler

Compiler based embedded memory is essential for SoC design. A new Contention Free Delayed Keeper (CFDK) topology has been developed in a leading edge 14 nm System-on-Chip (SoC) technology to improve the read performance of register file (RF) memories which can be easily used for both high density (HD) and high performance (HP) RF memory compiler design. This technique never allows contention and this helps to improve Vmin (minimum operating voltage at which design is functional) significantly compared to a conventional keeper with low area overhead. It does not require fine tuning the keeper delay across the range of the local bit line (LBL) lengths that the compiler supports. It is shown that the proposed technique enhances the circuit evaluation speed by at least 68% while reducing power dissipation by 2.75% as compared to conventional domino logic. It also shows minimum 10% improvement in area with at par or better Vmin and performance over other delayed keeper techniques. The same technique can be broadly applied to any domino path design including ROM design.

CAIRO

Three-dimensional (3D)-stacking technology and the memory-wall problem have popularized processing-in-memory (PIM) concepts again, which offers the benefits of bandwidth and energy savings by offloading computations to functional units inside the memory. Several memory vendors have also started to integrate computation logics into the memory, such as Hybrid Memory Cube (HMC), the latest version of which supports up to 18 in-memory atomic instructions. Although industry prototypes have motivated studies for investigating efficient methods and architectures for PIM, researchers have not proposed a systematic way for identifying the benefits of instruction-level PIM offloading . As a result, compiler support for recognizing offloading candidates and utilizing instruction-level PIM offloading is unavailable. In this article, we analyze the advantages of instruction-level PIM offloading in the context of HMC-atomic instructions for graph-computing applications and propose CAIRO , a compiler-assisted technique and decision model for enabling instruction-level offloading of PIM without any burden on programmers. To develop CAIRO, we analyzed how instruction offloading enables performance gain in both CPU and GPU workloads. Our studies show that performance gain from bandwidth savings, the ratio of number of cache misses to total cache accesses, and the overhead of host atomic instructions are the key factors in selecting an offloading candidate. Based on our analytical models, we characterize the properties of beneficial and nonbeneficial candidates for offloading. We evaluate CAIRO with 27 multithreaded CPU and 36 GPU benchmarks. In our evaluation, CAIRO not only doubles the speedup for a set of PIM-beneficial workloads by exploiting HMC-atomic instructions but also prevents slowdown caused by incorrect offloading decisions for other workloads.

Compiler Support for the Fortran 2003 and 2008 Standards Revision 22

column Share on Compiler Support for the Fortran 2003 and 2008 Standards Revision 22 Authors: Ian D. Chivers Rhymney Consulting, London Rhymney Consulting, LondonView Profile , Jane Sleightholme FortranPlus, London FortranPlus, LondonView Profile Authors Info & Claims ACM SIGPLAN Fortran ForumVolume 36Issue 3December 2017 pp 12–33https://doi.org/10.1145/3171572.3171574Published:05 December 2017Publication History 0citation50DownloadsMetricsTotal Citations0Total Downloads50Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Optimization of Low-Density Parity Check decoder performance for OpenCL designs synthesized to FPGAs

Open Computing Language (OpenCL) is a high-level language that allows developers to produce portable software for heterogeneous parallel computing platforms. OpenCL is available for a variety of hardware platforms, with compiler support being recently expanded to include Field-Programmable Gate Arrays (FPGAs). This article investigates flexible OpenCL designs for the iterative min-sum decoding algorithm for (3,6)-regular Low-Density Parity Check (LDPC) codes over a range of codeword lengths. The target FPGA hardware is the Altera Stratix V GX A7 based Nallatech 385n board. The computationally demanding LDPC decoding algorithm offers several forms of parallelism that could be exploited by the Altera Offline Compiler (AOC version 15.1) for OpenCL. Our best decoder design produced a corrected codeword throughput of 68.22 Mbps at the compiler-selected FPGA clock frequency of 163.88 MHz for a length-2048 (3,6)-regular LDPC code. For a length-1024 (3,6)-regular LDPC code, our best design produced a throughput of 54.8 Mbps (32 decoding iterations) which significantly improves on the throughput of around 7 Mbps (30 decoding iterations) produced by an OpenCL based decoder design reported by Falcao et al. for the same size of LDPC code.

Compiler Support for the Fortran 2003 and 2008 Standards Revision 21

column Share on Compiler Support for the Fortran 2003 and 2008 Standards Revision 21 Authors: Ian Chivers Rhymney Consulting, London, UK Rhymney Consulting, London, UKView Profile , Jane Sleightholme FortranPlus, London, UK FortranPlus, London, UKView Profile Authors Info & Claims ACM SIGPLAN Fortran ForumVolume 36Issue 1April 2017 pp 21–42https://doi.org/10.1145/3068783.3068785Published:22 March 2017Publication History 0citation70DownloadsMetricsTotal Citations0Total Downloads70Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

LD

Data race detection has become an important problem in GPU programming. Previous designs of CPU race-checking tools are mainly task parallel and incur high overhead on GPUs due to access instrumentation, especially when monitoring many thousands of threads routinely used by GPU programs. This article presents a novel data-parallel solution designed and optimized for the GPU architecture. It includes compiler support and a set of runtime techniques. It uses value-based checking, which detects the races reported in previous work, finds new races, and supports race-free deterministic GPU execution. More important, race checking is massively data parallel and does not introduce divergent branching or atomic synchronization. Its slowdown is less than 5 × for over half of the tests and 10 × on average, which is orders of magnitude more efficient than the cuda-memcheck tool by Nvidia and the methods that use fine-grained access instrumentation.

A 5.3 pJ/op approximate TTA VLIW tailored for machine learning

To achieve energy efficiency in the Internet-of-Things (IoT), more intelligence is required in the wireless IoT nodes. Otherwise, the energy required by the wireless communication of raw sensor data will prohibit battery lifetime, the backbone of IoT. One option to achive this intelligence is to implement a variety of machine learning algorithms on the IoT sensor instead of the cloud. Shown here is sub-milliwatt machine learning accelerator operating at the Ultra-Low Voltage Minimum-Energy Point. The accelerator is a Transport Triggered Architecture (TTA) Application-Specific Instruction-Set Processor (ASIP) targeted for running various Machine Learning algorithms. The ASIP is implemented in 28nm FDSOI (Fully Depleted Silicon On Insulator) CMOS process, with an operating voltage of 0.35V, and is capable of 5.3pJ/cycle and 1.8nJ/iteration when performing conventional machine learning algorithms. The ASIP also includes hardware and compiler support for approximate computing. With the machine learning algorithms, computing approximately brings a maximum of 4.7% energy savings.

Static Instruction Scheduling for High Performance on Limited Hardware

Complex out-of-order (OoO) processors have been designed to overcome the restrictions of outstanding long-latency misses at the cost of increased energy consumption. Simple, limited OoO processors are a compromise in terms of energy consumption and performance, as they have fewer hardware resources to tolerate the penalties of long-latency loads. In worst case, these loads may stall the processor entirely. We present Clairvoyance, a compiler based technique that generates code able to hide memory latency and better utilize simple OoO processors. By clustering loads found across basic block boundaries, Clairvoyance overlaps the outstanding latencies to increases memory-level parallelism. We show that these simple OoO processors, equipped with the appropriate compiler support, can effectively hide long-latency loads and achieve performance improvements for memory-bound applications. To this end, Clairvoyance tackles (i) statically unknown dependencies, (ii) insufficient independent instructions, and (iii) register pressure. Clairvoyance achieves a geomean execution time improvement of 14 percent for memory-bound applications, on top of standard O3 optimizations, while maintaining compute-bound applications’ high-performance.

F ree R ider

Short-vector S imd and D sp instructions are popular extensions to common I sa s. These extensions deliver excellent performance and compact code for some compute-intensive applications, but they require specialized compiler support. To enable the programmer to explicitly request the use of such an instruction, many C compilers provide platform-specific intrinsic functions, whose implementation is handled specially by the compiler. The use of such intrinsics, however, inevitably results in nonportable code. In this article, we develop a novel methodology for retargeting such nonportable code, which maps intrinsics from one platform to another, taking advantage of similar intrinsics on the target platform. We employ a description language to specify the signature and semantics of intrinsics and perform graph-based pattern matching and high-level code transformations to derive optimized implementations exploiting the target’s intrinsics, wherever possible. We demonstrate the effectiveness of our new methodology, implemented in the F ree R ider tool, by automatically retargeting benchmarks derived from O pen CV samples and a complex embedded application optimized to run on an A rm C ortex -M4 to an I ntel E dison module with S se 4.2 instructions (and vice versa). We achieve a speedup of up to 3.73 over a plain C baseline, and on average 96.0% of the speedup of manually ported and optimized versions of the benchmarks.

Compiler Support for the Fortran 2003 and 2008 Standards Revision 20

column Share on Compiler Support for the Fortran 2003 and 2008 Standards Revision 20 Authors: Ian Chivers Rhymney Consulting, London, UK Rhymney Consulting, London, UKView Profile , Jane Sleightholme FortranPlus, London, UK FortranPlus, London, UKView Profile Authors Info & Claims ACM SIGPLAN Fortran ForumVolume 35Issue 3December 2016 pp 29–50https://doi.org/10.1145/3022868.3022870Published:06 December 2016Publication History 1citation57DownloadsMetricsTotal Citations1Total Downloads57Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Compiler Support for the Fortran 2003 and 2008 Standards Revision 19

Compiler Support for the Fortran 2003 and 2008 Standards Revision 19

Compiling Affine Loop Nests for a Dynamic Scheduling Runtime on Shared and Distributed Memory

Current de-facto parallel programming models like OpenMP and MPI make it difficult to extract task-level dataflow parallelism as opposed to bulk-synchronous parallelism . Task parallel approaches that use point-to-point synchronization between dependent tasks in conjunction with dynamic scheduling dataflow runtimes are thus becoming attractive. Although good performance can be extracted for both shared and distributed memory using these approaches, there is little compiler support for them. In this article, we describe the design of compiler--runtime interaction to automatically extract coarse-grained dataflow parallelism in affine loop nests for both shared and distributed-memory architectures. We use techniques from the polyhedral compiler framework to extract tasks and generate components of the runtime that are used to dynamically schedule the generated tasks. The runtime includes a distributed decentralized scheduler that dynamically schedules tasks on a node. The schedulers on different nodes cooperate with each other through asynchronous point-to-point communication, and all of this is achieved by code automatically generated by the compiler. On a set of six representative affine loop nest benchmarks, while running on 32 nodes with 8 threads each, our compiler-assisted runtime yields a geometric mean speedup of 143.6× (70.3× to 474.7× ) over the sequential version and a geometric mean speedup of 1.64× (1.04× to 2.42× ) over the state-of-the-art automatic parallelization approach that uses bulk synchronization . We also compare our system with past work that addresses some of these challenges on shared memory, and an emerging runtime (Intel Concurrent Collections) that demands higher programmer input and effort in parallelizing. To the best of our knowledge, ours is also the first automatic scheme that allows for dynamic scheduling of affine loop nests on a cluster of multicores.

Compiler Support for the Fortran 2003 and 2008 Standards Revision 18

column Share on Compiler Support for the Fortran 2003 and 2008 Standards Revision 18 Authors: Ian Chivers Rhymney Consulting, London Rhymney Consulting, LondonView Profile , Jane Sleightholme FortranPlus, London FortranPlus, LondonView Profile Authors Info & Claims ACM SIGPLAN Fortran ForumVolume 35Issue 1April 2016 pp 9–29https://doi.org/10.1145/2922512.2922513Published:15 April 2016Publication History 0citation89DownloadsMetricsTotal Citations0Total Downloads89Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A Framework for Practical Dynamic Software Updating

Dynamic software updating (DSU) enables a program to be patched on the fly without being shutdown. This paper addresses the practicality problem of the recent research on DSU systems, and presents Replus, a new DSU system that balances practicality and functionality. Replus aims to retain backward binary compatibility and support multi-threaded programs. In addition, it does not require customers to have developer-level software knowledge. More importantly, without specific compiler support, Replus can patch programs that are difficult to be updated at runtime, as well as programs that may incur an indefinite delay in DSU. The key technique of our solution is to update the stack elements for the patched program using two new mechanisms: Immediate Stack Updating , which immediately updates the stack of a thread, and timely stack updating , which only updates the stack frames of the necessary functions without affecting others. Replus also develops an Instruction Level Updating mechanism, which is more efficient for certain security patches. We used popular server applications as test suites to evaluate the effectiveness of Replus. The experimental results demonstrated that Replus can successfully update all the test suites with negligible impact on application performance.

Refined transactional lock elision

Transactional lock elision (TLE) is a well-known technique that exploits hardware transactional memory (HTM) to introduce concurrency into lock-based software. It achieves that by attempting to execute a critical section protected by a lock in an atomic hardware transaction, reverting to the lock if these attempts fail. One significant drawback of TLE is that it disables hardware speculation once there is a thread running under lock. In this paper we present two algorithms that rely on existing compiler support for transactional programs and allow threads to speculate concurrently on HTM along with a thread holding the lock. We demonstrate the benefit of our algorithms over TLE and other related approaches with an in-depth analysis of a number of benchmarks and a wide range of workloads, including an AVL tree-based micro-benchmark and ccTSA, a real sequence assembler application.

ROOT 6 and beyond: TObject, C++14 and many cores.

Following the release of version 6, ROOT has entered a new area of development. It will leverage the industrial strength compiler library shipping in ROOT 6 and its support of the C++11/14 standard, to significantly simplify and harden ROOT's interfaces and to clarify and substantially improve ROOT's support for multi-threaded environments. This talk will also recap the most important new features and enhancements in ROOT in general, focusing on those allowed by the improved interpreter and better compiler support, including I/O for smart pointers, easier type safe access to the content of TTrees and enhanced multi processor support.

Compiler Support for the Fortran 2003 and 2008 Standards Revision 17

Compiler Support for the Fortran 2003 and 2008 Standards Revision 17