Compile Time Research Articles

Improved Parallel Scanner for the Concurrent Execution of Lexical Analysis Tasks on Multi-Core Systems

Purpose: The processing power of machines will continue to accelerate massively. Modern eras of computing are driven by elevated parallel processing by the revolution of multi-core processors. This continuing trend toward parallel architectural paradigms facilitates parallel processing on a single machine and necessitates parallel programming in order to utilize the machine's enormous processing power. As a consequence, scanner generator applications will eventually need to be parallelized in order to fully leverage the throughput benefits of multi-core processors. This article discusses the way of processing the tasks in parallel during the scanning stage of lexical analysis. This is done by recognizing tokens in different lines of the source program in parallel along with auto detection of keyword in a character stream. Tasks are allocated line-by-line to the multiple instances of the lexical analyzer program. Then, each of the instances is run in parallel to detect tokens on different cores that are not yet engaged. Design/Methodology/Approach: Developing a theoretical and experimental approach for parallelizing the lexical scanning process on a multi-core system. Findings/Result: Based on the developed model, the theoretical and practical results indicate that the suggested methodology outperforms the sequential strategy in terms of tokenization consistently. It significantly decreases the amount of time spent on lexical analysis during the compilation process. It is clearly observed that the speedup should increase at or close to the same rate as the number of cores and keywords in the source program increases. This enhancement would improve the overall compilation time even more. Originality/Value: A hybrid model is developed for the concurrent execution of a lexical analyzer on multi-core systems using a dynamic task allocation algorithm and an auto-keyword detection method. Paper Type: Experimental Research.

Improved Parallel Scanner for the Concurrent Execution of Lexical Analysis Tasks on Multi-Core Systems

Purpose: The processing power of machines will continue to accelerate massively. Modern eras of computing are driven by elevated parallel processing by the revolution of multi-core processors. This continuing trend toward parallel architectural paradigms facilitates parallel processing on a single machine and necessitates parallel programming in order to utilize the machine's enormous processing power. As a consequence, scanner generator applications will eventually need to be parallelized in order to fully leverage the throughput benefits of multi-core processors. This article discusses the way of processing the tasks in parallel during the scanning stage of lexical analysis. This is done by recognizing tokens in different lines of the source program in parallel along with auto detection of keyword in a character stream. Tasks are allocated line-by-line to the multiple instances of the lexical analyzer program. Then, each of the instances is run in parallel to detect tokens on different cores that are not yet engaged. Design/Methodology/Approach: Developing a theoretical and experimental approach for parallelizing the lexical scanning process on a multi-core system. Findings/Result: Based on the developed model, the theoretical and practical results indicate that the suggested methodology outperforms the sequential strategy in terms of tokenization consistently. It significantly decreases the amount of time spent on lexical analysis during the compilation process. It is clearly observed that the speedup should increase at or close to the same rate as the number of cores and keywords in the source program increases. This enhancement would improve the overall compilation time even more. Originality/Value: A hybrid model is developed for the concurrent execution of a lexical analyzer on multi-core systems using a dynamic task allocation algorithm and an auto-keyword detection method. Paper Type: Experimental Research.

Two decades of automatic amortized resource analysis

AbstractThis article gives an overview of automatic amortized resource analysis (AARA), a technique for inferring symbolic resource bounds for programs at compile time. AARA has been introduced by Hofmann and Jost in 2003 as a type system for deriving linear worst-case bounds on the heap-space consumption of first-order functional programs with eager evaluation strategy. Since then AARA has been the subject of dozens of research articles, which extended the analysis to different resource metrics, other evaluation strategies, non-linear bounds, and additional language features. All these works preserved the defining characteristics of the original paper: local inference rules, which reduce bound inference to numeric (usually linear) optimization; a soundness proof with respect to an operational cost semantics; and the support of amortized analysis with the potential method.

ACE-M: Automated Control Flow Integrity Enforcement Based on MPUs at the Function Level

Control-flow integrity(CFI) ensures that the execution flow of a program follows the control-flow graph(CFG) determined at compile time. CFI is a security technique designed to prevent runtime attacks such as return-oriented programming (ROP). With the development of the Internet of Things (IoT), the number of embedded devices has increased, and security and protection techniques in embedded systems have become important. Since the hardware-based CFI technique requires separate hardware support, it is difficult to apply to an embedded device that is already arranged. In this paper, we propose a function-level CFI technique named ACE-M, which uses the memory protection unit (MPU) included in most embedded devices. MPU may provide attributes such as read-write-execute to the memory area. ACE-M has three steps: (1) initiate—inserts an MPU-related function into a specific position; (2) profiling—provides information for MPU configuration. After the initation step, several pieces of information can be determined; (3) set—modify the already-inserted function’s arguments. We propose a design that supports the MPU. In our model, the MPU becomes a control flow monitor that detects control flow errors(CFEs), and the inserted codes cause the MPU to act as a control flow checker. If the program deviates from the original control flow, the MPU raises an exception since its corresponding area will not be included in the executable area. This approach not only verifies the target address but also guarantees the running position. Our technique can detect any modification of the program counter (PC) to an arbitrary address.

Carlomat_4.0, a new version of the general purpose Monte Carlo program

A new version of the general purpose Monte Carlo program carlomat is presented that substantially improves efficiency of the phase space integration by automatic inclusion of parameterizations which map away the t-channel poles and peaks due to soft and collinear photon or gluon emission. The quadruple precision versions of the routines for computation of the helicity amplitudes and phase-space parameterizations have been written and calls to them implemented in the code generation part of the program. This allows to better control numerical stability of the Monte Carlo programs generated, in particular for reactions with a virtual photon or gluon exchange in the t-channel. A new option of generating s-channel kinematics has been added which takes into account peaks due to Feynman propagators of intermediate bosons which decay into on shell final state particles, or of the top quark. It speeds up both the compilation and execution time of the Monte Carlo programs with respect to the kinematics based on topologies of the Feynman diagrams used in versions 2 and 3 of carlomat. To further speed up the execution time, the main routine of the Monte Carlo program has been supplemented with the Message Passing Interface which allows to run the program parallelly on several processors. Program summaryProgram Title:carlomat, version 4.0CPC Library link to program files:https://doi.org/10.17632/9rx84cpvwc.1Developer's repository link:https://www.kk.us.edu.pl/carlomat.htmlLicensing provisions: GPLv3Programming language: Fortran 90/95Supplementary material: ‘instructions.pdf’Journal reference of previous version: Comput. Phys. Commun. 196 (2015) 563Does the new version supersede the previous version?: YesReasons for the new version: Efficient integration over a multi particle phase space can be a challenging task. Phase space parameterizations allowing to smoothen t-channel poles, or peaks due to soft and collinear photon or gluon emission, which were not taken into account in former versions of carlomat, are now included in the multichannel Monte Carlo integration routine automatically generated by the program. This allows to obtain more reliable predictions for quite a number of reactions that are of interest, either as signal or potential sources of background, both in high or low energy particle colliders.Summary of revisions: Phase space integration routines, originally developed in Phys. Rev. D43 (1991) 3619 and Comput. Phys. Commun. 159 (2004) 106, have been brought to the form suitable for implementation in the general purpose Monte Carlo (MC) program. The code generation part of carlomat has been appropriately modified in order to include new phase space parameterizations in the automatically generated multichannel MC integration routine. Quadruple precision versions of the routines for computation of the helicity amplitudes and phase-space parameterizations have been written and calls to them implemented in the code generation part of carlomat. A number of new options have been introduced in the program which allow to control generation of the multichannel integration routine and the process of MC integration. Among them a new option of generating s-channel kinematics has been added which takes into account peaks due to Feynman propagators of intermediate bosons which decay into on shell final state particles, or of the top quark. It speeds up both the compilation and execution time of the Monte Carlo programs with respect to the kinematics based on topologies of the Feynman diagrams used in versions 2 and 3 of the program. To further speed up the execution time, the main routine of the Monte Carlo program has been supplemented with the Message Passing Interface in order to allow for a parallel run of the program on several processors.Nature of problem: Automatic generation of the MC codes for a wide class of reactions that can be measured in current and future accelerators.Solution method: The Fortran 90/95 MC programs are generated with a meta program that is also written in Fortran 90/95. All amenities of the former versions of carlomat are kept in the current version, too.

Sherlock: A Multi-Objective Design Space Exploration Framework

Design space exploration (DSE) provides intelligent methods to tune the large number of optimization parameters present in modern FPGA high-level synthesis tools. High-level synthesis parameter tuning is a time-consuming process due to lengthy hardware compilation times—synthesizing an FPGA design can take tens of hours. DSE helps find an optimal solution faster than brute-force methods without relying on designer intuition to achieve high-quality results. Sherlock is a DSE framework that can handle multiple conflicting optimization objectives and aggressively focuses on finding Pareto-optimal solutions. Sherlock integrates a model selection process to choose the regression model that helps reach the optimal solution faster. Sherlock designs a strategy based around the multi-armed bandit problem, opting to balance exploration and exploitation based on the learned and expected results. Sherlock can decrease the importance of models that do not provide correct estimates, reaching the optimal design faster. Sherlock is capable of tailoring its choice of regression models to the problem at hand, leading to a model that best reflects the application design space. We have tested the framework on a large dataset of FPGA design problems and found that Sherlock converges toward the set of optimal designs faster than similar frameworks.

A Parallelized Qubit Mapping Algorithm for Large-scale Quantum Circuits

Quantum computers are superior to existing classical supercomputers in terms of run time for specific tasks, and various studies on quantum computers are in progress. Despite this, there is a significant gap in technology between available technologies and actual quantum computers on the noisy intermediate-scale quantum-scale. Currently, various quantum algorithms have been implemented and verified using quantum simulations. Therefore, the runtime performance of a quantum circuit can be verified in the same environment as a real quantum machine. A quantum compiler compiles quantum circuits. When a quantum circuit is compiled, logical qubits in a quantum circuit should be mapped to physical qubits, called qubit mapping. As qubit mapping is an NP-Complete problem, the compilation time increases exponentially according to the number of qubits. Therefore, various studies on effective qubit mapping techniques have been developed to accelerate the execution time. This paper proposes a new parallelized Qubit mapping algorithm. The proposed method consists of three-step processes: one circuit is divided into several circuits; the SABRE enhanced algorithm is executed on each circuit in parallel and then merged. The performance was evaluated using 10 benchmarks. The experimental results revealed an acceleration of up to 6.42x and an average speed up of 4.8x, with an average overhead of 1.03x in terms of the number of gates obtained. The proposed method outperformed the well-known modern qubit-mapping algorithm in terms of the execution time with exponential speedup improvement.

Improving Loop Parallelization by a Combination of Static and Dynamic Analyses in HLS

High-level synthesis (HLS) can be used to create hardware accelerators for compute-intense software parts such as loop structures. Usually, this process requires significant amount of user interaction to steer kernel selection and optimizations. This can be tedious and time-consuming. In this article, we present an approach that fully autonomously finds independent loop iterations and reductions to create parallelized accelerators. We combine static analysis with information available only at runtime to maximize the parallelism exploited by the created accelerators. For loops where we see potential for parallelism, we create fully parallelized kernel implementations. If static information does not suffice to deduce independence, then we assume independence at compile time. We verify this assumption by statically created checks that are dynamically evaluated at runtime, before using the optimized kernel. Evaluating our approach, we can generate speedups for five out of seven benchmarks. With four loop iterations running in parallel, we achieve ideal speedups of up to 4× and on average speedups of 2.27×, both in comparison to an unoptimized accelerator.

Threaded Code Generation with a Meta-Tracing JIT Compiler.

Language implementation frameworks, e.g., RPython and Truffle/Graal, are practical tools for creating efficient virtual machines, including a well-functioning just-in-time (JIT) compiler. It is demanding to support multitier JIT compilation in such a framework for language developers. This paper presents an idea to generate threaded code by reusing an existing meta-tracing JIT compiler, as well as an interpreter design for it. Our approach does not largely modify RPython itself but constructs an effective interpreter definition to enable threaded code generation in RPython. We expect our system to be extended to support multilevel JIT compilation in the RPython framework. We measured the potential performance of our threaded code generation by simulating its behavior in PyPy. We confirmed that our approach reduced code sizes by 80 \% and compilation times by 60 \% compared to PyPy's JIT compiler on average, and ran about 7 \% faster than the interpreter-only execution.

FineDIFT: Fine-Grained Dynamic Information Flow Tracking for Data-Flow Integrity Using Coprocessor

Dynamic Information Flow Tracking (DIFT) is a technique that facilitates run-time data-flow analysis on a running process, allowing a system to overcome the limitations of finding data dependencies statically at compilation time. DIFT serves as the backbone for applications including data-flow integrity (DFI). However, previous uses of DIFT towards DFI often have large overhead in terms of hardware, software or both, and often cannot provide fine-granularity tracking for software object, such as variables. To address these limitations, we present FineDIFT as a DFI framework which utilizes DIFT to generate a live data-flow graph of a running process and perform hardware-based assisted analysis at fine-granularity, thus being able to enforce the application’s Data-Flow Graph (DFG). We provide a sample implementation on a RISC-V core with a performance overhead of 5.03% for BEEBS benchmarks and hardware overhead of 6% LUTs and 8% Flip-Flops in the FPGA implementation, if excluding the Content-Addressable Memory (CAM) like structure used for metadata storage. With CAM-like structure being synthesized using FPGA logic, the total hardware overhead is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 2 \times $ </tex-math></inline-formula> LUTs and 33% Flip-Flops compared to the original RISC-V core. We also use the real-world application and customized vulnerable application to demonstrate the effectiveness of the proposed framework in protecting computing systems.

IMPROVING ECONOMIC AND TECHNICAL EFFICIENCY OF PROCEDURAL PROGRAMMING IN COMPILABLE, STATICALLY TYPED C-LIKE LANGUAGES ACCORDING TO THE SPEED OF THE PROCESS AND THE STABILITY OF THE PROGRAM IMPLEMENTATION

In the modern IT industry, there is a trend towards languages with high performance. The products implemented through them become more efficient and energy-saving. However, these languages have a number of disadvantages based on their technical implementation. These defects create side problems over time and increase the cost of implementing, securing, configuring, and extending the functionality of the product. Thus, the product becomes more expensive from a financial point of view, but more competitive. In order to further increase the competitiveness of products, to neutralize side problems, to reduce the cost, companies listed in international indexes and universities with global scientific qualifications either develop a new language, or update and add new functionality to the already existing language. The article presents recommendations for compilable, statically typed, C-like languages to make their procedural programming safer. They will ensure readability and increase the speed of the process. These changes will make IT products more competitive in the free market. The advantage of recommendations is that the most time-consuming checks and decisions will be made at compile time. There are some examples of the changes in the article.

The problems of history of creation of alisher navoi's works

This article is devoted to the history of creation of the works of Alisher Navoi. It considers the history of the collection “Hazoin ul - Maoniy” (“Treasury of Thoughts”), the poem Saddi Iskandari (Alexander's Wall) and the religious work Siroj ul-Muslimin (“The Light of Muslims”). The author pays special attention to such issues as the time of compilation of “Hazoin ul -Maoniy ”(“Treasury of Thoughts”) and in what period of the poet's life and conditions the poems were included in the collection. Conclusions obtained as a result of author's research are set out in the end of the article. The article also clarified the issue related to the history of the creation of Siroj ul -Muslimin (“The Light of Muslims”).

Assessment of static type checking compliance of EOLANG

The EOLANG programming language is a novel technology relying on formal phi-calculus similar to lambda-calculus for functional programming languages, and on design choices declared as mitigating most weak points of mainstream object-oriented programming languages. EO is under active development up to date and has some obvious development vectors. One of these vectors is development of compilation time type checker. With dynamic type checking provided by now, writing and testing programs in EO takes long and is vulnerable to bugs. In this paper the assessment of static type checking compliance of EOLANG is performed. The results reveal serious weak points in EOLANG implementation and theoretical basis making development of static type checker impossible.

Type specimens in the fish collection of the National Museum of Natural History, National Academy of Sciences of Ukraine

The creation of a collection of type specimens of fishes of the National Museum of Natural History NAS of Ukraine has started in 1974. In the following years, the collection of fish type specimens of the Zoological Museum was enriched by both national and foreign specialists such as E. E. Meisner, L. G. Manilo, G. A. Shandikov, D. A. Didier and M. Stehmann, M. R. De Carvalho and others. Some of these specimens (holotypes and paratypes of eight cartilaginous and bony fishes described at that time) were included into the first catalogue of type specimens of all groups of invertebrates and vertebrates of the Zoological Museum (Catalogue… 2001). This catalogue includes information on 73 type specimens of fishes (10 holotypes and 63 paratypes) belonging to 12 species of 6 families: Acroteriobatus stehmanni Weigmann, Ebert, Séret, 2021; Raja taaf Meisner, 1987; Torpedo adenensis Carvalho, Stehmann, Manilo, 2002; Neoharriotta pumila Didier, Stehmann, 1996; Channichthys aelitae Shandikov, 1995; Channichthys bospori Shandikov, 1995; Channichthys irinae Shandikov, 1995; Channichthys mithridatis Shandikov, 2008; Channichthys panticapaei Shandikov, 1995; Channichthys richardsoni Shandikov, 2011; Channichthys velifer Meisner, 1974; Parapercis ventromaculata Manilo, 1990, stored in the fish collection of the National Museum of Natural History NAS of Ukraine. Two taxa were not found in the collection: the holotype of Arius dayi Dmitrenko, 1974 (lost), as well as the holotype and paratypes of Romanogobio albipinnatus tanaiticus Naseka, 2001 (not received from the author of the description). The number of paratypes of each species (subspecies) is given according to their presence in the collection as of the time of compilation of this catalogue. In the text, after the Latin name of species (subspecies), the following information is given: collection record number, number of paratype specimens, length (standard or absolute) in millimetres, full label information including water body, coordinates, name of the vessel and cruise number, depth, trawl (station) number, date of collection, and name of collectors.

SymPhas—General Purpose Software for Phase‐Field, Phase‐Field Crystal, and Reaction‐Diffusion Simulations

AbstractThis work develops a new open source application programming interface (API) and software package called SymPhas for simulations of phase‐field, phase‐field crystal, and reaction‐diffusion models, supporting up to three dimensions and an arbitrary number of fields. SymPhas delivers two novel program capabilities: 1) User specification of models from the associated dynamical equations in an unconstrained form and 2) extensive support for integrating user‐developed discrete‐grid‐based numerical solvers into the API. The capability to specify general phase‐field models is primarily achieved by developing a novel symbolic algebra functionality that can formulate mathematical expressions at compile time; is able to apply rules of symbolic algebra such as distribution, factoring, and automatic simplification; and support user‐driven expression tree manipulation. A modular design based on the C++ template meta‐programming paradigm is applied to the symbolic algebra library and general API implementation to minimize application runtime and increase the accessibility of the API for third party development. SymPhas is written in C/C++ and emphasizes high‐performance capabilities via parallelization with OpenMP and the C++ standard library. SymPhas is equipped with a forward Euler solver and a semi‐implicit Fourier spectral solver. Sample implementations and simulations of several phase‐field models are presented, generated using the semi‐implicit Fourier spectral solver.

Estimation of the Conditional Probability Using a Stochastic Gradient Process

The use of conditional probabilities has gained in popularity in various fields such as medicine, finance, and imaging processing. This has occurred especially with the availability of large datasets that allow us to extract the full potential of the available estimation algorithms. Nevertheless, such a large volume of data is often accompanied by a significant need for computational capacity as well as a consequent compilation time. In this article, we propose a low-cost estimation method: we first demonstrate analytically the convergence of our method to the desired probability and then we perform a simulation to support our point.

Structure verification of deep neural networks at compilation time

This paper presents TensorSafe , a Haskell library that makes possible the definition and structural validation of deep neural network architectures. Nowadays, the development process of deep learning models has been notably simplified due to the availability of sophisticated tools in the industry. However, most of these tools do not provide any security controls at compilation time, making the developers deal with unexpected run-time errors and uncertainties. In particular, validating the structure of deep neural networks at compilation time is a complex subject that involves the mathematical validation of all operations that a deep learning model will perform. Moreover, this structural checking requires an advanced usage of types systems theories to manipulate abstract type definitions capable of modeling neural network constructions. Many different programming techniques were involved in the specification of TensorSafe. Primarily, the application of the functional programming paradigm and the use of type-level programming were of great importance for the development process and to probe the correctness of the neural network models. The experimental evaluation showed that by using TensorSafe it is possible to correctly create well-known deep neural network architectures, such as AlexNet or ResNet50 . • Review state of the art of deep learning DSLs that provide structural controls at compile time. • Extensible Haskell library that is capable of defining non-sequential deep learning architectures. • Interaction with external deep learning frameworks like TensorFlow for JavaScript or Keras for Python.

Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks

In this paper, we present hardware accelerators created with high-level synthesis techniques for sparse and dense matrix multiplication operations. The cores can operate with different precisions and are designed to be integrated in a heterogeneous CPU-FPGA system for Edge AI applications. The methodology involves quantization-sparsity aware training and it is applied to a case study consisting of human activity classification. We initially investigate the effects of quantization and sparsity on the accuracy of neural networks with convolution, dense and recurrent layers observing better tolerance to pruning when recurrent layers are present. Then, we propose the hardware accelerators that can switch precision at run-time and work with any matrix size up to a maximum configured at compile time. We compare the performance of these accelerators at different levels of precision and sparsity levels and create a performance model to enable workload balancing. The results show that the proposed sparse matrix multipliers can outperform dense multipliers when sparsity levels are higher than 70% and the improvements are more evident when higher precision arithmetic or structural pruning is used. Additionally, sparsity levels as high as 99% can maintain the level of accuracy required in the network especially when recurrent layers are deployed. Overall, the balance between sparse and dense performance depends on matrix shape, precision, structural pruning and sparsity levels and performance modelling can be used to balance concurrent execution in a heterogeneous configuration.

RWRoute: An Open-source Timing-driven Router for Commercial FPGAs

One of the key obstacles to pervasive deployment of FPGA accelerators in data centers is their cumbersome programming model. Open source tooling is suggested as a way to develop alternative EDA tools to remedy this issue. Open source FPGA CAD tools have traditionally targeted academic hypothetical architectures, making them impractical for commercial devices. Recently, there have been efforts to develop open source back-end tools targeting commercial devices. These tools claim to follow an alternate data-driven approach that allows them to be more adaptable to the domain requirements such as faster compile time. In this paper, we present RWRoute, the first open source timing-driven router for UltraScale+ devices. RWRoute is built on the RapidWright framework and includes the essential and pragmatic features found in commercial FPGA routers that are often missing from open source tools. Another valuable contribution of this work is an open-source lightweight timing model with high fidelity timing approximations. By leveraging a combination of architectural knowledge, repeating patterns, and extensive analysis of Vivado timing reports, we obtain a slightly pessimistic, lumped delay model within 2% average accuracy of Vivado for UltraScale+ devices. Compared to Vivado, RWRoute results in a 4.9× compile time improvement at the expense of 10% Quality of Results (QoR) loss for 665 synthetic and six real designs. A main benefit of our router is enabling fast partial routing at the back-end of a domain-specific flow. Our initial results indicate that more than 9× compile time improvement is achievable for partial routing. The results of this paper show how such a router can be beneficial for a low touch flow to reduce dependency on commercial tools.

Model-based autotuning of discretization methods in numerical simulations of partial differential equations

We present an autotuning approach for compile-time optimization of numerical discretization methods in simulations of partial differential equations. Our approach is based on data-driven regression of performance models for numerical methods. We use these models at compile time to automatically determine the parameters (e.g., resolution, time step size, etc.) of numerical simulations of continuum spatio-temporal models in order to optimize the tradeoff between simulation accuracy and runtime. The resulting autotuner is developed for the compiler of a Domain-Specific Language (DSL) for numerical simulations. The abstractions in the DSL enable the compiler to automatically determine the performance models and know which discretization parameters to tune. We demonstrate that this high-level approach can explore a large space of possible simulations, with simulation runtimes spanning multiple orders of magnitude. We evaluate our approach in two test cases: the linear diffusion equation and the nonlinear Gray-Scott reaction–diffusion equation. The results show that our model-based autotuner consistently finds configurations that outperform those found by state-of-the-art general-purpose autotuners. Specifically, our autotuner yields simulations that are on average 4.2x faster than those found by the best generic exploration algorithms, while using 16x less tuning time. Compared to manual tuning by a group of researchers with varying levels of expertise, the autotuner was slower than the best users by not more than a factor of 2, whereas it was able to significantly outperform half of them.