Compensation Circuit Research Articles

A 1.2-V 0.959-ppm/°C multi-section curvature-compensated bandgap voltage reference with trimming

This article introduces a high-precision and low temperature coefficient(TC) bandgap reference (BGR) with a 1.2 V output voltage after a novel digital trimming. A multi-section curvature compensation circuit alleviates the variation caused by the temperature dependence of the base emitter nonlinear voltage of bipolar transistors. The novel digital trimming technology is utilized to reduce the TC and improve the output voltage precision(VP) of the proposed the BGR. Designed and simulated in a 65 nm CMOS process with an active area of 0.037 mm2. Simulation results of the proposed the BGR demonstrates that its output voltage is 1.2 V, the best TC is 0.959 ppm/°C over a −40 °C to 125 °C temperature range and the power consumption of 138 μW under 3.3 V supply voltage at room temperature with trimming. In the supply voltage range of 1.8–3.4 V, the line regulation (LR) is 0.25%/V.

A New Piecewise-Compensated Bandgap Reference Circuit with a Trimming Procedure

A new CMOS bandgap reference (BGR) circuit with a piecewise-compensation circuit and a trimming network is proposed and designed to obtain a bandgap reference voltage with a low-temperature coefficient and a high precision, taking into account the effect of non-ideal factors on the results. The proposed piecewise compensation circuit is designed to achieve a constant reference voltage by using a current mirror to mirror the current, combined with a subtractive circuit and an additive circuit to obtain a low-temperature coefficient over an extensive temperature range. The trim network part is used to change the voltage value of the output reference by controlling the magnitude of the resistance value of the resistors connected to the circuit. The design and simulation of the proposed bandgap reference circuit are obtained by using Cadence Spectre simulation by SMIC 0.18 μm CMOS technology. The results indicates that when the power is 3.3 V and the temperature scope is within -40 °C to 125 °C, the output voltage is 1.2 V with the temperature coefficient equal to 0.658 ppm/°C. When the power varies within 3.2 V to 3.4 V, the linear regulating rate is 0.001019 %/V.

Double-Sided LCC Compensation Network and Its Tuning Method for Wireless Power Transfer for EV charging

Abstract: This research explores a double-sided LCC compensation network's utilization in an inductively coupled wireless power transfer (WPT) system for electric car charging applications and its wireless power transfer tuning procedure (WPT). A wireless power transmission system is offered with a double-sided LCC compensating network. The compensation circuit is crucial because it may be used to adjust the system's resonance frequency, lower reactive power in the power electronics converter, and boost the efficiency and capability of transferred power. The proposed architecture and its tuning technique allow the system to operate at a constant switching frequency since the resonant frequency is unaffected by the coupling coefficient between the two coils and is also independent of the load status. Also, it has been discovered that the corrected receiving coil inductance is a useful tuning parameter for ensuring the primary side zero voltage switching (ZVS) operation.

Investigation of current balance methodologies for inductive power transfer coupler with multiple branches

AbstractIn the inductive power transfer (IPT) system, using multiple coil branches instead of a whole large coil can effectively solve the thickness problem and save space. In that case, there are small parameter differences in mutual inductance and self‐inductance between the coil branches in parallel. These differences are amplified in high‐frequency IPT systems, resulting in different currents flowing through the different coil branches. The current unbalance will create many hazards. Therefore, this paper analyzes the key factors that cause current to unbalance and studies the equivalent circuit model of an inductive power transfer system with secondary multiple parallel branches. Moreover, this paper designs the compensation circuit and studies two kinds of current balance methods. Furthermore, the parameter design criteria are detailed to obtain a nearly ideal current balance effect. The characteristic analysis, parameter design, and verification are described in detail.

High-Power Converters and Challenges in Electric Vehicle Wireless Charging – A Review

This article reviews various inductive and capacitive wireless charging systems to achieve high-power infrastructures. The characteristics of SAE, ICINRP, and IEEE safety standards for wireless charging technology were highlighted. The working of compensation circuits, resonant converters, and challenges in wireless power transfer (WPT) systems was discussed. The mechanism of different compensation circuits used in the WPT was discussed in detail. In addition, the design of the converter circuit topology of inductive and capacitive power transfer systems in electric vehicle (EV) batteries was highlighted. The foreign object detection (FOD) methods that prevent output power variations due to metal/living objects in the charging environment were explored. The foreign object detection (FOD) techniques in terms of impedance variations in the primary side of the charging circuit were explained. This review on EVs would help researchers and industrialists to identify and develop novel charging infrastructure with low cost and charging time.

A biphasic current-mode stimulator integrated circuit with a novel residual charge compensation mechanism

A mixed-signal four-channel biphasic current-mode functional electrical stimulator chip with a novel charge compensation circuit is presented in this paper. This chip can induce programmable biphasic current ranging from 10 μA to 2.56 mA for each channel. However, a significant problem with functional electrical stimulation is charge balancing (CB) due to anodic and cathodic current mismatch for process variation. Therefore, a novel compensation module including both passive and active charge compensation schemes are adopted in this chip. The charge compensation module autonomously adjusts the supply and compensation current to achieve fast compensation and low-power consumption simultaneously. The proposed biphasic stimulator is designed and fabricated in a 0.18 μm CMOS process with a die area of 2.27 mm × 1.99 mm. The measurement results from a test bench demonstrate the proposed circuit functionalities, and the standby power consumption of this chip is 193.7 μW. Besides, animal experiments on mice for seizure suppression with deep brain stimulation were performed to verify the efficacy and safety of the developed stimulation chip.

Investigation of temperature variations on a Class-E inverter and proposing a compensation circuit to prevent harmful effects on biomedical implants

In this paper, a Class-E inverter and a thermal compensation circuit for wireless power transmission in biomedical implants are designed, simulated, and fabricated. In the analysis of the Class-E inverter, the voltage-dependent non-linearities of Cds, Cgd, and RON as well as temperature-dependent non-linearity of RON of the transistor are considered simultaneously. Close agreement of theoretical, simulated and experimental results confirmed the validity of the proposed approach in taking into account these nonlinear effects. The paper investigated the effect of temperature variations on the characteristics of the inverter. Since both the output power and efficiency decrease with increasing temperature, a compensation circuit is proposed to keep them constant within a wide temperature range to enable its application as a reliable power source for medical implants in harsh environments. Simulations were performed and the results confirmed that the compensator enables significant improvements by maintaining the power and efficiency almost constant (8.46 ± 0.14 W and 90.4 ± 0.2%) within the temperature range of − 60 to 100 °C. Measurements performed at 25 °C and 80 °C with and without the compensation circuit were in good agreement with the theoretical and simulation results. The obtained measured output power and efficiency at 25 °C are equal to 7.42 W and 89.9%.

A Stage–Stage Dead-Band Compensated Multiband RF Energy Harvester for Sensor Nodes

This article presents a dead-band compensated multiband stacked electromagnetic energy harvester for powering sensor nodes. It is adaptive for typical ambient radio frequency (RF) power levels found within the environment. A stage–stage feedforward technique is adopted in the proposed harvester to enhance the output voltage, in turn, harvested power and sensitivity. Moreover, a compensation circuit is included in the design for bypassing the inactive bands to avoid unexcited band rectifier diodes. A prototype is designed to cover four frequency bands GSM (900 and 1800 MHz), 4G-LTE (2.3 GHz), and Wi-Fi (2.4 GHz) and further integrated with a TI BQ25570 power converter. The analytical, simulated, and measured results show the increment in the output voltage with the frequency bands. The measured efficiency of the RF-to-dc converter is 44.2% at −20-dBm input power and 89% at 0 dBm. The efficiency is improved by 13% on average under dead-band compensation. With the multiband stacking, the harvester achieves a start-up voltage of 320 mV at −24 dBm and is found to be efficient to drive a temperature sensor STLM20 at −12-dBm input power.

A Circuit Design Method for Constant Voltage Output With Zero Phase Angle and Minimum Coupler Voltages in Capacitive Power Transfer

Constant output characteristics, zero phase angle (ZPA), and coupler voltage stresses as low as possible are practical requirements for high power and large air-gap capacitive power transfer (CPT) applications. This article derives conditions of load-independent constant voltage output, ZPA, and minimum coupler voltages for general CPT systems, respectively. Minimum degrees of freedom (DOF) for the above performance are analyzed. Given performance requirements, a systematic circuit design method based on DOF analysis is proposed to design compensation circuits with fewer components to simplify complexity and decrease costs. The proposed method can predict feasible topologies, and application considerations are provided to guide topology selection. A 3 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -compensated CPT system is proposed to realize the constant voltage output with ZPA, minimum coupler voltages, and efficiency optimization. A 2.2 kW CPT prototype has been prepared with a 250 mm air-gap distance and dc–dc efficiency is 87.2%. Rms values of coupler voltages are about 5 kV at the rated power.

Dynamic Compensation Optimization and Frequency Characteristic Analysis for Contactless Energy Transfer Under Load Variations in Rotary Ultrasonic Machining

In rotary ultrasonic machining, contactless energy transfer (CET) converts power from an ultrasonic power supply to the ultrasonic transducers. Two-side compensation circuits improve the efficiency of this process, but the addition of secondary compensation causes problems such as dynamic imbalance. Load changes affect the performance of CET system (CETS) with compensation, and dynamic compensation is needed for good CETS performance, such as high transfer efficiency and output power. This article investigates the frequency characteristics of CETS without compensation under different loads. The effects of two-side compensation on CETS under load variations is studied for the dynamic compensation characteristic. The comparison of mathematical model and performance of CETS with dynamic compensation are investigated to propose the optimized dynamic compensation. The model of CETS with optimized dynamic compensation under load variations is developed. The CETS frequency characteristics with optimized dynamic compensation are studied. The experimental results basically agree with the calculated results. The CETS with optimized dynamic compensation at the series resonant frequency can produce high transfer efficiency, high output power, low input impedance range under load variations in the cutting process of RUM, and solves the problems caused by the secondary side compensation.

Development of an EGFET microsensor with 3D structure for high-specificity cardiac troponin I detection

In this study, we used microelectromechanical systems (MEMS) technology to design a three-dimensional microsensor, which is based on an extended gate field-effect transistor (EGFET), to detect cardiac troponin (cTnI). A planar micro-reference electrode was integrated onto the same chip. All fabrication processes were compatible with integrated circuit and MEMS technologies, and the dimension of our cTnI microsensor was 1.0 cm × 0.8 cm. From measurements, microsensor sensitivity was 11.408 V (ng ml−1)−1 and sensing linearity was 0.961 in the 0–0.05 ng ml−1 range. In the 0.05–1 ng ml−1 range, sensitivity was 0.887 V (ng ml−1)−1 and linearity 0.933. The detection limit was 0.0063 ng ml−1, and the response time was approximately 300 s. Bridge-type source read-out, temperature correction and temperature compensation circuits were also successfully designed and were used to reduce the influence of temperature on sensing signals.

Sensorless Current Pulsation Compensation in a Hybrid Energy Storage

This paper presents a dual active bridge DC/DC converter used as an AC current compensator in a hybrid energy storage application. The AC current in the DC link appears when a three-phase, four-wire inverter operates with unbalanced output currents—for example, when trying to compensate for grid voltage unbalance. This AC current has adverse effects on the operation of the electrochemical energy storage, and it should be compensated. To achieve this, a compensator is introduced into the DC link circuit of the inverter—a DC/DC converter with a capacitor bank. The DC/DC converter is responsible for compensating the AC pulsation by creating its own pulsation with the opposite phase. In the paper, the genesis of this pulsation is explained, and a compensation circuit is proposed along with a sensorless compensation algorithm. The algorithm is based on symmetrical decomposition and is used to generate a reference signal for the compensator. The numerical analysis of the algorithm is presented, and the operation of the compensator is verified on the laboratory bench.

A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation.

This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is -54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of -20 to 80 °C, with a projected area of 0.003 mm2.

Sub-pT oscillatory magnetometric system using magnetoresistive sensor array for a low-field magnetic particle imaging

Implementing low ac excitation fields toward clinical magnetic particle imaging (MPI) system is critical to avoid magnetostimulation effects. However, low-field MPI scenario demands high sensitivity to probe the change in monotone magnetization response of magnetic nanoparticles. Here, we use an array of ultrasensitive MR sensors to detect sub-pT magnetic signal and obtain its spatial distribution. While each sensor is operated at 5 V, signal processing circuit rises its sensitivity to 20 mV pT−1 at 10 kHz with 0.25 pT noise level. In evaluating sensor performance, we initially measured a 10-kHz magnetic field from a 40-turns coil with 1 mm in diameter. MR sensor recognizes magnetic signal of mini coil to be linear with the coil input current. We then recorded the signals simultaneously from a 6 × 6 sensor channels to map the fields at 0.2 kHz. While placing mini coil 50 mm apart from the array, we obtained high-contrast field image showing coil position and its change in field polarity. For practical nanoparticle detection, we later used a 3 × 3 array configuration for the 10 kHz oscillatory magnetometry while compensating the MR sensor magnetically from the ac excitation field. Despite a 20-pT noise floor associated with the field compensation circuit, we were able to map stray fields of a 37-mgFe iron oxide nanoparticle sample distanced 100 mm from the array, under 12.4 µT/μ0 field amplitude. This result highlights usability of MR sensor array for low-field MPI system.

An area-efficient 1.96 nA 0.55 V 96 ppm/°C self-biased current reference using active resistor temperature coefficient compensation

This paper presents a simple scheme for a nano-ampere supply and temperature-stabilized current reference based on the well-known Beta multiplier circuit. Under the control of the proposed active resistor temperature coefficient compensation (TCC) circuit, the threshold voltage of the traditional active resistor in the triode region can be reduced and the temperature coefficient (TC) can be adjusted. The proposed current reference circuit was implemented using standard VTH (SVT) MOS devices and included active resistors (MΩ) to achieve area efficiency. The power consumption of the current reference generator designed using a 180 nm CMOS process was 9.2 nW at a supply voltage of 0.55 V. Monte-Carlo simulation results showed that the reference current was 1.96nA, temperature coefficient was 96 ppm/°C over a temperature range of 0–100 °C, and line sensitivity was 0.2 %/V for supply voltages ranging from 0.55 to 1.8 V. The active area was only 0.003 mm2.

ECONOMIC EFFICIENCY OF VOLTAGE AND TEMPERATURE DRIFT COMPENSATION CIRCUIT FOR DIGITAL DELAY LINE

Nowadays when semiconductor devices sizes reached to the few nanometers, high-speed SERDES systems became less power-consuming, and systems operating frequen-cies reached dozens of gigahertz. Despite these advantages, devices became more vulne-rable against temperature-voltage drifts. Also, because of dozens of gigahertz frequency data transmission, it became more complicated to meet timing constraints in Serdes sys-tems. Therefore, it is important to have stable de-skew mechanisms, otherwise data loss and other timing issues can be observed. One of the commonly used circuits to over-come this problem is digital delay lines (DDL). Often integrated circuits (IC) being used in non-standard environments, so it is necessity to have voltage-temperature (VT) compensation circuit (VTDCC), otherwise DDL will lose its effectiveness. The development of the proposed of VTDCC has become an economically important condition, because VTDCC allows digital delay line (DDL) to work correctly in non-standard conditions, which increases the demand for DDL. Digital delay line with included compensation circuit has shown around 51% DDL delay range improvement during non-standard conditions VT drift compensation circuit requires an additional 37% area in DDL.

A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory

Resistive random access memory (RRAM) is a promising emerging nonvolatile memory (NVM) due to its large resistance ratio in different switching states. To improve memory density and reduce cost-per-bit, multi-level cell (MLC) RRAM stores multiple bits in a single cell, compared to a single-level cell (SLC). However, random mismatch, process variation, and resistance shift lead to reliability issues, degrade the probability of correct read, and increase the bit error rate (BER). This paper presents a time-based sensing scheme for robust read operation and extends to multi-level sensing for SLC and MLC RRAM arrays. Bit line (BL) voltage is converted into time delay by a voltage-to-time converter (VTC) and compared with the implicit timing reference generated by a delay line. By detecting different states in the time domain, the proposed time-mode sense amplifier (TSA) requires no analog reference voltage or current, which is used in the conventional voltage-mode sense amplifiers (VSA) or current-mode sense amplifiers (CSA). Power gating is employed to enable the time sampling only at the sensing points to suppress the short-circuit current. A charge sharing-induced error compensation (CSEC) circuit is used to eliminate the charge sharing-induced voltage drop and expand the sense margin by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.56\times $ </tex-math></inline-formula> . Monte Carlo simulations in 40nm technology show that the proposed TSA improves read reliability and reduces BER by 3–4 orders of magnitude compared to conventional VSA and CSA. The proposed time-based sensing scheme operates from 0.7-1.2 V supply and consumes 49 fJ/bit for read operation under a nominal 1.2 V supply.

Источник тока с компенсацией падения выходного сопротивления для электроимпедансной томографии

Рассмотрен источник тока для электроимпедансной томографии с компенсацией падения выходного сопротивления, показана его структурная схема, описана аппаратная реализация. Представлена методика оценки стабильности выходных параметров источника тока, проведено сравнение источников тока с компенсацией падения выходного сопротивления и амплитуды и без нее соответственно. Сделан вывод, что при заданной амплитуде выходного тока в заданном диапазоне частот и сопротивлений источник тока со схемой компенсации падения выходного сопротивления обладает погрешностью на порядок меньше, чем традиционный источник тока с той же схемотехникой, и это положительно повлияет на метрологические характеристики всего устройства электроимпедансной томографии.

An Adaptive Slope Compensation Circuit for Peak Current Mode of Boost Switching Power Supply

An Adaptive Slope Compensation Circuit for Peak Current Mode of Boost Switching Power Supply

Approximate Multiplier based on Low power and reduced latency with Modified LSB design

The devised approximation multiplier can adapt the precision and processing power needed formul triplication sat run-time based on the needs of the user. To decrease error distance, we also suggest a straight forward error compensation circuit. There are two types of approximate multi pliers. Dynamic voltages caling can be used for the first kind, which controls the timing route of the multiplier. If the voltage is lower, the critical path will take longer to complete. As a result, when the time path is violated, errors occurs and approximated results are produced. These cond types involves redesigning precise multiplier circuits like the Wallace Tree Multiplier and Dadda Tree Multiplier in order to change the functional behaviors of multipliers. Most of the earlier research on rebuilding multipliers suggested erroneous m-n compressors, which have m inputs and producen outputs. It dynamically reduces the area covered under the multiplier LSB which enables the MSB in accurate manner and LSB in approximate manner. This convolution al system approach is regarded to sequential cover up more than 32 bit multiplier. Since the accompanied circuit reduce then tire area by10times lesser than original multiplier, this conventional unit is regarded as abled circuit in the segment. Since the process of compressing partial products absorbed the majority of the multiplier energy and resulted in a consider able route delay, these incorrect compressors were utilized to compress the partial products within multiplication. These functionality are over come through our experimental setup.