Compact Electrostatic Discharge Research Articles

Human Metal ESD: Design of a Full-Wave Model and an Improved Compact Generator

A full-size, full-wave human body model has been designed. Compared with a real human-metal electrostatic discharge (ESD), similar fields and currents are obtained from the numerical model. A resistive surface sheet is used in microwave studio to control the currents on the air-filled body. Its performance is verified by comparing it to the currents and fields from the real human ESD. A subcircuit models the time-dependent resistance of the spark using the well-known Rompe–Weizel spark resistance model. Real human metal ESD does not reveal the double hump shape as shown in the IEC standard. To create a generator that reproduces the real human metal ESD current waveform, a compact ESD generator was designed, which is based on matching the impedance of real human metal mode ESD with the impedance of the compact ESD generator. Furthermore, a circuit-based simulator is presented. It is based on a PCB implementation of the equivalent circuit of the human metal ESD.

Compact ESD Protection Cell for Multi-Band Millimeter-Wave Applications

A compact electrostatic discharge (ESD) protection cell is proposed for multi-band millimeter-wave (MMW) circuits in nanoscale CMOS technology. The proposed ESD protection cell consists of a silicon-controlled rectifier (SCR) and a diode as the main ESD protection devices, and an inductor in this cell is divided into several sections to resonate at multifrequencies. The proposed design has been demonstrated for 28- and 67-GHz applications. The measurement results show that the proposed design exhibits lower loss at the specified frequency bands, higher ESD robustness, and sufficiently small layout area. Therefore, the novel compact ESD protection cell will be better for multi-band MMW applications in CMOS technology.

Compact ESD Protection Design for CMOS Low-Noise Amplifier

A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the ${K}$ -band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified.

Single and compact ESD device Beta-Matrix solution based on bidirectional SCR Network in advanced 28/32 nm technology node

Advanced CMOS technologies, like CMOS32nm high K metal gate, become more and more sensitive to electrostatic discharge (ESD) phenomenon particularly because of their low overvoltage robustness. In this context, we develop a Beta-Matrix concept [1] which merges six silicon controlled rectifier (SCR) in a same structure and having one single triggering gate N (GN) for a high integration and high flexibility in IO frame. This device is the center of a new protection strategy which combined both local and global protection approach [1]. Also, a specific trigger circuit has been developed to turn-on Beta-Matrix whatever stressed pins during an ESD event and to keep it off when IC is in normal operation mode and is presented in [2]. Both, Beta-Matrix and trigger circuit, make a robust and very efficient ESD network which allows removing all IO placement constraint and power IO [3]. Also, this study is a synthesis of both previous work and a development of new Beta-Matrix topology to improve the device behavior, particularly by improving the uniformity of activation and decreasing triggering voltage of the structure. This work presents results of 3 dimensional TCAD simulations and measurements of transmission line pulse (TLP) and very fast-TLP.

Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology

Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.

A novel on-chip electrostatic discharge protection design for RF ICs

A novel, compact electrostatic discharge (ESD) protection structure is designed, which protects integrated circuits (ICs) against ESD damages in all modes. This ultra-fast-response ESD structure, with response time of t1∼0.16nS, operates symmetrically. Measurements showed desired low holding voltage (∼2V), low discharging impedance (<2Ω), high current handling capacity and adjustable triggering voltages. ESD testing passed HBM 14 and 15kV air-gap IEC zapping. Design prediction was achieved by comprehensive mixed-mode ESD simulation. The area-efficient ESD design features small Si consumption, low parasitic effects and is particularly suitable for high-speed VLSI and RF ICs. The design was implemented in commercial sub micron BiCMOS technologies for multi-power-supplies mixed-signal ICs.

An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage (/spl sim/7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (/spl sim//spl Omega/). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (/spl sim/80 V//spl mu/m width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips.