Compact Analytical Model Research Articles

A More Accurate Analytical DC Compact Modeling of Tunneling Field-Effect Transistor for SPICE Simulation

In this work, an analytical DC compact model of tunneling field-effect transistor (TFET) with higher accuracy is presented. Non-local band-to-band tunneling current equation in the device simulation equips density of states (DOS) and Fermi-Dirac distribution of carriers, and the electrical parameters are extracted from the device simulation and fed into the circuit-level simulation. All the equations with the full set of coefficients obtained from the device simulations are have been encoded by Verilog-A and implanted in the HSPICE. Along with the abrupt switching subthreshold and on-state current characteristics, ambipolar current characteristics in the negative gate bias region has been also precisely described in this work. The device and circuit simulation results have demonstrated plausibly good agreement and the developed model will be of great practical use in the digital and analog circuit designs.

A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

This paper presents a compact two-dimensional analytical device model of surface potential, in addition to electric field of triple-material double-gate (TMDG) tunnel FET. The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source. The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage, lateral and vertical electric field. Because the TMDG TFET has a simple compact structure, the surface potential is computationally efficient and, therefore, may be utilized to analyze and characterize the gate-controlled devices. Furthermore, using Kane's model, the current across the drain can be modeled. The graph results achieved from this device model are close to the data collected from the technology computer aided design (TCAD) simulation.

Strain effects on the quantum capacitance of graphene nanoribbon devices

One of the most important characteristics of graphene-based nanodevices is the quantum capacitance (QC) of the channel which plays a dominant role in governing the device performance. Moreover, QC can be utilized to realize various types of high performance sensors and energy storage devices. In the present work, the effect of in-plane uniaxial strain on the QC of GNR-based devices is investigated utilizing a compact analytical model which accounts for several finite-size and edge effects. Carrier density and QC are calculated for the three distinct families of armchair GNRs. The strong modulation of QC by uniaxial strain is related to strain-induced changes in both bandgap and effective mass of GNRs. Our study could be helpful for designing GNR-based nanodevices in the Quantum Capacitance Limit.

Current-voltage analytical model and multiobjective optimization of design of a short channel gate-all-around-junctionless MOSFET

In this paper we investigate the optimized design of a short channel gate-all-around-junctionless (GAAJ) metal-oxidesemiconductor field-effect-transistor (MOSFET), including the source-drain extensions, by means of genetic algorithm solutions applied to a compact current-voltage analytical model. In fact, due to the complex device structure, it seems useful to exploit a metaheuristic-based approach to search the optimal combination of the fundamental geometrical and physical parameters that lead to an improved performance. Through this analysis, different parameter constraints are imposed for the calculation of specific objective functions. In particular, for a fixed gate-drain bias level, the task pursues the maximization of the drain current and cut-off frequency while limiting the short channel (SC) effects. The MOSFET series resistance is also evaluated in the transition region of the Id – Vgs characteristics which appear, however, strongly affected by SC effects. The accuracy of the model is verified by comparison with experimental data reported in literature.

Electronic transport in graphene nanoribbons with correlated line-edge roughness

In this paper, the impact of correlation between two line-edge roughnesses (LERs) on electronic transport in armchair graphene nanoribbons (AGNRs) is investigated, employing an atomistic model based on the non-equilibrium Greens function formalism. For demonstrating the influence of this correlation, crucial transport properties like mean free path and localization lengths corresponding to different sets of roughnesses and geometrical parameters are extracted. The results indicate the substantial role of the degree of cross-correlation in transport characteristics. Besides, for showing its importance in practice, some parameters in an AGNR-based field effect transistor relating to diverse correlations are provided. Additionally, an analytical compact model is developed to formulate conductance as a function of cross-correlation coefficient. The presented results offer novel insights into electronic transport in GNRs casting light on how the correlation of LERs should be regarded as the decisive factor in choosing an experimental approach for fabrication of GNRs.

Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach

PurposeThis study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs.Design/methodology/approachThis paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach.FindingsIt is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement.Originality/valueCompact Analytical models for undoped symmetric double gate MOSFETs.

Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range

This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.

Gallium Nitride FET Model

We have presented an analytical physics-based compact model of GaN power FET, which can accurately describe the I-V characteristics in all operation modes. The model considers the source-drain resistance, different interface trap densities and self-heating effects.

Impact of Interface Trap Charges on the Electrical Characteristics of Back-Gated 2D Negative Capacitance (NC) FET

In this letter, a fully analytical compact drain current model of back-gated two-dimensional (2D) negative capacitance (NC) FET including interface trap charges has been developed by solving Poisson's, drift-diffusion and 1-D Landau-Khalatnikov equations, and it is validated against the experimental data. In addition, the impact of interface trap charges on the electrical characteristics of the back-gated 2D NC-FET is investigated systematically based on the model. It is found that the subthreshold swing (SS) and on-off current ratio ( I on/ I off) are seriously degraded because of the presence of interface traps at 2D channel/oxide interface and 2D NC-FET with a big tf is more immune to the degradation induced by the interface traps. In addition, the underlying physics are elucidated by the capacitance matching of 2D NC-FET.

Compact Modeling of Perpendicular STT-MTJs With Double Reference Layers

This paper shows the steps to set up a simulation framework for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) with double-barrier and two antiparallel reference layers (DMTJs). The approach is based on a Verilog-A analytical compact model that properly takes into account the effect of the DMTJ physical stack on both resistance and statistical switching characteristics. Validation results demonstrate a good agreement of analytical calculations with both numerical simulations and experimental data. To test the functionality of the developed Verilog-A code in hybrid CMOS/STT-MTJ circuit simulations, we have investigated the performance of a non-volatile flip-flop (NVFF) implemented with DMTJs and FinFETs in comparison with its single-barrier MTJ (SMTJ)-based counterpart. The reduced switching current of DMTJs allows reducing the backup time and energy by a factor of 3X and 6.1X, respectively. Such benefits are obtained along with smaller area occupation and better performance in the flip-flop (FF) active operation mode.

Gate-Recessed E-mode p-Channel HFET With High On-Current Based on GaN/AlN 2D Hole Gas

High-performance p-channel transistors are crucial to implementing efficient complementary circuits in wide-bandgap electronics, but progress on such devices has lagged far behind their powerful electron-based counterparts due to the inherent challenges of manipulating holes in wide-gap semiconductors. Building on recent advances in materials growth, this work sets simultaneous records in both on-current (10 mA/mm) and on-off modulation (four orders) for the GaN/AlN wide-bandgap p-FET structure. A compact analytical pFET model is derived, and the results are benchmarked against the various alternatives in the literature, clarifying the heterostructure trade-offs to enable integrated wide-bandgap CMOS for next-generation compact high-power devices.

Analytical Low Frequency NBTI Compact Modeling with H2 Locking and Electron Fast Capture and Emission

Besides reaction-diffusion theory explaining the generation and passivation of interface trap (ΔNIT), hole trapping/de-trapping in preexisting gate insulator traps and transient charge occupancy in ΔNIT are also combined to describe the characteristic of NBTI degradation. However, it is found that H2 locking effect and Electron Fast Capture/Emission play key roles in the NBTI degradation. In this paper, an analytical low frequency AC NBTI compact model has been proposed to accurately predict the shift in threshold voltage. Two fitting parameters (α and FFAST) have been introduced to account for the H2 locking and fast electron capture and emission. The comparison between the proposed model and the experimental data has been carried out, and the results show that our proposed can catch the kinetics of NBTI degradation under low frequency AC stress conditions.

Effect of Temperature on the Performance of Triple-Gate Junctionless Transistors

The device transport parameters (subthreshold slope, low-field mobility, series resistance, and threshold voltage) of n-channel triple-gate junctionless transistors are investigated in the temperature range 298–398 K. The temperature dependence of these parameters is analyzed to clarify the mechanisms responsible for the impact of temperature on the device performance. Based on analytical empirical expressions capturing their temperature dependence, our analytical compact model can predict the transfer and output characteristics at elevated temperatures with good accuracy.

Papertronics: Multigate paper transistor for multifunction applications

The use of disposable recyclable, eco-friendly, sustainable and low-cost devices with multiple functions is becoming a demand in the emerging area of the Internet of Things as a way to decrease the degree of complexity of the electronic circuits required to serve a plethora of applications. Moreover, for low-cost disposable applications, it is relevant the systems to be recyclable. The idea beyond the present study concerns to exploit our imagination with simple questions such as: What happens if it is possible to have a simple and universal device architecture, easy to implement on paper substrates, but capable to provide different multiple functionalities? It would be possible to have a common template for electronic systems on paper that would be then easily customized depending on the final application? The present study answers to these demands by reporting the physics and electronics behavior of a multigate paper transistor where paper is simultaneously the substrate and the dielectric, while a metal-oxide-semiconductor (IGZO) is used as the active channel. Moreover, the same device is able to present logic functionalities simply by varying the amplitude and frequency of the input gate signals. These transistors operate at drain voltages of 1V with low power, exhibiting ION/IOFF>104 and a mobility ≈2cm2V−1s−1, serving the specifications for a broad range of smart disposable low power electronics. To sustain all this, an analytical compact model was developed able to precisely reproduce the response of paper-based dual-gate FETs and provide full understanding of their unique and innovative operational characteristics.

Static and dynamic compact analytical model for junctionless nanowire transistors

This paper presents a compact analytical model for the static and dynamic electrical characteristics of Junctionless Nanowire Transistors. The static drain current model formulation is derived from the 2D solution of the Poisson equation with appropriate boundary conditions and long-channel devices, leading to a continuous effective surface potential that accounts for the conduction in partial depletion and accumulation regimes. The long-channel model is modified to account for short-channel effects by using the coupled solution of 3D Laplace equation with the 2D Poisson equation. The substrate bias influence on the drain current is also included in the model formulation. The charges at the device terminals are differentiated with respect to the applied biases leading to an analytical description of the transconductances and transcapacitances. The proposed model is validated using experimental data at different bias conditions and temperatures, showing very good agreement.

Contactless four-terminal MEMS variable capacitor for capacitive adiabatic logic

This paper reports the design, energy recovery and logical functionality modeling of four-terminal microelectromechanical (MEMS) comb-drive devices for capacitive adiabatic logic (CAL). The proposed electromechanical element consists of the moving mass with two insulated electrodes and two fixed electrodes. The two pairs of fixed and moving electrodes form an input and an output comb-drive capacitive transducer. The voltage across the input port allows us to control the capacitance of the output port. The developed contactless four-terminal design is simulated in Coventor MEMS+ ® software. In order to speed up transient simulation of numerous devices in an electronic Simulation Program with Integrated Circuit Emphasis (SPICE) simulator, the obtained electrical and mechanical characteristics are used to fit our Verilog-A analytical compact model. SPICE simulation results demonstrate CAL logical functionalities using a cascadable power clock scheme, i.e. logic state differentiation and cascadability. We also show that MEMS-based calculation is energy efficient: for example, in a chain of four buffers, 99.1% of the energy transferred to the device is recovered for later use when devices operate at 25 Hz. The non-recoverable energy is mainly dissipated by mechanical damping during the logic state transition from high to low level and can be removed by using retractable power clocks. For this mm-scale device the energy dissipated per operation is of the order of 1 pJ. This is still far from the energy dissipated by a nm-scale field-effect transistor (FET), which is of the order of tens of attojoules. However, for the contactless design constant electric field scaling is possible and the energy dissipation decreases proportionally to the cube of the size. Finally, the limitations of irreversible MEMS-based CAL are discussed.

A new compact analytical model of nanoelectromechanical systems-based capacitive micromachined ultrasonic transducers for pulse echo imaging

A compact analytical model of a capacitive micromachined ultrasonic transducer (CMUT) exhibiting a damped oscillatory output for pulse echo imaging is proposed. The analysis is improved herein by taking into account the acoustic damping coefficient, proportional to the velocity of vibration of the CMUT membrane equation of motion. Solutions for both radial and temporal variables of the modeled equation are obtained. The result is found to be a comprehensively damped oscillation that would enable an enhanced time interval for a pulse echo imaging sensor system. Finite element method modeling of the CMUT was also performed using PZFlex, a finite element analysis-based simulation tool. The results obtained from the analytical model are in good agreement with those from PZFlex.

A New Holistic Model of 2-D Semiconductor FETs

An analytical compact model for 2-D crystal FETs is proposed. It provides an explicit expression for the drain current as a function of the gate and drain voltages considering Fermi–Dirac statistics and drift-diffusion transport. The model is applicable to n-type or p-type symmetric and asymmetric double gate devices as well as single gate transistors. It is validated against experimental results and can be used to explore in a simple but accurate fashion the physics and the performance limits of 2-D crystal FETs.

An Analytical Model of Gate-All-Around Heterojunction Tunneling FET

A compact analytical drain current model considering the inversion layer and source depletion is developed for the gate-all-around (GAA) heterojunction tunneling FET (H-TFET) with staggered-gap alignment. Poisson’s equations are solved to obtain the continuous surface potential profile for the GAA H-TFET first, then the drain current is derived based on Kane’s model by using the tangent line approximation method, and finally, the model is verified by TCAD simulation using GaAs0.5Sb0.5/In0.53Ga0.47As GAA H-TFET and published data. The impacts of bias, gate oxide dielectric constant, and interface fixed charge on the surface potential, electric field, and ${I} _{{\textsf {DS}}}$ – ${V} _{{\textsf {GS}}}$ can be well predicted by the proposed model. The super-linear onset and saturation characteristics of ${I} _{{\textsf {DS}}}$ – ${V} _{{\textsf {DS}}}$ curves are also obtained.

Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes

The operation of static random access memory (SRAM) in the subthreshold region reduces both leakage power and access energy. Subthreshold operation is one of the proficient techniques to accomplish low-power and high performance system on chip. But the challenge, in subthreshold SRAM design, is the SRAM stability. The sensitivity to process variations increases with technology scaling resulting in reduced stability. In this paper, SRAM write stability is analyzed in the subthreshold region. The semi-analytical model of write static noise margin (WSNM) for 6T SRAM (subthreshold region) has been given in this paper. The results obtained from the analytical model are verified through simulations in Cadence using GPDK 45-nm, UMC 65-nm, and UMC 130-nm technology files. The model is based on the subthreshold current equations of the transistor. Further, the write stability of the SRAM is analyzed with the varying supply voltage and the sizing ratios. The process corner analyses is also accomplished to verify the write stability of the SRAM cell using the model at the worst process corners. To the best of the author’s knowledge, this is the first model to analyze the WSNM based on the traditional butterfly static noise margin approach. It has been observed that the model is valid for all of the technology nodes, i.e., at 45 nm, 65 nm, as well as 130 nm. Also the model holds well for 8T and 10T SRAM configurations in addition to 6T SRAM cell.