Common Subexpression Elimination Algorithm Research Articles

Design and Development of Diminution of Multiplier in FIR Sieve Consuming Mutual Sub-Expression Removal Algorithm

The difficulty of Finite-Impulse-Response (FIR) sieve out is ruled with means of that wide variety of adders or subtractors that are consumed toward enforce these co-green multipliers. The Common-Sub-expression-Elimination (CSE) set of rules is founded totally at that Canonical-Signed-Digit (CSD) depiction of clear out co-efficient pro imposing stumpy difficulty FIR sieves. Now, decrease of multiplier inside rectilinear phase FIR sieves is completed through changing this multiplier quantity toward Minimum-Signed-Powers-of-Two (MNSPT) or Canonical-Signed-Digit (CSD) illustration of this multiplier respectively. This multiplier may be executed consuming a sequence of changes and accompaniments or deductions. This CSE algorithm is expended toward discover and dispose of additional commonplace sub-expressions amongst sieve coefficients whichever ends up inside energy and vicinity convertible at the same time as executed inside FIR sieves. This Common-Sub-expression-Elimination (CSE) approach toward be consumed pro this VLSI layout will outcome in condensed multiplier inside Finite-Impulse-Response (FIR) clear out by a trivial quantity of adders and records.

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal

Low-complexity, high-speed and re-configurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of acquired seismic signal in real-time seismic-alert-system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (LOs) and logic depths (LDs) in digital FIR filter. In this brief, a novel matrix grouped CSE (MCSE) algorithm has been proposed which outperforms the existing CSE algorithms in terms of LOs and LDs minimization. Moreover, a new half-unit biased (HUB) based rounding technique is incorporated in the proposed design to reduce the truncation error while maintaining low-complexity and the cut-set retiming technique is employed to reduce the critical-path-delay (CPD). Two hardware efficient FIR filter architectures (I and II) involving the proposed canonical signed digit (CSD) based MCSE algorithm, HUB rounding and cut-set retiming approach have been presented. Further, the architecture II represents a hardware efficient realization of a reconfigurable FIR filter. The hardware implementation of the architectures is performed on both FPGA and ASIC platforms. The hardware implementation of the proposed architecture I yields more than 25%, 49%, 38%, 36% and, 31% reduction in LOs, CPD, effective latency, area-delay-product (ADP) and, power-delay-product (PDP), respectively, over the state-of-the-art CSE based architectures. Whereas the reconfigurable architecture II exhibits nearly 48%, 12% and, 13% reduction in CPD, ADP and, PDP over the counterpart.

EEG Processing Using VHBCSE Based FIR Filter

There is a major role for filter in noise removal. because of simple structure, stationary response and adaptively with embedded microprocessors. The Finite Impulse Response (FIR) filter has many advantages on signal processing . to process the Electroencephalography (EEG) signal the FIR filter is the best suited option. The noise in the EEG signal can reduced by using FIR filter. The hardware complexity of FIR filter is high because of multipliers present in the FIR filter. By reducing the multipliers fast and less area using FIR filter is obtained. This paper present a vertical and horizontal Binary common subexpression elimination (VHBCSE) algorithm based FIR filter to process the EEG signal. The common subexpression elimination (CSE) algorithm eliminate the bit patterns which are often occurring. The proposed FIR filter reduce noise of EEG signal rapidly ,by consuming less power and design only required less area. Xilinx ISE design suite 14.7 is used to simulate the FIR filter in FPGA and the MATLAB environment is to generate the EEG signal.

A novel technique for common sub-expression elimination for digital FIR filters using hit and miss transform

In this paper, a new design technique for hybrid common sub-expression elimination (CSE) algorithm is proposed based on Hit and Miss Transform (HMT). The novelty of proposed hybrid CSE is to exploit the basic concept of HMT for minimizing the common patterns, which is required in CSE, similar to minimization of structuring elements (SEs), performed as logic reduction of SEs through erosion process. This mechanism of logic reduction of HMT is imported as a new design technique in proposed hybrid CSE and has been examined through designing adder efficient multiplier-less finite impulse response (FIR) filters. The design results included in this paper illustrate the significance of proposed algorithm by achieving least number of adders in the realization.

Design of low power multiplierless FIR filter with enhanced adder efficiency using flower pollination optimization

This paper presents an improved design of minimal power multiplierless finite impulse response (FIR) by using flower pollination algorithm (FPA) and newly proposed hybrid common sub-expression elimination (CSE) algorithm. The novel extract of this paper is three fold: first, enhancement of the power performance by reducing the switching activity; second, raising adder efficiency using newly proposed hybrid CSE algorithm; and third, optimizing the frequency response characteristics of filter by controlling ripples in passband and stopband region using FPA in one step. For this purpose, the minima of an objective function is achieved, constructed as sum of integral mean squared error with allowable tolerable limits to control ripples in passband and stopband region, and the dynamic power that has computed through hamming distance (HD) between two successive filter coefficients. In addition to this, the application of recently proposed CSE reduces the amount of adders, and lowers the value of HD. The significance of proposed algorithm is measured on the basis of different performance evaluation parameter such as; stopband attenuation (As), stopband ripple (δs), passband ripple (δp), hamming distance (HD), power and amount of adders respectively.

Radix‐2 r recoding with common subexpression elimination for multiple constant multiplication

In a recent work on multiple constant multiplication (MCM) problems, a fully predictable sub-linear runtime heuristic was introduced, called Radix-2 r MCM. This method shows competitive results in speed, power and area, comparatively with the leading algorithms. In this study, the authors combine Radix-2 r MCM with an exact common subexpression elimination (CSE) algorithm. The resulting algorithm denoted Radix-2 r -CSE allows a substantial reduction in the number of addition/subtraction operations in MCM by maximising the sharing of partial terms after an initial recoding in Radix-2 r MCM. The savings over Radix-2 r MCM ranges from 4.34 to 18.75% (10% on average) when considering a set of 14 benchmark finite impulse response filters of varying complexity.

A Triangular Common Subexpression Elimination Algorithm With Reduced Logic Operators in FIR Filter

Common subexpression elimination (CSE) technique is regarded as one of the popular methods to minimize the number of logic operators (LOs) in digital filter by eliminating the redundant occurrence of bit pattern. To this aim, this brief presents an innovative triangular CSE algorithm that generates FIR filters with reduced number of logic operators when compared to other CSE techniques in the literature. Supremacy of our design strategy has also been established in terms of logic operators and logic depths over a number of state-of-the-art techniques of recent interest. Simulation results have offered a noticeable average LO reduction when compared with other related algorithms. Supremacy of the proposed design has also been substantiated by implementing the filters on Cyclone IV FPGA chip.

Performance of Multiplierless FIR Filter Based on Directed Minimal Spanning Tree: A Comparative Study

This paper presents a novel low complex configuration methodology by deploying a directed minimal spanning tree (DMST) algorithm for designing digital multiplierless finite impulse response filter. This method utilizes the shift inclusive differential coefficient and common sub-expression elimination (CSE) technique to minimize the multiple constant multiplications using steepest decent approach. The attractive feature of this work lays on the detailed comparison of the cost, reconstruction error, pass-band and stop-band error by exploiting various evolutionary techniques such as cuckoo search algorithm, particle swarm optimization, artificial bee intelligence, hybrid swarm optimization and flower pollination algorithm; followed by employing hybrid SID and DMST on these techniques. For this purpose, a mean squared error-based objective function is optimized in the pass-band and stop-band region of the filter. Further, a detailed comparison of hybrid SID and DMST with other existing CSE algorithms is also illustrated. It has been observed that up to 80% reduction in number of adders can be accomplished using the proposed DMST-based approach for multiplierless filter design.

Design and implementation of low complexity circularly symmetric 2D FIR filter architectures

This paper presents a low complexity two dimensional (2D) circular symmetric Finite Impulse Response (FIR) filter design and implementation of architecture. The optimized circular symmetric 2D FIR filter is designed using a modified Park–McClellan transformation method and filter coefficients are quantized using a canonical signed digit (CSD) binary number format. The CSD encoded coefficients are optimized to reduce the number of adder/subtractors using common subexpression elimination (CSE) algorithms. Based on the modified filter coefficients, the two structures fully direct form and hybrid-II form 2D FIR filter architectures are implemented using CSD and CSD with Horizontal CSE and Vertical CSE techniques. The proposed architectures compared with the conventional symmetry 2D filters and state-of-the-art architectures in terms of area, power, and speed.

A new method for designing multiplierless two-channel filterbank using shifted-Chebyshev polynomials

ABSTRACTThis paper presents an efficient design method for a digital multiplierless two-channel filterbank using the shifted-Chebyshev polynomials and common sub-expression elimination (CSE) algorithm for reducing hardware requirements such as adders and multipliers. For designing a two-channel filterbank, the design problem is constructed as minimization of integral mean square error between the desired and designed response of a prototype filter in the passband and stopband. For controlling the performance in passband and stopband, two parameters (KP, and KS) are used, whose optimum values are determined by swam optimization techniques such as differential evolution algorithm, artificial bee colony optimization, particle swarm optimizations, cuckoo search algorithm and hybrid method using a fitness function, constructed by perfect reconstruction condition of a filterbank. The number of polynomials used for approximation depends upon the order of a prototype filter. A new hybrid CSE is proposed for further reduction of hardware requirement. A comparative study of various CSE techniques such as horizontal, vertical and proposed hybrid CSE is also made. Numerical examples illustrate the effectiveness of the proposed algorithm in the reduction of adders with comparisons accomplished using existing methods. It has been found that almost 43% adder gain can be achieved when a filter is designed with N = 32 and wordlength (WL) as 12 using proposed methodology.

An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm

As the only nonlinear operation, masked S-box is the core to resist differential power attack (DPA) for advanced encryption standard (AES) cipher chips. In order to suit for the resource-constrained applications, a compact masked S-box based on composite field is proposed in this paper. Firstly, the architecture of masked S-box is designed with composite field masking method. Secondly, four masked S-boxes based on GF ((2[Formula: see text], which are based on four basis methods with the optimal coefficient and the corresponding optimal root, are implemented and optimized by the delay-aware common subexpression elimination (DACSE) algorithm. Finally, experimental results show that, while maintaining the DPA-resistance performance, our best masked S-box achieves better area performance with the fastest speed compared with the existing works. Therefore, our masked S-box is suitable for resource-constrained applications with fast speed requirements.

A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm

This paper introduces a computationally efficient hardware architecture for reconfigurable multiple constant multiplication block, which functions according to the canonical signed digit (CSD)-based vertical and horizontal common sub-expression elimination (VHCSE) algorithm. In the proposed architecture, the CSD decoded coefficient along with 4-b common sub-expressions (CSs) in the vertical direction and 4- and 8-b CSs in the horizontal direction reduces the required number of full adder cells and the adder depths. This technique helps in reducing area consumption by decreasing the number of coefficient multiplier adders by 59% than that of the binary VHCSE (VHBCSE) algorithm. This technique helps in reducing the average switching activity of the adder blocks used in each coefficient multiplier block by 26.1%, 25.6%, and 21.3%, while compared with those of the 2- and 3-b binary CS elimination (BCSE) and VHBCSE algorithms, respectively. For different orders of filter, the proposed one delivers 57.5% and 61.9% improvement in area-power product (APP) on an average compared with the VHBCSE and mixed integer programming algorithms, respectively. Experimental results of differently specified finite impulse response (FIR) filters ranging from 10 to 100 taps and the coefficients of 8, 12, and 16 b show the improvements of 42.8%, 53.6%, and 37%, respectively, in the average gate count and 51.8%, 43.5%, and 36.7% less propagation delay than those of earlier canonical double-based number representation method. Moreover, in the metric made of APP divided by throughput, the proposed technique experiences 63.7% improvement on an average over that of faithfully rounded truncated multiple constant multiplication/accumulation technique of designing constant multiplier and demonstrates its suitability for implementing efficient reconfigurable FIR filter.

H‐RADIX a new heuristic for a single constant multiplication

In the authors’ previous work on the multiplication by a constant, optimisations have been done on the RADIX-2 r heuristic based on Radix-2 r arithmetic, which is a fully predictable, and a sub-linear-runtime heuristic. This improved version of RADIX-2 r is called RADIX-2 r +. The latter makes the former more competitive in term of average number of additions compared with existing heuristics. In this study, the authors propose a new heuristic for multiplication by a constant, denoted H-RADIX, which combines RADIX-2 r + with a common sub-pattern (Lefevre's CSP) heuristic. It belongs to the category of common subexpression elimination algorithm. Results of the designed hybrid algorithm (H-RADIX), namely, the average number of additions and the smallest value that requires q adders, are compared with the standard canonical signed digit (CSD) representation, RADIX-2 r +, and Lefevre's CSP algorithms. The results highlight the efficiency of the designed heuristic, up to N-bits = 64. H-RADIX uses 37.496, 5.015 and 3.082% less additions than CSD, RADIX-2 r +, and Lefevre's CSP, respectively.

A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction

This paper makes a paradigm shift in the assumed notion of common subexpressions for complexity reduction of multiple constant multiplications implementation. Our proposed unified adder/subtractor (UAS)-based common subexpression elimination (CSE) algorithm is inspired by the recent advancement in complex arithmetic component mapping for datapath synthesis of digital systems. A dedicated UAS operator is designed at gate level to achieve arithmetic reduction for concurrent computation of the sum and difference of two input signals. To maximize computation reuse, dual subexpression is defined to enable a UAS to be shared by the otherwise incompatible odd and even common subexpressions. The three different types of common subexpression are uniquely encoded by a quadruple in the proposed data structure. Constant coefficients are represented by signed digits in Cartesian coordinate system from which nonoverlapping pairs of nonzero digits are parsed for dual, even, and odd subexpressions to maximize the reuse of all three types of arithmetic resources. The effectiveness of our proposed UAS-based CSE in overcoming the complexity reduction bottleneck are demonstrated by comparing the synthesis results obtained from six benchmark finite impulse response filters, an electroencephalogram filter bank, fast Fourier transform, and discrete cosine transform multipliers designed by ten algorithms. The results show a noteworthy 27.2% reduction in area-time complexity of our method over the baseline canonical signed digit implementation. Our solutions are also more power efficient, with average power saving of 12.0% over those designed by other algorithms in comparison.

A VLSI Architecture of Root Raised Cosine Filter Using Efficient Algorithm

This paper describe about a reduction of area and power using Vertical and Horizontal Common Sub-Expression Elimination Algorithm in root raised cosine filter. The common sub-expression elimination algorithm is commonly used to reduce the number of adders present the given multiplier architecture is done by reducing MPIS (Multiplications per Input Samples) and APIS (Additions per Input Samples). In the 2bit and 3-bit BCSE algorithms, shift and add method was proposed. Those provide less area than the normal multiplier. Hence algorithm is proposed to further reduce the area utilization, power consumption .Area is utilized by reducing the number of gates in the architecture. This algorithm used for implementing higher adder filters with very few adders and few stages. The proposed algorithm is used to multiply both the signed and unsigned constant multiplication. Here the adjacent co-efficient are grouped by 2bit, 4bit and 8bit grouping as per the horizontal and vertical common sub-expressions. The Shift and add method is used to reduce the number of adders. Similarly multiplexers are used for switching activity to reduce the adders and multiplication stages. These operations are applied to the RRC FIR filter with the different standards. The whole work is done in Quartus II 9.2 web edition, cyclone III

Enhanced MixColumn Design for AES Encryption

The main aim of the current research work is to reduce the complexity path of AES (Advanced Encryption Standard) Encryption. Architecture of MixColumn transformation has been optimized in this research work. Traditional methods of MixColumn transformation methods has been realized and re-designed by reducing the redundant logical functions. Verilog Hardware Description Language (Verilog HDL) has been used to design the optimized MixColumn transformation of AES Encryption. Further optimized MixColumn design has been incorporated into AES Encryption with appropriate input points. Common Sub-expression Elimination (CSE) algorithm is used in developed AES Encryption algorithm. Proposed optimized MixColumn design offers 10.93% improvements in hardware slices, 13.6% improvements in LUTs and 1.19% improvements in delay consumption than traditional MixColumn design. Further proposed optimized MixColumn design has been incorporated into AES Encryption design. Further, proposed optimized MixColumn based AES Encryption design offers 4.75% improvements in silicon area, 4.56% reduction in power consumption than traditional MixColumn based AES Encryption. In future, proposed optimized MixColumn design will be useful in space and terrestrial applications for exhibiting secure transmissions.

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis.

LOW COMPLEXITY DIGIT SERIAL FIR FILTER BY MULTIPLE CONSTANT MULTIPLICATION ALGORITHMS

Serial input data is multiplied with constant pair to produce constant multiplication called Multiple Constant Multiplications (MCM). In order to reduce number of shifting, an addition/subtraction operation, Graph Based (GB) algorithm is taken as a proposed algorithm to construct multiplier for transposed form of digit serial FIR (Finite Impulse Response) filter design 4-tap digit serial FIR filter with digit size d=2,4,8. To analyze low complexity Digit based recoding algorithm and CSE (Common Subexpression Elimination) algorithm simulation compared with GB algorithm based on the performance of area utilization and delay report in Xilinx ise design suite12.1software. Finally this FIR filter is implemented in FPGA spartan3 hardware for real time implementation.

An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform

An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform

A Common Subexpression Elimination Tree Algorithm

A common subexpression elimination algorithm is proposed to minimize the complexity of the multiple constant multiplication operation. The coefficients (constants) of the multiple constant multiplication are represented using the binary signed digit number system. The binary signed digit representations of each coefficient are enumerated using the representation tree. The algorithm traverses the tree to calculate the possible subexpressions at each node. Each subexpression is used to find a possible decomposition for the coefficient to be encoded. A complexity formula is proposed to compare the decompositions. The algorithm is designed to prune the tree when it finds a decomposition with minimum complexity. This reduces the search space while minimizing the hardware complexity. Results show that the algorithm has better performance than other published algorithms including linear programming optimization methods. The algorithm outperforms the subexpression sharing method in that uses only the canonical signed-digit representations.