Abstract
This paper makes a paradigm shift in the assumed notion of common subexpressions for complexity reduction of multiple constant multiplications implementation. Our proposed unified adder/subtractor (UAS)-based common subexpression elimination (CSE) algorithm is inspired by the recent advancement in complex arithmetic component mapping for datapath synthesis of digital systems. A dedicated UAS operator is designed at gate level to achieve arithmetic reduction for concurrent computation of the sum and difference of two input signals. To maximize computation reuse, dual subexpression is defined to enable a UAS to be shared by the otherwise incompatible odd and even common subexpressions. The three different types of common subexpression are uniquely encoded by a quadruple in the proposed data structure. Constant coefficients are represented by signed digits in Cartesian coordinate system from which nonoverlapping pairs of nonzero digits are parsed for dual, even, and odd subexpressions to maximize the reuse of all three types of arithmetic resources. The effectiveness of our proposed UAS-based CSE in overcoming the complexity reduction bottleneck are demonstrated by comparing the synthesis results obtained from six benchmark finite impulse response filters, an electroencephalogram filter bank, fast Fourier transform, and discrete cosine transform multipliers designed by ten algorithms. The results show a noteworthy 27.2% reduction in area-time complexity of our method over the baseline canonical signed digit implementation. Our solutions are also more power efficient, with average power saving of 12.0% over those designed by other algorithms in comparison.
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More From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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