Common Subexpression Research Articles

Hardware‐efficient tree expansion for MIMO symbol detection

A simple yet effective method is proposed to reduce the hardware complexity of tree expansion in multiple-input multiple-output (MIMO) symbol detection. Tree-expansion equations are transformed in the proposed method so as to maximise common subexpressions that can be shared. The proposed method reduces the number of operators significantly, especially multipliers which are costly, without any degradation of bit error rate.

High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier

In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.

Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes

In this work, we derive three novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field GF(((2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). The best construction is selected after a sequence of algorithmic and architectural optimization processes. Furthermore, for each composite field constructions, there exists eight possible isomorphic mappings. Therefore, after the exploitation of a new common subexpression elimination algorithm, the isomorphic mapping that results in the minimal implementation area cost is chosen. High throughput hardware implementations of our proposed CFA AES S-boxes are reported towards the end of this paper. Through the exploitation of both algebraic normal form and seven stages fine-grained pipelining, our best case achieves a throughput 3.49 Gbps on a Cyclone II EP2C5T144C6 field-programmable gate array.

VLSI Architecture for 8-Point AI-based Arai DCT having Low Area-Time Complexity and Power at Improved Accuracy

A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, leading to the proposed novel architecture based on a new final reconstruction step (FRS) having lower complexity and higher accuracy compared to the state-of-the-art. This FRS is based on an optimization derived from expansion factors that leads to small integer constant-coefficient multiplications, which are realized with common sub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well as the proposed architectures for two expansion factors α† = 4.5958 and α′ = 167.2309 are implemented. The proposed circuits show 150% and 300% improvements in the number of DCT coefficients having error ≤ 0:1% compared to [1]. The three designs were realized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm CMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm CMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputs show potential real-time operation at 2.083 GHz clock frequency leading to a combined throughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs show a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA realizations. An 11% reduction in area is observed for the ASIC design for α† = 4.5958 for an 8% reduction in total power (PT ). Our second ASIC design having α′ = 167.2309 shows marginal improvements in area and power compared to our reference design but at significantly better accuracy.

Optimization Algorithms for the Multiplierless Realization of Linear Transforms

This article addresses the problem of finding the fewest numbers of addition and subtraction operations in the multiplication of a constant matrix with an input vector---a fundamental operation in many linear digital signal processing transforms. We first introduce an exact common subexpression elimination (CSE) algorithm that formalizes the minimization of the number of operations as a 0-1 integer linear programming problem. Since there are still instances that the proposed exact algorithm cannot handle due to the NP-completeness of the problem, we also introduce a CSE heuristic algorithm that iteratively finds the most common 2-term subexpressions with the minimum conflicts among the expressions. Furthermore, since the main drawback of CSE algorithms is their dependency on a particular number representation, we propose a hybrid algorithm that initially finds promising realizations of linear transforms using a numerical difference method, and then applies the proposed CSE algorithm to utilize the common subexpressions iteratively. The experimental results on a comprehensive set of instances indicate that the proposed approximate algorithms find competitive results with those of the exact CSE algorithm and obtain better solutions than the prominent, previously proposed, heuristics. It is also observed that our solutions yield significant area reductions in the design of linear transforms after circuit synthesis, compared to direct realizations of linear transforms.

Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT‐Based Image Compression

The canonical signed digit (CSD) representation of constant coefficients is a unique signed data representation containing the fewest number of nonzero bits. Consequently, for constant multipliers, the number of additions and subtractions is minimized by CSD representation of constant coefficients. This technique is mainly used for finite impulse response (FIR) filter by reducing the number of partial products. In this paper, we use CSD with a novel common subexpression elimination (CSE) scheme on the optimal Loeffler algorithm for the computation of discrete cosine transform (DCT). To meet the challenges of low‐power and high‐speed processing, we present an optimized image compression scheme based on two‐dimensional DCT. Finally, a novel and a simple reconfigurable quantization method combined with DCT computation is presented to effectively save the computational complexity. We present here a new DCT architecture based on the proposed technique. From the experimental results obtained from the FPGA prototype we find that the proposed design has several advantages in terms of power reduction, speed performance, and saving of silicon area along with PSNR improvement over the existing designs as well as theXilinx core.

Effective Utilization of Tensor Symmetry in Operation Optimization of Tensor Contraction Expressions

The optimization of tensor expressions with hundreds of terms is required for the development of accurate quantum chemistry models such as the coupled cluster method. In this paper, we address the effective exploitation of symmetry properties of tensors in performing algebraic transformations for minimizing operation count of tensor expressions. We develop rules to detect symmetries in intermediate tensors, cost models for tensor contractions with symmetries, and a canonical representation to facilitate effective common subexpression elimination. We demonstrate significant improvements to the operation counts for the coupled cluster method when compared to several state-of-the-art im-plementations. Furthermore, we show that tensor expressions optimized for a few input parameter combinations can be used to achieve operation counts within 3% of the optimal, for the entire parameter space of interest.

An Area-Efficient 4-Stream FIR Interpolation/Decimation for IEEE 802.11n WLAN

This paper presents an area-efficient 4- stream finite impulse response (FIR) interpolation/decimation for IEEE 802.11n wireless local area network (WLAN). Novelty of the presented design is threefold. First, a multi-path pipelined polyphase structure is proposed to deal with multiple data streams, thereby four simultaneous data streams can be supported in the design with minimal hardware complexity. Second, a hybrid common subexpression elimination (HCSE) method that using signed binary representation of coefficients is applied to the implementation of subfilters. The multiplications in each subfilter are efficiently implemented using a few hardwired shifts, adders, and subtracters. And last, the interpolating mode and decimating mode of the design are configurable. That help to improve system level hardware utilization efficiency since WLAN is a time division duplex system. Under 0.13 μm 1.2 V 1P6M CMOS technology, the cell area and power consumption of the presented interpolation/decimation are 0.22 mm2 and 10.08 mW respectively. The error vector magnitude (EVM) performance of an 802.11n baseband prototype which adopts the presented design is measured ?42.2 dB.

Composite field GF(((2 2 ) 2 ) 2 ) Advanced Encryption Standard (AES) S-box with algebraic normal form representation in the subfield inversion

In this study, the authors categorise all of the feasible constructions for the composite Galois field GF(((2 2 ) 2 ) 2 ) Advanced Encryption Standard (AES) S-box into four main architectures by their field representations and their algebraic properties. For each of the categories, a new optimisation scheme which exploits algebraic normal form representation followed by a sub-structure sharing optimisation is presented. This is performed by converting the subfield GF((2 2 ) 2 ) inversion into several logical expressions, which will be in turn reduced using a common sub-expression elimination algorithm. The authors show that this technique can effectively reduce the total area gate count as well as the critical path gate count in composite field AES S-boxes. The resulting architecture that achieves maximum reduction in both total area coverage and critical path gate count is found and reported. The hardware implementations of the authors proposed AES S-boxes, along with their performance and cost are presented and discussed.

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a non-canonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

Implementing Explicit and Finding Implicit Sharing in Embedded DSLs

Aliasing, or sharing, is prominent in many domains, denoting that two differently-named objects are in fact identical: a change in one object (memory cell, circuit terminal, disk block) is instantly reflected in the other. Languages for modelling such domains should let the programmer explicitly define the sharing among objects or expressions. A DSL compiler may find other identical expressions and share them, implicitly. Such common subexpression elimination is crucial to the efficient implementation of DSLs. Sharing is tricky in embedded DSL, since host aliasing may correspond to copying of the underlying objects rather than their sharing. This tutorial summarizes discussions of implementing sharing in Haskell DSLs for automotive embedded systems and hardware description languages. The technique has since been used in a Haskell SAT solver and the DSL for music synthesis. We demonstrate the embedding in pure Haskell of a simple DSL with a language form for explicit sharing. The DSL also has implicit sharing, implemented via hash-consing. Explicit sharing greatly speeds up hash-consing. The seemingly imperative nature of hash-consing is hidden beneath a simple combinator language. The overall implementation remains pure functional and easy to reason about.

2-큐브 몫 행렬을 이용한 공통식 산출

This paper presents a new Boolean extraction technique for logic synthesis. This method first calculates divisor/2-cube quotients, 2-cube quotient pairs, and 2-cube quotient matrices. Then we find candidates, which can be common sub-expressions, from 2-cube quotients and matrices. Next, candidate intersection provides the common sub-expressions for several logic expressions. Experimental results show the improvements in literal counts over the previous methods.

Adaptive optimization for multiple continuous queries

Because it operates under a strict time constraint, query processing for data streams should be continuous and rapid. To guarantee this constraint, most previous researches optimize the evaluation order of multiple join operations in a set of continuous queries using a greedy optimization strategy so that the order is re-optimized dynamically in run-time due to the time-varying characteristics of data streams. However, this method often results in a sub-optimal plan because the greedy strategy traces only the first promising plan. This paper proposes a new multiple query optimization approach, Adaptive Sharing-based Extended Greedy Optimization Approach ( A-SEGO), that traces multiple promising partial plans simultaneously. A-SEGO presents a novel method for sharing the results of common sub-expressions in a set of queries cost-effectively. The number of partial plans can be flexibly controlled according to the query processing workload. In addition, to avoid invoking the optimization process too frequently, optimization is performed only when the current execution plan is relatively no longer efficient. A series of experiments are comparatively analyzed to evaluate the performance of the proposed method in various stream environments.

Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization

To achieve a high-throughput decoder, massive-parallel computations are normally applied to the Chien search, but the parallel realization increases the hardware complexity significantly. To reduce the hardware complexity of the parallel Chien search, this brief proposes a 2-D optimization method. In contrast to the previous 1-D optimizations, the proposed method maximizes the sharing of common subexpressions in both the row and column directions. All the partial products needed in the parallel structure are represented in a single matrix, and the finite-field adders are completely eliminated in effect. Simulation results show that the proposed 2-D optimization leads to a significant reduction of the hardware complexity. For the (8191, 7684, 39) BCH code, the count of xor gates in the parallel Chien search is reduced by 92% and 22%, compared to the straightforward and strength-reduced structures, respectively.

커널-커널 쌍을 이용한 공통 논리식 산출

본 논문에서는 논리합성을 위한 공통식 추출 방법을 새롭게 제안한다. 제안하는 방법은 주어진 각 논리식들에서 커널/커널 쌍들과 코커널/커널 쌍을 추출한다. 커널/커널 쌍은 주어진 논리식을 부울 나눗셈에 의해 제수, 몫, 나머지로 논리식을 다시 표현하게 된다. 다음, 여러 논리식에서 산출된 제수, 몫들에서 공통식을 추출하는 커널 교집합에 의해 공통식을 구하는 방법을 제안한다. 실험 결과 기존의 공통식 산출 결과들과 비교했을 때 제안한 방법은 리터럴 개수를 줄일 수 있었다. This paper presents a new Boolean extraction technique for logic synthesis. This method extracts kernel-kernel pairs as well as cokernel-kernel pairs. The given logic expressions can be translated into Boolean divisors and quotients with kernel-kernel pairs. Next, kernel intersection method provides the common sub-expressions for several logic expressions. Experimental results show the improvement in literal count over previous other extraction methods.

컴파일러에 의한 C레벨 에러 체크

We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

Common Sub-expression Sharing을 사용한 저면적 FFT 프로세서 구조

이 논문에서는 저면적 256-point FFT 구조를 제안한다. 저면적 구현을 위하여 CSD(Canonic Signed Digit) 곱셈기 방식을 채택하여 구현하였다. CSD 곱셈기 방식을 효율적으로 적용하기 위해서는 곱셈연산의 가지 수가 적어야 하는데, 여러 알고리즘을 조사한 결과 Radix-<TEX>$4^2$</TEX> 알고리즘이 곱셈연산의 가지 수가 적음을 발견하였다. 따라서 제안 구조는 Radix-<TEX>$4^2$</TEX> DIF 알고리즘과 CSD 곱셈기 방식을 사용하였다. 즉 Radix-<TEX>$4^2$</TEX> 알고리즘을 사용하여 4개의 스테이지에서 사용되는 곱셈연산의 가지 수를 최소화한 후에 각각의 곱셈연산 블록은 CSD 곱셈기를 사용하여 구현하였다. CSD 곱셈기 구현에서 공통패턴을 공유하여 덧셈기의 수를 줄일 수 있는 CSS(Common Sub-expression Sharing) 기술을 사용하여 구현면적을 더욱 감소시켰다. 제안된 FFT 구조를 Verilog-HDL 코딩 후 합성하여 구현한 결과, Radix-4를 사용한 구조와 비교하여 복소 곱셈기 부분의 29.9%의 cell area 감소를 보였고 전체적인 256-point FFT 구조에 대한 비교에서는 12.54% cell area 감소를 보였다. In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-<TEX>$4^2$</TEX> algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

WLAN용 저면적 심볼 타이밍 옵셋 동기화기 구조

이 논문에서는 OFDM Modem의 심볼 타이밍 옵셋 동기화 블록에 대한 저면적 구조를 제안한다. 심볼 타이밍 동기화 블록에서의 곱셈연산을 디지털 필터 구조의 개념을 도입하여 저면적 구조를 유도하였다. 즉 곱셈연산을 CSD(Canonic Signed Digit) 방식과 CSS(Common Sub-expression Sharing) 방식의 덧셈기를 사용한 구조를 제안하였다. 제안 구조에 대한 Verilog-HDL 코딩과 합성을 통하여 <TEX>$0.264mm^2$</TEX>로 구현하였으며, 이는 기존 구조의 <TEX>$0.723mm^2$</TEX>와 비교하여 63.54%의 구현 면적 감소를 달성하였다. 따라서 제안된 구조는 OFDM 시스템의 심볼 타이밍 동기화기에 효율적으로 사용 될 수 있을 것이다. In this paper, a low-area symbol timing offset synchronization structure for WLAN Modem is proposed. Using CSD(Canonic Signed Digit) coefficients and CSS(Common Sub-expression Sharing) technique for the filter implementation, efficient structure for multiplication block can be obtained. Function simulation for proposed structure is done by using the preamble with timing offset. Through Verilog-HDL coding and synthesis, it is shown that the proposed symbol timing offset synchronization structure can be implemented with low-area semiconductor.

Design of High-Order Extrapolated Impulse Response FIR Filters with Signed Powers-of-Two Coefficients

Expensive multiplication operations can be replaced by simpler additions and hardwired shifters so as to reduce power consumption and area size, if the coefficients of a digital filter are signed power-of-two (SPT). As a consequence, FIR digital filters with SPT coefficients have been widely studied in the last three decades. However, most approaches for the design of FIR filters with SPT coefficients focus on filters with length less than 100. These approaches are not suitable for the design of high-order filters because they require excessive computation time. In this paper, an approach for the design of high-order filters with SPT coefficients is proposed. It is a two-step approach. Firstly, the design of an extrapolated impulse response (EIR) filter is formulated as a standard second-order cone programming (SOCP) problem with an additional coefficient sensitivity constraint for optimizing its finite word-length effect. Secondly, the obtained continuous coefficients are quantized into SPT coefficients by recasting the filter-design problem into a weighted least squares (WLS) sequential quadratic programming relaxation (SQPR) problem. To further reduce implementation complexity, a graph-based common subexpression elimination (CSE) algorithm is utilized to extract common subexpressions between SPT coefficients. Simulation results show that the proposed method can effectively and efficiently design high-order SPT filters, including Hilbert transformers and half-band filters with SPT coefficients. Experiment results indicate that 0.81N∼0.29N adders are required for 18-bit N-order FIR filters (N=335∼3261) to meet the given magnitude response specifications.

Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters

The coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tradeoff between implementation costs and quantization errors is essential for designing optimal FIR filters. This paper presents our complexity-aware quantization framework of FIR filters, which allows the explicit tradeoffs between the hardware complexity and quantization error to facilitate FIR filter design exploration. A new common subexpression sharing method and systematic bit-serialization are also proposed for lightweight VLSI implementations. In our experiments, the proposed framework saves 49%~ 51% additions of the filters with 2's complement coefficients and 10%~ 20% of those with conventional signed-digit representations for comparable quantization errors. Moreover, the bit-serialization can reduce 33%~ 35% silicon area for less timing-critical applications.