Common Path Pessimism Removal Research Articles

A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs

Common path pessimism removal (CPPR) is imperative for eliminating redundant pessimism during static timing analysis (STA). However, turning on CPPR can significantly increase the analysis runtime by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100\times $ </tex-math></inline-formula> in large designs. Recent years have seen much research on improving the algorithmic efficiencies of CPPR, but most are architecturally constrained by either the speed–accuracy tradeoff or design-specific pruning heuristics. In this article, we introduce a novel CPPR algorithm that is provably good and practically efficient. We have evaluated our algorithm on large industrial designs and demonstrated promising performance over the current state of the art. As an example, our algorithm outperforms the baseline by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$36\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$135\times $ </tex-math></inline-formula> faster when generating the top-10K post-CPPR critical paths on a million-gate design. At the extreme, our algorithm with one core is even <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times $ </tex-math></inline-formula> faster than the baseline with eight cores. Our algorithm also outperforms the commercial STA engine PrimeTime up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$26.99\times $ </tex-math></inline-formula> faster. By exploiting parallelism within the circuit graph, we can reduce the memory consumption of our algorithm by 30%, with only 3% runtime increase.

Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates

Superconductive single-flux-quantum (SFQ) circuits operate with very high clock frequency and its timing design is a difficult task. In circuit design, static timing analysis (STA) is a key process for evaluating and verifying the timing of a circuit design. Conventional timing analysis for SFQ circuits focuses on circuits composed of clocked gates and splitters; however, practical SFQ circuits are composed of various gates, i.e., not only clocked gates but also other gates, such as nondestructive read-out, confluence buffer, and clockless logic gates. In this article, to express timing constraints of both clocked gate cells and other cells, we define timing requirements of cells as minimum and maximum acceptable intervals on ordered pairs of input pins. Via these, we express timing constraints of cells in an SFQ circuit design. Furthermore, to eliminate unnecessary pessimism during variation-aware timing analysis, we propose a method of common path pessimism removal (CPPR) for SFQ circuits composed of various cells. We implement an STA tool using the defined timing constraints and the CPPR method. The experimental results show that our STA tool verifies the timing of SFQ circuits composed of various cells.

QSTA: A Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single-flux-quantum (SFQ) technology is a beyond-complementary metal–oxide–semiconductor (CMOS) technology, promising ultrahigh processing speed and low power consumption. A timing analysis tool for SFQ circuits should check circuit timing behavior, including working frequencies and hold time violations to determine the circuit performance. Unlike CMOS gates, generic SFQ gates are clocked gates, which produce their output pulses in response to a clock pulse and have a fan-out capability of one. An SFQ splitter, a special clockless gate that has a fan-out capability of two, is used to address the fan-out limitation. This gate is also utilized in the clock tree, which distributes clock pulses to various SFQ gates. The delay of a clock path in a clock tree is determined by the wire delays of connection nets and gate delays of splitters. However, the splitter delays in a clock path are significantly affected by process variations, resulting in a challenging skew problem. Furthermore, existing timing analysis tools of SFQ circuits are developed based on the timing definitions, rules, and constraints from CMOS technology with very few modifications. This article demonstrates the incompleteness of the existing SFQ technology timing definitions. Precisely, it presents a novel static timing analysis (STA) tool, qSTA, which checks the timing behavior of SFQ circuits based on revised definitions of the setup time and hold times. qSTA encompasses the common path pessimism removal technique, which removes the delays of the shared path segments between two clock paths to achieve a better approximation of real skew values. qSTA takes only 5.33 s to check the timing behavior of a 16-bit integer divider with 36 732 gates and 55 939 nets.

UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR

The recent TAU computer-aided design (CAD) contest has aimed to seek novel ideas for accurate and fast common path pessimism removal (CPPR). Unnecessary pessimism forces the static timing analysis tool to report worse violation than the true timing properties owned by physical circuits, thereby misleading signoff timing into a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper UI-Timer 1.0, a powerful CPPR algorithm which achieves high accuracy and ultrafast runtime. Unlike existing approaches which are dominated by explicit path search, UI-Timer 1.0 proves that by implicit path representation the amount of search effort can be significantly reduced. Our timer is superior in both space and time saving, from which memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 CAD contest have justified that UI-Timer 1.0 achieved the best result in terms of accuracy and runtime over existing CPPR algorithms.