Common Mode Voltage Variations Research Articles

Low Voltage Differential Input Stage With Improved CMRR and True Rail-to-Rail Common Mode Input Range

A scheme for low voltage rail-to-rail operation with improved common mode rejection ratio is introduced. It can operate with single supply voltages close to a transistor's threshold voltage and it is very compact and power efficient. It is based on a differential amplifier with floating gate input transistors featuring dynamical adjustment of a floating gate biasing voltage. This reduces significantly common mode voltage variations at the input terminals of the differential pair. The implementation of single ended two stage class AB operational amplifiers based on this scheme is discussed. Experimental results of a test chip in 0.5 mum CMOS technology that validates the proposed scheme are presented.

A 40-MHz Double Differential-Pair CMOS OTA With $-{\hbox{60-dB}}$ IM3

A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability and thus reduces distortion caused b y common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about third-order inter-modulation (IM3) distortion for up to 0.9 at 40 MHz. This OTA was fabricated by the TSMC 180-nm deep n-well CMOS process. It occupies a small area of 15.1 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption is 9.5 mW under a 1.5-V supply voltage.

Three-level inverter scheme with reduced power device count for an induction motor drive with common-mode voltage elimination

A three-level inverter scheme with common-mode voltage elimination and reduced power device count for dual inverter-fed open-end winding induction motor is proposed. The open-end winding induction motor is fed by two three-level inverters, formed by cascading two two-level inverters, from both sides. These two three-level inverters share the top inverter, thereby reducing the power device count. The switching states with zero common-mode voltage variation are selected for pulse-width modulated switching so that there is no alternating common-mode voltage in the pole voltages and phase voltages. Only two DC links, with half the ratings of a conventional three-level neutral point clamped inverter, are used for the proposed scheme.

Twelve-Sided Polygonal Voltage Space Vector Based Multilevel Inverter for an Induction Motor Drive With Common-Mode Voltage Elimination

In this paper, a 12-sided polygonal voltage space vector generation with common-mode voltage elimination (CME) is proposed for an induction motor drive. An open-end winding configuration is used for the motor. The proposed multilevel structure is achieved by cascading only the conventional two-level inverters with asymmetrical dc link voltages. By appropriately selecting the voltage vectors with identical common-mode voltage from the opposite ends, a pulsewidth modulation (PWM) strategy with zero common-mode voltage variation can be achieved for the entire modulation range with a common dc link requirement for both the inverter systems. Along with the CME, the proposed 12-sided polygonal space vector based multilevel inverter structure has increased modulation range with the absence of 5th, 7th, 17th, 19th, etc., harmonics up to 12-step operation. The bandwidth problems associated with conventional hexagonal voltage space vector structure current controllers due to the presence of 5th and 7th harmonics in the overmodulation region are absent in the present 12-sided structure. So a simple PWM voltage control with linear voltage control up to 12-step operation is possible from the present 12-sided scheme with less current control complexity.

Active Common Mode Current Reduction in Multiinverter Systems

The paper deals with the common mode current issue in a multidrive system. Common mode currents are caused by steep variations of the common mode voltage, strictly related to the sequence of the inverter states during the voltage pulsewidth modulation. An inexpensive technique that allows compensation of the common mode voltage variation in multidrive systems composed of two or more inverters is proposed in order to eliminate the common mode currents. The common mode current paths and generation mechanisms are reviewed and the influence of the inverter state sequence on the common mode voltage and currents is pointed out. Based on such considerations, a new digital PWM modulation strategy is introduced to compensate the common mode voltage variations generated in a two PWM inverter system.

Reduction of Conducted Electromagnetic Emissions in Multi-Inverter Drive Systems

Conducted emissions are caused by circulation of high frequency common mode currents generated by steep variations of the common mode voltage. In this paper, an inexpensive technique is presented that allows to noticeably reduce conducted electromagnetic emissions of multi-inverter drive systems by compensating common mode voltage variations.