Common Mode Rejection Ratio Research Articles

A Wideband Tangential Electric Probe Based on Common Mode Absorbing

A new tangential electric field probe covering a wide frequency band (1.4 GHz to 7.0 GHz) based on common mode absorbing is presented in this article. The self-resonance of a traditional electric field probe incorporating reflective balun is firstly characterized based on the principle of transverse resonance, which is the major barrier for achieving wideband. In order to annihilate the self-resonance for a wider working band, an absorbing-type balun is therefore proposed and integrated into the tangential electric field probe. The common mode rejection ratio of the new probe is greatly elevated, compared with the conventional ones. A prototype of the probe is fabricated and measured for different electromagnetic interference problems. The results demonstrate excellent performances in terms of the sensitivity, suppression of unwanted fields coupling and the spatial resolution over the wide working band.

Design and Validation of a Low-Cost Mobile EEG-Based Brain-Computer Interface.

Objective: We designed and validated a wireless, low-cost, easy-to-use, mobile, dry-electrode headset for scalp electroencephalography (EEG) recordings for closed-loop brain-computer (BCI) interface and internet-of-things (IoT) applications. Approach: The EEG-based BCI headset was designed from commercial off-the-shelf (COTS) components using a multi-pronged approach that balanced interoperability, cost, portability, usability, form factor, reliability, and closed-loop operation. Main Results: The adjustable headset was designed to accommodate 90% of the population. A patent-pending self-positioning dry electrode bracket allowed for vertical self-positioning while parting the user's hair to ensure contact of the electrode with the scalp. In the current prototype, five EEG electrodes were incorporated in the electrode bracket spanning the sensorimotor cortices bilaterally, and three skin sensors were included to measure eye movement and blinks. An inertial measurement unit (IMU) provides monitoring of head movements. The EEG amplifier operates with 24-bit resolution up to 500 Hz sampling frequency and can communicate with other devices using 802.11 b/g/n WiFi. It has high signal-to-noise ratio (SNR) and common-mode rejection ratio (CMRR) (121 dB and 110 dB, respectively) and low input noise. In closed-loop BCI mode, the system can operate at 40 Hz, including real-time adaptive noise cancellation and 512 MB of processor memory. It supports LabVIEW as a backend coding language and JavaScript (JS), Cascading Style Sheets (CSS), and HyperText Markup Language (HTML) as front-end coding languages and includes training and optimization of support vector machine (SVM) neural classifiers. Extensive bench testing supports the technical specifications and human-subject pilot testing of a closed-loop BCI application to support upper-limb rehabilitation and provides proof-of-concept validation for the device's use at both the clinic and at home. Significance: The usability, interoperability, portability, reliability, and programmability of the proposed wireless closed-loop BCI system provides a low-cost solution for BCI and neurorehabilitation research and IoT applications.

Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications

This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.

A Wireless, High-Quality, Soft and Portable Wrist-Worn System for sEMG Signal Detection.

The study of wearable systems based on surface electromyography (sEMG) signals has attracted widespread attention and plays an important role in human-computer interaction, physiological state monitoring, and other fields. Traditional sEMG signal acquisition systems are primarily targeted at body parts that are not in line with daily wearing habits, such as the arms, legs, and face. In addition, some systems rely on wired connections, which impacts their flexibility and user-friendliness. This paper presents a novel wrist-worn system with four sEMG acquisition channels and a high common-mode rejection ratio (CMRR) greater than 120 dB. The circuit has an overall gain of 2492 V/V and a bandwidth of 15~500 Hz. It is fabricated using flexible circuit technologies and is encapsulated in a soft skin-friendly silicone gel. The system acquires sEMG signals at a sampling rate of over 2000 Hz with a 16-bit resolution and transmits data to a smart device via low-power Bluetooth. Muscle fatigue detection and four-class gesture recognition experiments (accuracy greater than 95%) were conducted to validate its practicality. The system has potential applications in natural and intuitive human-computer interaction and physiological state monitoring.

A 0.8-Volt 29.52-μW Current Mirror-Based OTA Design for Biomedical Applications

An operational trans-conductance amplifier (OTA) is a fundamental component of electronic appliances. This paper introduces a novel design of OTA for minimal power, low voltage applications. The proposed OTA comprises an ultra low power current mirror design with enhanced bandwidth. The proposed OTA circuit is operated at 0.8[Formula: see text]V, contributing input noise of 26.33[Formula: see text]nV/(Hz)[Formula: see text] with a power of [Formula: see text]W. The additional parameters of new OTA are DC gain (87.32[Formula: see text]dB), common mode rejection ratio (145.47[Formula: see text]dB), gain bandwidth (4.73[Formula: see text]MHz), phase margin (36.56[Formula: see text]). These figures are significantly improved as compared to conventional OTAs. Analog-to-digital convertor (ADC) is also designed as an application of the proposed OTA. The improvements offered by ADC in terms of power and bandwidth are also compared with state of the art.

A programmable analog front-end with independent biasing technique for ECG signal acquisition

This paper presents a programmable low power and low noise analog front-end (AFE) for electrocardiogram (ECG) signal acquisition. A novel capacitor-coupled instrumentation amplifier (CCIA) features independent biasing technique and AC coupling to signal source is proposed. Independent biasing technique is capable of obtaining better noise performance and more stable static working point reducing the glitch of chopping. An AC coupling style helps suppress electrode DC offset and enhance input impedance with metal-oxide-metal capacitor array, which is symmetrical to the center to alleviate the mismatch of input capacitor enhancing system common mode rejection ratio (CMRR). The current steering technology (CST) and programmable feedback capacitors are utilized to achieve an area-efficient programmable low pass filter (PLPF) under PVT variations. Also, a charge buck after PLPF is introduced to strengthen the driving ability of AFE. To verify the proposed AFE structure, a prototype is designed in 0.13 μm standard CMOS process with a 1.2 V supply. Post-simulation results show that the input impedance reaches 1.4 GΩ under 50 Hz. The in-band white noise density and integrating noise are 48 nV/sqrt (Hz) and 0.6 μV, respectively. The obtained low pass corner of PLPF are 380 Hz, 451 Hz and 1 kHz. The CMRR and PSRR under montecarlo simulation are 93 dB and 77 dB, respectively. The power of whole AFE is 48 μW.

A Differential Difference Amplifier Employing Pseudo-Differential CMFB for Neural Signal Recording Applications

This brief presents a differential difference amplifier (DDA) with a pseudo-differential (PD) common-mode feedback (CMFB) for neural signal recording. One of the input transconductors within the proposed DDA is connected to target neural signal, to ensure a high input impedance. Another input transconductor employs a self-stabilized topology to stabilize the dc quiescent point and to determine the cut-off frequency. The CMFB is applied via the proposed PD terminal. Benefiting from the parallel connection of PD, the common mode rejection ratio (CMRR) is approximately increased by a factor of differential-mode gain, without damaging the voltage headroom and dynamic range. Moreover, the proposed PD CMFB is suitable for multi-channel neural signal acquisition, the more the channels, the higher the CMRR. The circuits are targeted at IC realization, designed in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\mu }\text{m}$ </tex-math></inline-formula> CMOS technology. It achieves an input impedance of circa 51 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}\boldsymbol{\Omega }$ </tex-math></inline-formula> at 100 Hz, a CMRR of 103 dB, and a power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.8~\boldsymbol {\mu }\text{W}$ </tex-math></inline-formula> . The proposed DDA (two channels) with a system PD CMFB consumes a die area of 0.24 mm2.

C-Band optical 90-degree hybrid using thin film lithium niobate.

The integrated optical 90-degree hybrid is a crucial component for coherent receivers. Here, we simulate and fabricate a 4 × 4 multimode interference coupler as a 90-degree hybrid using thin film lithium niobate (TFLN). The device features low loss (0.37 dB), high common mode rejection ratio (over 22 dB), compact footprint, and small phase error (below 2°) within the whole C-band experimentally, which is promising for integration with coherent modulators and photodetectors for TFLN-based high-bandwidth optical coherent transceivers.

A Fully Differential Analog Front-End for Signal Processing from EMG Sensor in 28 nm FDSOI Technology

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 GΩ with a chip area of 0.09 mm2.

A chopper amplifier with a pseudo MOS resistor-based tunable bandwidth for EEG applications

PurposeThe purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.Design/methodology/approachThis paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.FindingsThe total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.Research limitations/implicationsAll kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.Practical implicationsThe proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.Originality/valueThe high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

A Measurement System with High Precision and Large Range for Structured Surface Metrology Based on Atomic Force Microscope

With the rapid and continuous development of nanomanufacturing technology, the demands for both large range and high precision metrology of structured surfaces are becoming increasingly urgent. This paper proposes a metrological measurement system based on a commercial atomic force microscope. By using the nano-positioning platform from SIOS, the measurement range of the system expands from 110 μm × 110 μm × 20 μm to 25 mm × 25 mm × 5 mm. A signal amplifier with low noise and a high common mode rejection ratio that decreases the noise level of the measurement system to 2 nm is designed. Integration of the metrological system, signal processing, and calibration of the whole system is introduced. Three experimental studies are carried out on an ultrahigh step, an atomic deposition grating, and a cutting tool. The experimental results demonstrate high measurement repeatability and reproducibility in both vertical and lateral directions. By repeating 10 times of measurement, the expended uncertainties of the step and the grating measurement are 36.24 nm and 0.60 nm, respectively. Additionally, measurement of a cutting tool tip is conducted to illustrate the performance of the system. The Ra and Rz values of the tool tip arc ripple are 29.8 nm and 189 nm, respectively.

Interactive Analog Layout Editing With Instant Placement and Routing Legalization

Analog layout design is still primarily reliant on manual efforts. Current fully automated workflows are unable to meet the expectations for flexible customization and are incompatible with existing manual workflows. For both performance and productivity, interactive layout editing has the ability to bridge the gap between manual and automated flows. We present an interactive layout editing system in this study that includes well-defined commands for both placement and routing customization. This is a pioneering work that provides a holistic study on the interactive design methodology for analog layouts and its capability of speeding up design closure. Our framework comes up with the instant placement legalization and routing adjustment mechanism for rapid layout update and modification. The framework is capable of handling real-time user interaction and improving the performance of fully automated layout generators verified by post-layout simulation on real-world analog designs. Experimental results demonstrate the performance enhancement on real-world analog designs with only a few editing commands. As examples, on the low-dropout regulator, our framework can reduce the overshot down and up voltage to nearly <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/3$ </tex-math></inline-formula> of layout generated by automation tool with two editing commands, and on the operational transconductance amplifier, it achieves 33.5% better common mode rejection ratio with only one command.

A Review of Techniques to Enhance an Amplifier’s Performance Using Resistive Local Common Mode Feedback

A review of some of the most common applications of the resistive local common mode feedback technique to enhance amplifier’s performance is presented. It is shown that this simple technique offers essential improvement in open loop gain, gain-bandwidth product, slew rate, common mode rejection ratio, power supply rejection ratio, etc. This is achieved without increasing power dissipation or supply voltage requirements and with small additional silicon area and circuit complexity. It is also shown that it is especially appropriate to improve amplifiers’ performance in current fine-line submicrometer CMOS technology. Some of the applications discussed are GB enhanced, class AB and super class AB operational amplifiers, gain boosted op-amps, bulk-driven circuits, sample and hold circuits and power management circuits, among others.

Design and Analysis of Low-Power Bulk-Driven Operational Transconductance Amplifier: A Self-Cascode Partial Positive Feedback Approach

Achieving high-gain and low-noise operation of bulk-driven (BD) operational transconductance amplifier (OTA) with low-power consumption is a challenging task owing to inherent low transconductance and high noise in BD MOSFET. In this paper, we report a self-cascode partial positive feedback (SCPPF) approach-based BD OTA and have fairly compared the results with regular single MOS partial positive feedback (PPF) approach-based BD OTA. In comparison to regular BD PPF OTA, the proposed BD SCPPF OTA yields an improved gain of 68.71 dB, gain-bandwidth of 39.4 kHz, power consumption of 630 nW, output impedance of 0.4 MΩ and common mode rejection ratio of 134.4 dB for same input referred noise of 1.11 μV/√ Hz at frequency of 10 Hz and supply voltage of ±0.5 V. The area consumed by BD SCPPF OTA is 0.0523 mm2. The proposed BD SCPPF OTA can be possibly used to improve the performance of biomedical analog front-end sensing and signal processing systems.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

Current state and challenges of ECG amplifiers

This paper describes and compares three amplifiers for ECG recording, namely a four-transistor stage band-pass amplifier, a DDA-based fully differential CMOS instrumentation amplifier and an OTA amplifier using current reuse. The performance metrics of the three amplifiers are listed, their respective advantages are compared, what factors limit their disadvantages are analyzed, the current state of the art and the direction of development of the ECG amplifier are indicated, and suggestions are given for further enhancement of the ECG amp. These amplifier circuits are designed in 0.35 µm CMOS and are verified by layout followed by simulation simulations. The results show that running at 2V dc supply, the quad-transistor stage amplifier and the DDA fully differential amplifier consume 672nW, obtain at least 2uVrms of input reference noise, and obtain greater common mode rejection ratios of 86dB and 83dB, while the OTA amplifier consumes less 320nW, obtains the most 2.05uVrms of input reference noise, and obtains a smaller common-mode rejection ratio of 65dB.

Design of ECG Signals Filter Circuit Based on OTA Filtering

The ECG signal reflects the physiological characteristics of the heart to a certain extent and is an extremely important clinical reference for the diagnosis, treatment, and prevention of cardiovascular diseases. However, the ECG signal is affected by various noises during the acquisition process, especially the 50Hz noise from power lines which makes the diagnosis and analysis of ECG difficult. In this paper, a transconductance amplifier with strong practical applications is proposed and designed to filter out interference from ECG signals in power lines, based on the characteristics of ECG signals and the ability of differential signals to effectively resist external common-mode noise. This amplifier is able to effectively filter out 50Hz interference from power lines and features a high common-mode rejection ratio and low power consumption, in addition to using relatively few components and low production costs.

Aging-robust amplifier composed of p-type low voltage OTFT and organic semiconductor load

This paper proposes an amplifier circuit design suitable for low-voltage organic thin-film transistors (OTFTs). To overcome the issues common to low-voltage OTFTs, such as the yield, degradation, and performance differences between p-type and n-type TFTs, we design the circuit based on an inverter comprising only p-type transistors. The optimal bias voltage for the amplifier stage is provided through a bias circuit. The transistor performance degradation is compensated for by sharing the gate bias voltage (i.e. the main cause of degradation) between the bias and amplifier stages. In addition, an organic semiconductor is used as a passive load of the amplifier to reduce the area and failure probability. Test chip measurements demonstrate that the organic material operates as a resistor. The gain and cut-off frequencies of the proposed amplifier circuit can be adjusted by changing the size of the dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]-thiophene resistor, providing a maximum gain of 27 dB. The proposed circuit can operate continuously for over 100 min without significant characteristic changes. The operation of the bias circuit, when applied to a differential amplifier design, is also verified. The differential amplifier achieves a maximum common-mode rejection ratio of 25 dB.

Design of current controlled instrumental amplifier by using complementary metallic oxide semiconductor technology

&lt;p&gt;In this paper, a complementary metal oxide semiconductor (CMOS) instrumental amplifier was designed and implemented in order to provide the possibility of controlling the current and voltage gain. The proposed instrumentation amplifier consists of three conveyors with active resistor. The parasitic resistance value (Rx) was reduced with a large bandwidth level in addition to achieving a high common mode rejection ratio (CMRR). Simulation was performed by using 0.35μm CMOS technology by using the advanced design system (ADS) software. The results obtained prove that the proposed circuit has a good efficiency with higher degree of CMRR in comparison with other amplifiers designed and implemented in other similar works.&lt;/p&gt;

Buck Converter Current Measurement Using Differential Amplifier

The accuracy of the measured current is a preeminent parameter for Current Control based Power Converter applications to ensure genuine operation of the designed converter. The current measurement accuracy can be affected by several parameters which includes the type of technology used, components used for the selected technology, aging, usage, operating and environmental conditions. The effect of gain resistors and their manufacturing tolerances on differential amplifier-based buck converter current measurement is investigated in this work. The analysis mainly focused on the output voltage variation and its accuracy with respect to the change in gain resistance tolerances. The gain resistors with 5%, 1%, 0.5% and 0.1% manufacturing tolerances taken for the worst-case analysis and the calculated performance results are compared and verified with the simulation results. The Operational amplifiers (Op-Amp) for high frequency power converter applications must operate in a high frequency noise environment and the intended current measuring system must manage common mode noise disturbances paired with the signal to be measured. Based on the Common Mode Rejection Ratio (CMRR) the common mode voltages and noise signals will effectively get filtered out. Lesser CMRR results in lower common mode signal rejection, resulting in poor precision and noise rejection. In differential amplifiers, the CMRR predominantly depends on gain resistors. So, the variations in Common Mode Rejection Ratio due to gain resistor tolerances also analyzed and compared with the output voltage variations. Besides the effects of resistor tolerances, this paper also examines the effect of Op-Amp offset voltage on output accuracy specifically for low magnitude input currents. The obtained results from this analysis clearly shows that the gain resistors with 0.1% tolerance gives maximum accuracy with improved CMRR and accuracy at low magnitude input currents will get well improved by using Op-Amps with Low Offset voltage specifications.