Common-emitter Topology Research Articles

A 0.78–0.91–THz Wideband Frequency Tripler With Harmonic-Matched Bias Network

A 0.78–0.91-THz wideband frequency tripler is demonstrated using a 250-nm InP DHBT technology. Considering potential inaccuracy of the transistor model at the submillimeter-wave frequencies, a simple one-stage common-emitter topology is adopted for the wideband and stable operation. To enhance the output power and suppress the unwanted harmonics, a harmonic-matched bias network is used for dc feed at the output. The frequency tripler was measured with an on-chip probing method. Although an overmode waveguide probe was used, which imposes an additional measurement loss, a peak output power was measured as -28 dBm at 0.813 THz. The bandwidth for a -35-dBm output power ranges from 0.78 to 0.91 THz. The conversion loss is from 35.9 to 45 dB over the bandwidth. The chip area is 273 × 460 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the dc power consumption is 22 mW.

UWB HABERLEŞME İÇİN BİR DARBE ÜRETEN DEVRENİN TASARIMI

Generation of very short pulses with a pulse width in the order of a few nanoseconds or less is a requirement for an UWB communications system. A pulse generator circuit based on the step-recovery effect of an RF transistor has been designed for the 0-960-MHz UWB system, and is presented in this paper. The pulse generator includes a linear RF amplifier with common-emitter topology and a high-pass filter following the amplifier. Input of the RF amplifier is driven by a clock signal provided by a function generator. Amplifier output includes positive amplitude and negative amplitude pulses due to rising and falling edges of the collector-emitter voltage of the transistor, respectively. Amplifier output is then fed to a high-pass filter. Low-frequency transitions are further filtered out, and the output of the high-pass filter is a pulse train consisting of very short pulses. The pulse width has been measured as about 2.5 ns using a 300-MHz digital oscilloscope.

A G-band terahertz monolithic integrated amplifier in 0.5-μm InP double heterojunction bipolar transistor technology**Project supported by the National Natural Science Foundation of China (Grant No. 61501091) and the Fundamental Research Funds for the Central Universities of Ministry of Education of China (Grant Nos. ZYGX2014J003 and ZYGX2013J020).

Design and characterization of a G-band (140–220 GHz) terahertz monolithic integrated circuit (TMIC) amplifier in eight-stage common-emitter topology are performed based on the 0.5-μm InGaAs/InP double heterojunction bipolar transistor (DHBT). An inverted microstrip line is implemented to avoid a parasitic mode between the ground plane and the InP substrate. The on-wafer measurement results show that peak gains are 20 dB at 140 GHz and more than 15-dB gain at 140–190 GHz respectively. The saturation output powers are −2.688 dBm at 210 GHz and −2.88 dBm at 220 GHz, respectively. It is the first report on an amplifier operating at the G-band based on 0.5-μm InP DHBT technology. Compared with the hybrid integrated circuit of vacuum electronic devices, the monolithic integrated circuit has the advantage of reliability and consistency. This TMIC demonstrates the feasibility of the 0.5-μm InGaAs/InP DHBT amplifier in G-band frequencies applications.

AN ultra-wideband SiGe BiCMOS LNA for W-band applications

This article presents the design steps and implementation of a W-band ultra-wideband low noise amplifier (LNA) for both automotive and imaging applications. Three amplifiers based on common-emitter topology with different configurations are manufactured using IHP 0.13 mu m SiGe BiCMOS 300/500 GHz (f(t)/f(max)) SG13G2 technology. A three-stage single-ended structure is proposed for ultra-wideband imaging purposes. As the results are analyzed, this 0.2 mm(2) LNA can operate in a 25 GHz of measured 3-dB bandwidth in W-band with 21 dB peak gain and 4.9 dB average noise figure using 1.5 V supply voltage. It consumes 50 mW of power in the edge operation conditions and the output 1 dB compression point is found as -4 dBm. To the authors' knowledge, this chip achieves one of the best overall performances compared to other W-band LNAs.

Designing Linear PAs at Millimeter-Wave Frequencies Using Volterra Series Analysis

Power amplifiers (PAs) at millimeter-wave (mm-wave) frequencies are required for delivering high output linear power while being efficient; however, their performance is severely affected by the scaled semiconductor technology and the operating frequency. To improve the linearity of mm-wave PAs, it is recommended that an external linearization technique such as predistortion be used. The PA presented in this paper uses adaptive predistortion (APD). The APD linearization technique was developed using the Volterra series analysis on the silicon–germanium (SiGe) heterojunction bipolar transistor. The Volterra series analysis was used to identify and characterize the third-order intermodulation distortion components. The PA uses a single-ended common-emitter topology. It consists of three stages biased in the Class AB mode. The PA and APD were designed using the 130-nm SiGe bipolar and complementary metal–oxide–semiconductor process. The PA and APD achieve an optimum third-order intermodulation reduction of 10 dB and an improved linear output power of 2.5 dBm.

A SiGe LC-ladder low noise amplifier with base resistance match, gain and noise flatness for UWB applications

This study presents a 3.1–10.6GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S21) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33mW power and achieves S21 of 20.65+0.7dB, NF of 2.79+0.2dB over the band of 3.1–10.6GHz. The simulated input third-order intermodulation point (IIP3) is −17dBm at 10GHz.

A Low Noise Amplifier with 1.1dB Noise Figure and +17dBm OIP3 for GPS RF Receivers

A 1.575GHz SiGe HBT(heterojunction bipolar transistor) low-noise-amplifier(LNA) optimized for Global Positioning System(GPS) L1-band applications was presented. The designed LNA employed a common-emitter topology with inductive emitter degeneration to simultaneously achieve low noise figure and input impedance matching. A resistor-bias-feed circuit with a feedback resistor was designed for the LNA input transistor to improve the gain compression and linearity performance. The LNA was fabricated in a commercial 0.18µm SiGe BiCMOS process. The LNA achieves a noise figure of 1.1dB, a power gain of 19dB, a input 1dB compression point(P1dB) of -13dBm and a output third-order intercept point(OIP3) of +17dBm at a current consumption of 3.6mA from a 2.8V supply.

Common-emitter topology of multilevel current-source pulse width modulation inverter with chopper-based DC current sources

The study proposes a new circuit configuration of multilevel current-source inverter (CSI). In this new multilevel CSI topology, all power switching devices of the inverter are connected at a common-emitter point or at a common-potential line. Hence, all the power switches need only a single gate drive power supply without using isolated power supplies or conventional bootstrap techniques. This feature is still valid even if the number of the power switches increases owing to the higher-level number of the output current waveform. As a result, complexity of the gate drive circuit can be remarkably moderated. In addition, the multilevel CSI circuit is more capable to operate at high switching frequency if required, because all the power switches are connected at a common potential level. A five-level pulse width modulation inverter configuration, including chopper circuits as DC current-power source circuits using small smoothing inductors, is verified through computer simulations and experimental tests. The results show feasibility of the proposed multilevel inverter topology with reducing the complexity of the gate drive circuits, the inductor size, total harmonic distortion (TMD) of output current and increasing the efficiency of the multilevel CSI.

Three-Level Current-Source PWM Inverter with No Isolated Switching Devices for Photovoltaic Conditioner

This paper presents a new configuration of a three-level current-source PWM inverter (CSI) with a full common-source or common-emitter topology in terms of all transistor switching devices. Using this new configuration, the number of gate or base drive power supplies can dramatically be reduced to only a single instead of use of several isolated power supplies or conventional bootstrap circuits. As a result, bulky, heavy and expensive transformers and capacitors in the drive circuits are eliminated. In addition, the proposed configuration is capable to be operated at a higher switching frequency and a higher voltage without violent potential changes because of its common-source or common-emitter topology. Design and operation principle of the new circuit are investigated and analyzed using computer simulations. Finally, effectiveness of the circuit is experimentally verified by using a laboratory prototype set up. The simulation and the experimental results show that the circuit works properly to generate a three-level output current waveform, which proves feasibility of the proposed approach.

Novel current‐source multilevel inverter driven by single gate drive power supply

AbstractThis paper proposes a novel current‐source multilevel inverter, which is based on a current‐source half‐bridge topology. Multilevel inverters are effective for reducing harmonic distortion in the output voltage and the output current. However, the multilevel inverters require many gate drive power supplies to drive switching devices. The gate drive circuits using a bootstrap circuit and a pulse transformer can reduce the number of the gate drive power supplies, but the pulse width of the output PWM waveform is limited. Furthermore, high‐speed power switching devices are indispensable to create a high‐frequency power converter, but various problems, such as high‐frequency noise, arise due to the high dv/dt rate, especially in high‐side switching devices. The proposed current‐source multilevel inverter is composed of a common emitter topology for all switching devices. Therefore, it is possible to operate it with a single power supply for the gate drive circuit, which allows stabilizing the potential level of all the drive circuits. In this paper, the effectiveness of the proposed circuit is verified through experimental results. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 166(2): 88–95, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20475

Novel Current-Source Multi-Level Inverter Driven by Single Gate Drive Power Supply

This paper proposes a novel current-source multi-level inverter, which is based on a current-source half bridge topology. Multi-level inverters are effective to reduce harmonic distortion of the output voltage and the output current. However, the multi-level inverters require many gate drive power supplies to drive switching devices. The gate drive circuits using a bootstrap circuit and a pulse transformer can reduce the number of the gate drive power supplies, but a pulse width of the output PWM waveform is limited. Furthermore, high-speed power switching devices are indispensable to compose a high-frequency power converter but various problems of high frequency noise arise due to high dv/dt rate, especially in high-side switching devices.The proposed current-source multi-level inverter is composed with a common emitter topology of all switching devices. Therefore, it is possible to operate with a single power supply of gate drive circuit, which allows stabilizing a potential level of all the drive circuits.In this paper, effectiveness of the proposed circuit is verified with experimental results.