Common-drain Amplifier Research Articles

A LoC Ion Imaging Platform for Spatio-Temporal Characterisation of Ion-Selective Membranes.

In this paper, a complete Lab-on-Chip (LoC) ion imaging platform for analysing Ion-Selective Membranes (ISM) using CMOS ISFET arrays is presented. An array of 128 × 128 ISFET pixels is employed with each pixel featuring 4 transistors to bias the ISFET to a common drain amplifier. Column-level 2-step readout circuits are designed to compensate for array offset variations in a range of up to ±1 V. The chemical signal associated with a change in ionic concentration is stored and fed back to a programmable gain instrumentation amplifier for compensation and signal amplification through a global system feedback loop. This column-parallel signal pipeline also integrates an 8-bit single slope ADC and an 8-bit R-2R DAC to quantise the processed pixel output. Designed and fabricated in the TSMC 180 nm BCD process, the System-on-Chip (SoC) operates in real time with a maximum frame rate of 1000 fps, whilst occupying a silicon area of 2.3 mm × 4.5 mm. The readout platform features a high-speed digital system to perform system-level feedback compensation with a USB 3.0 interface for data streaming. With this platform we show the first reported analysis and characterisation of ISMs using an ISFETs array through capturing real-time high-speed spatio-temporal information at a resolution of 16 μm in 1000 fps, extracting time-response and sensitivity. This work paves the way of understanding the electrochemical response of ISMs, which are widely used in various biomedical applications.

Design of a Linear LNA for 5G Applications using 45 nm Technology

A low noise amplifier (LNA) plays a very significant role in communication systems. Despite having a good amplification of the signal it must offer other attributes like noise figure, linearity etc for making the communication system more robust. With the advent of 5G communication, the requirement of a high BW LNA is becoming important. This paper presents the design of a LNA which have a common gate input configuration, an active inductor in place of a passive inductor, common drain amplifier at the output stage and a linearity circuit. Common gate amplifier offers a good voltage amplification while the common drain stage enhances the stability. The active inductor facilitates reduction of the die area paving the way for a cost efficient structure. This proposed design achieves a gain of 15.17dB with substantial enhancement of linearity. A good noise figure of 7dB is obtained while using 11 transistors and eliminating the need of passive inductors. The peak gain is achieved at 3.5GHz

A 10-MHz Current-Mode AOT Boost Converter With Dual-Ramp Modulation Scheme and Translinear Loop-Based Current Sensor for WiFi IoT Applications

In this article, a dual-ramp modulation scheme is proposed to solve an instability during the discontinuous conduction mode (DCM) operation of current-mode constant on-time (COT) controlled boost converters. A duty cycle-dependent auxiliary waveform, which is generated by the proposed capacitor-coupled common-drain amplifier (CCCDA), is summed with an inductor current information to form a current feedback loop. With the proposed scheme, the pulse frequency modulation (PFM) operation can be spontaneously accompanied by the current-mode COT control to enhance a light-load efficiency. In addition, a translinear loop (TLL)-based valley current sensor is introduced to sense a valley inductor current while solving the response time and stability problems of the previous SenseFET-based current sensor. An adaptive ON-time (AOT) generator provides a quasi-fixed switching frequency in the CCM operation regardless of the conversion ratio. The proposed boost converter has been fabricated using a 0.18- μm CMOS process with a total chip area of 1.23 mm × 1.37 mm. It achieves a peak efficiency of 94.5% even at a high-switching frequency of 10 MHz, and smooth mode transition between PFM and pulsewidth modulation (PWM) operations depending on the load conditions.

On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks

In this work an evaluation of analog building blocks using junctionless nanowire transistors is presented. This analysis has been carried out through experimental measurements of junctionless nMOS transistors configured as two amplifier stages composed by single transistors, namely the common-source and the common-drain amplifiers. The performance of junctionless devices is evaluated as a function of channel length, nanowire width, doping concentration and bias condition, taking as figures of merit the voltage gain, linearity and, in the case of the common drain amplifier, the input voltage range. The obtained results indicate that these two basic analog blocks can be benefitted by the use of junctionless devices, providing nearly ideal voltage gain when configured as common-drain amplifier, and improvement on voltage gain and linearity with device narrowing in the case of the common-source amplifier.

Analysis and design of class-O RF power amplifiers for wireless communication systems

In this paper, we present analysis, design and show experimental results of a new type of CMOS based power amplifier (PA) known as class-O Aref et al. (ISSCC Digest of Technical Papers, 2015). Modern CMOS based PAs design is constrained by three fundamental trade-offs, i.e. linearity, efficiency and reliability. More precisely, for a standalone PA, unless advanced and expensive solutions are employed, no such PA architecture exists which is able to meet aforementioned design trade-offs. Theoretical insight is needed to understand the origin of performance trade-offs and the possible solutions to counter them. Class-O is a novel out-of-the-box solution to meet these tough challenges. Our prototype amplifier is a highly linear low-band 706 MHz 4G long term evolution (LTE) compatible class-O RF power amplifier in 130 nm CMOS technology for handheld wireless applications. The class-O architecture uses two sub-amplifiers working together as one grand PA. These two sub-amplifiers are common-source (CS) and common-drain (CD) amplifiers working in parallel feeding a common load with high linearity without the need for digital predistortion (DPD). The prototype chip is measured and characterized with continuous wave (CW), modulated signal and reliability measurements. With CW measurements, 1-dB compression point (P$$_{1\,{\mathrm{dB}}}$$1dB) of 30.6 dBm and peak power added efficiency (PAE) of 45.2 $$\%$$% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20 MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an adjacent channel power ratio (ACPR) less than ź30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20 $$\%$$%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst voltage-standing-wave-ratio (VSWR) conditions.

Design of a New CMOS TRA

A new complementary metal oxide semiconductor transresistance amplifier that is very suitable for high-gain and low-voltage analog application is presented in this paper presents. The designed transresistance amplifier features common-source and gain-boosting topology to improve the gain of the transresistance amplifiers. The complementary metal oxide semiconductor transresistance amplifier provides low input and output impedances, which are required for the design of I-V analog circuits. Conventional common-drain, current-mirror, and common-gate transresistance amplifiers are analyzed through small signal analysis and simulation, and the results are compared with those of the proposed transresistance amplifiers. HSPICE simulation confirmed that the proposed transresistance amplifier has a gain of 83.9 dBΩ and provides higher gain by up to 30.1dBΩ compared to the other transresistance amplifiers.

A physically-derived nonquasi-static model of ferroelectric amplifiers for computer-aided device simulation – Part I: The ferroelectric common-drain amplifier

A physically-derived nonquasi-static model describing the behavior of the ferroelectric common-drain amplifier is presented. The model is based on the method of partitioned channel and ferroelectric layers and is valid in accumulation, depletion, and the three inversion cases: weak, moderate, and strong. The equations of this model are based on the standard MOSFET equations that have been modified to reflect the ferroelectric properties. The model code is written in MATLAB and outputs voltage plots with respect to time. The accuracy and effectiveness of the model are verified by a few test cases, where the modeled results are compared to empirically-derived oscilloscope plots.

Expanded Characterization of the Common-Drain Amplifier Using Metal-Ferroelectric-Semiconductor Field Effect Transistors

Data is presented in this paper that was obtained using a metal-ferroelectric-semiconductor field effect transistor (MFSFET) in a common-drain amplifier configuration. The empirical data shown has been collected using larger drain voltages than previously seen, which helps to further understand and characterize the interesting operation of this amplifier circuit. The effects of varying different parameters such as load resistance, poling voltage, and input voltages of the amplifier circuit are examined. Differences between the MFSFET and MOSFET common-drain amplifier configurations are explored in-depth.

A Mathematical Model for the Common-Drain Amplifier Using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

This paper presents a new mathematical model created for the common-drain amplifier using metal-ferroelectric-semiconductor field effect transistors (MFSFET). The model developed in this paper is based upon empirical data collected through experimentation with the common-drain amplifier while using a MFSFET. Several parameters are considered when calculating the output voltage, such as varying gate capacitance, input voltage, quiescent point, and power supply voltages. A comparison between collected and modeled data is presented as verification of the model's performance when applied to the common-drain configuration.

A MATHEMATICAL MODEL OF A COMMON-DRAIN AMPLIFIER USING A FERROELECTRIC TRANSISTOR

ABSTRACT This paper presents a mathematical model characterizing the behavior of a common-drain amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the amplifier is the basis of many circuit configurations, a mathematical model that describes the behavior of a FeFET-based amplifier will help in the integration of FeFETs into many other circuits.

Amplifiers using bipolar and unipolar transistors with limited drain—source voltage

An important class of amplifiers uses a field-effect device in the first stage and a bipolar transistor in the second. If the drain-source voltage of the former is limited to the base-emitter voltage of the latter, a particularly simple circuit arrangement results. Other advantages of operation in this mode include reduction in the power dissipated in the field-effect device, improvement in high-frequency response and, when circuit constants are suitably chosen, some degree of inherent compensation for change of working conditions due to thermal effects. Of the four possible configurations which give high input impedance and voltage gain, it is shown that only two can easily be stabilised against working-point changes, and of these one [in which a common-drain (c.d.) amplifier precedes a common-emitter (c.e.) stage] is preferred, because it exhibits higher gain and lower output impedance and needs only a single polarity of supply voltage. The transfer conductance, input and output impedances and thermal drift of the c.d.-c.e. amplifier are calculated, using an equivalent circuit in which the drain-source channel is represented by a variable resistor.