Commercial Silicon Carbide MOSFETs Research Articles

Assessing Short-Circuit Robustness of 1200 V SiC MOSFETs: Using Deep Structural and Physical Analysis

Silicon carbide (SiC) transistors are known for their high breakdown voltage capabilities and ability to operate at much higher temperatures relative to silicon (Si) power semiconductors. The first commercial SiC MOSFETs were introduced in 2010 [1], [2]. Currently, third generation devices are in production and leading manufacturers will soon release fourth generation products [3]. However, usage of these devices requires special considerations. Due to its impact in circuit design and device reliability, short-circuit (SC) robustness is of prime importance among them.

Effect of Gate-Oxide Degradation on Electrical Parameters of Silicon Carbide MOSFETs

Although gate-oxide degradation occurs in both silicon (Si) and silicon carbide (SiC) MOSFETs, it requires a special attention in SiC MOSFETs. This is because the gate oxide in SiC MOSFETs is comparatively thinner than the gate oxide in Si MOSFETs, and thus, a higher electric field that appears across it could push the gate oxide to its reliability limit. While several electrical parameters have been identified as precursors (indicators) for monitoring the gate-oxide degradation process in Si MOSFETs, very few have been identified for their SiC counterparts. The purpose of this article is twofold. The first objective is to demonstrate that the three gate-oxide degradation precursors identified for Si MOSFETs: 1) threshold voltage, 2) gate-plateau voltage, and 3) gate-plateau time can also be extended to SiC MOSFETs. The second objective is to demonstrate analytically and experimentally that all three precursors increase in a linear-with-log-stress-time manner during gate-oxide degradation in both planar and trench-gate SiC MOSFETs. The increasing trends of precursors and their associated logarithmic time responses were experimentally verified by inducing accelerated gate-oxide degradation in two different commercial SiC MOSFETs (650-V, 70-A trench-gate MOSFETs and 1200-V, 19-A planar MOSFETs) under high temperatures of 150 and 125 °C, respectively.

The Current Status and Trends of 1,200-V Commercial Silicon-Carbide MOSFETs: Deep Physical Analysis of Power Transistors From a Designer’s Perspective

There is continuous activity to increase the efficiency and reduce the size of power electronic systems and modules developed for transportation and automotive electrification applications [1], [2]. One of the key requirements for achieving these objectives is to operate semiconductor devices at higher power density and junction temperature (Tj max), while maintaining high reliability. The emergence of wideband-gap (WBG) semiconductors [silicon carbide (SiC) and gallium nitride (GaN)] [9] and new high-temperature die-attach methods, interconnects, and packaging materials [9] enables power-device manufacturers to increase Tj max from Tj = 150 °C to Tj = 175 °C and, further, to Tj = 200 °C [3]-[10].

Design Methodology of DC Power Cycling Test Setup for SiC MOSFETs

The long-term reliability concerns regarding the latest power devices, e.g., silicon carbide (SiC) MOSFETs, need to be well understood for their rapid and widespread deployment in industrial applications. As an effective reliability assessment, the dc power cycling test is one of the most realistic procedures providing accelerated lifetime tests. In this paper, a dc power cycling setup for SiC power MOSFETs is proposed, and the design methodology is generalized for practicing engineers. At first, the aging-independent junction temperature measurement method is identified to eliminate the laborious recalibration process. Specifically, the electrical parameter changes of commercial SiC MOSFETs are evaluated in a power cycling test. It is observed experimentally that the body diode's voltage drop at low current and negative gate bias is unaffected by the device/package degradation. Therefore, it is selected for T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</sub> measurement in the proposed setup. Following that, the design considerations regarding precise parameter measurement of the device's parameter are presented. The transient behavior of the proposed test setup is analyzed, and a simulation model is built in LTspice. Based on the model, the effects of gate timing control and paralleled capacitors are investigated for realizing accurate measurements, and the simulation results are verified experimentally in a prototype. In addition, considering the measurement delay in the conditioning circuits and the common-mode noise, the practical issues affecting the measurement accuracy in a multiple-phase setup are investigated in the experiment. Experimental results show that an accurate measurement can be achieved with the design considerations.

SiC Stacked-Capacitor Converters for Pulse Applications

Pulse power converters demands single high voltage and current pulse shape waveform in high temperature, heavy neutrons, and ions radiation environment, where ${\text{50}}\% \sim {\text{75}}\%$ voltage derating margin is typically required for the power devices. silicon carbide (SiC) mosfet s are promising to improve radiation reliability owing to wide band-gap. However, the conventional converters with off-the-shelf commercial SiC mosfet s cannot provide enough voltage margin accordingly. A stack-capacitor pulse converter topology is proposed to reduce the voltage stress of switching devices and capacitors and improve the voltage derating capability significantly. The main idea is to build high voltage with multiple low voltage stacks instead of single high voltage capacitors, so that SiC mosfet s can be applied with improved voltage margin. The method is to charge the stack-capacitors in parallel with fast charging speed, and discharge in series for high pulse voltage. The converter operates at higher switching frequency, which reduces the weight and size of the magnetic components. A 300-kHz prototype with 18–28 V input and 1 kV/ 100 A output was built using 650 V SiC devices, demonstrating 75% reduction of the voltage stress of the capacitors and power devices compared with the conventional converters.

Extremely Low ON-Resistance SiC Cascode Configuration Using Buried-Gate Static Induction Transistor

A 35-A cascode configuration of a drain-to-source breakdown voltage of 978 V utilizing an silicon carbide (SiC) buried gate static induction transistor (BGSIT) and low voltage Si-MOSFET (SiC-BGSIT cascode) has been experimentally demonstrated for the first time. The SiC-SIT is mounted with the Si-MOSFET in an originally designed resin 4pin package. The ON-resistance $R_{\text {DS(ON)}}$ of this device exhibits 34.3 $\text{m}\Omega $ at room temperature, which is 50% of the commercial SiC MOSFET of the similar rating. The temperature dependence of $R_{\text {DS(ON)}}$ and gate threshold voltage has been revealed. It has been suggested that when compared with the SiC-JFET cascode with the similar rating, the BGSIT cascode has a soft $\textit {dV}_{\text {ds}}/\textit {dt}$ property with a relatively small switching loss.

Characterization and Comparison of Planar and Trench Silicon Carbide (SiC) Power MOSFETs

This paper presents a comprehensive evaluation and experimental comparison of silicon carbide power MOSFETs through double pulse test. First, a universal hardware platform is designed and developed to test power semiconductor devices with various device packages and measuring requirements. Using the developed platform, the static characteristics and switching performance of the two types of SiC MOSFETs (one planar and one trench type) are evaluated under different case temperatures from 25 oC to 175 oC. Based on the evaluation data, a comparison of both SiC MOSFETs is conducted in terms of their on-state resistance, switching loss, and temperature dependent behavior. It is found that the latest trench SiC MOSFETs present similar switching loss while much lower conduction loss compared to existing commercial planar SiC MOSFETs. Moreover, the trench devices show a nearly temperature independent switching loss, which is beneficial to suppress the potential thermal runaway issue under high temperature continuous operation.

Characterization and Comparison of Planar and Trench Silicon Carbide (SiC) Power MOSFETs

This paper presents a comprehensive evaluation and experimental comparison of silicon carbide power MOSFETs through double pulse test. First, a universal hardware platform is designed and developed to test power semiconductor devices with various device packages and measuring requirements. Using the developed platform, the static characteristics and switching performance of the two types of SiC MOSFETs (one planar and one trench type) are evaluated under different case temperatures from 25 oC to 175 oC. Based on the evaluation data, a comparison of both SiC MOSFETs is conducted in terms of their on-state resistance, switching loss, and temperature dependent behavior. It is found that the latest trench SiC MOSFETs present similar switching loss while much lower conduction loss compared to existing commercial planar SiC MOSFETs. Moreover, the trench devices show a nearly temperature independent switching loss, which is beneficial to suppress the potential thermal runaway issue under high temperature continuous operation.

Temperature-Dependent Short-Circuit Capability of Silicon Carbide Power MOSFETs

This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.

(Invited) Threshold Voltage Stability Comparison of Commercial SiC Mosfets and Related Issues

Silicon-Carbide (SiC) MOSFETs are beginning to gain wide acceptance for power electronics applications requiring high efficiency and high operational temperatures. There is a growing number of commercial offerings at 1200 V from different manufacturers that may have very distinctive processes that need to be evaluated in a consistent manner to make valid comparisons. As SiC MOSFET technology continues to mature, device performance and reliability should also improve. In recent years, a diverse number of publications in the literature have addressed the poor quality of the MOS gate dielectric layer, and the challenges related to charging of both interface defects and near-interfacial oxide defects during electrical and thermal stressing. A significant number of intrinsic defects in the gate oxide result from growth of the dielectric layer itself. Subsequent process steps can activate a number of these defects which can trap charge during electrical gate-stress, thereby altering the device threshold voltage. During bias temperature stressing, activation of additional oxide defects can occur, which gives rise to larger threshold voltage instabilities. The stability of the MOS threshold voltage under electrical gate-stress at high temperature is an important reliability phenomenon with potential application relevance. A large positive shift reduces on-state conduction, increases power losses, and may reduce efficiency in switch-mode converter applications. A large negative shift in the threshold voltage is a more serious reliability concern because of excessive drain leakage current in the MOS-channel during the off-state. This effect will limit blocking capability and possibly lead to device failure. This work will provide an overview of threshold voltage stability issues in commercially-available SiC MOSFETs subject to both positive and negative gate-stress at high temperature. Figure 1 is a plot of the subthreshold-voltage shift as a function of unipolar (positive) bias stress time for commercial devices purchased between 2012 and 2015. Recent devices show significant improvement in threshold voltage shift for a +25 V gate-bias stress at 175 °C. The older commercial devices shift considerably more, with the onset of degradation occurring much earlier in time. We have also observed differences in the responses of devices from different manufactures for similar stress and test conditions. It is expected that process differences among device manufacturers would in turn, result in differences in the bias-temperature-stress responses. A fuller discussion of these test results and related issues will be presented in the final paper. Figure 1

Single pulse avalanche robustness and repetitive stress ageing of SiC power MOSFETs

This paper presents an extensive electro-thermal characterisation of latest generation Silicon Carbide (SiC) power MOSFETs under Unclamped Inductive Switching (UIS) conditions. Tests are carried out to thoroughly understand the single pulse avalanche ruggedness limits of commercial SiC MOSFETs and assess their ageing under repetitive stress conditions. Both a functional and a structural characterisation of the transistors is presented, with the aim of informing future device technology development for robust and reliable power system development.