Commercial Multiprocessors Research Articles

Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactions

Hardware transactional memory is a new parallel programming paradigm supported by current commercial multiprocessors. This paradigm provides optimistic concurrency and overcomes some of the problems associated with classical lock-based synchronization, such as deadlock and serialization. Certain algorithms of computational geometry are found to be good candidates for parallelization with this paradigm. However, hardware transactional approaches to these algorithms lead to poor performance as the resulting transactions are too large for the underlying hardware to deal with. Large transactions overflow hardware resources serializing the execution.In this paper, we propose using privatizing transactions to parallelize two computational geometry algorithms: Lee’s algorithm, which solves the shortest-route problem, and Ruppert’s algorithm for Delaunay/Voronoi mesh refinement. Privatizing transactions are based on commercial hardware transactional memory extensions, and their goal is to reduce transaction footprint by means of a non-transactional private execution section. This results in effective smaller transactions. Our implementation is able to further reduce the transaction size as we propose a reduced validation set for privatizing transactions. Programming complexity of these implementations is discussed.Results show that our privatizing transaction implementations indeed enhance performance comparing with existing hardware transactional memory versions. Experiments with Intel’s transactional memory extensions yield speedups ranging from 2× to 3.5× with four threads.

Towards High Performance Computing (HPC) Through Parallel Programming Paradigms and Their Principles

Nowadays, we are to find out solutions to huge computing problems very rapidly. It brings the idea of parallel computing in which several machines or processors work cooperatively for computational tasks. In the past decades, there are a lot of variations in perceiving the importance of parallelism in computing machines. And it is observed that the parallel computing is a superior solution to many of the computing limitations like speed and density; non-recurring and high cost; and power consumption and heat dissipation etc. The commercial multiprocessors have emerged with lower prices than the mainframe machines and supercomputers machines. In this article the high performance computing (HPC) through parallel programming paradigms (PPPs) are discussed with their constructs and design approaches.

Software-based rerouting for fault-tolerant pipelined communication

This paper presents a software-based approach to fault-tolerant routing in networks using wormhole or virtual cut-through switching. When a message encounters a faulty output link, it is removed from the network by the local router and delivered to the messaging layer of the local node's operating system. The message passing software can reroute this message, possibly along nonminimal paths. Alternatively, the message may be addressed to an intermediate node, which will forward the message to the destination. A message may encounter multiple faults and pass through multiple intermediate nodes. The proposed techniques are applicable to both obliviously and adaptively routed networks. The techniques are specifically targeted toward commercial multiprocessors where the mean time to repair (MTTR) is much smaller than the mean time between router failures (MTBF), i.e., it is sufficient to tolerate a maximum of three failures. This paper presents requirements for buffer management, deadlock freedom, and livelock freedom. Simulation results are presented to evaluate the degradation in latency and throughput as a function of the number and distribution of faults. There are several advantages of such an approach. Router designs are minimally impacted, and thus remain compact and fast. Only messages that encounter faulty components are affected, while the machine is ensured of continued operation until the faulty components can be replaced. The technique leverages existing network technology, and the concepts are portable across evolving switch and router designs. Therefore, we feel that the technique is a good candidate for incorporation into the next generation of multiprocessor networks.

Multiprocessors should support simple memory consistency models

In the future, many computers will contain multiple processors, in part because the marginal cost of adding a few additional processors is so low that only minimal performance gain is needed to make the additional processors cost effective. Intel, for example, now makes cards containing four Pentium Pro processors that can easily be incorporated into a system. Multiple processor cards like Intel's will help multiprocessing spread from servers to the desktop. But how will these multiprocessors be programmed? The evolution of the programming model is already under way. One important function of the programming model is to describe how memory operates. For a multiprocessor, a reasonable model is sequential consistency (SC), which makes a multiprocessor behave like a multitasking uniprocessor. Nevertheless, many commercial multiprocessors support more relaxed memory models. The author argues that multiprocessors should support SC because-with speculative execution, relaxed models do not provide sufficient additional performance to justify exposing their complexity to the authors of low level software.

Multicoloring of grid-structured PDE solvers on shared-memory multiprocessors

In order to execute a parallel PDE (partial differential equation) solver on a shared-memory multiprocessor, we have to avoid memory conflicts in accessing multidimensional data grids. A new multicoloring technique is proposed for speeding sparse matrix operations. The new technique enables parallel access of grid-structured data elements in the shared memory without causing conflicts. The coloring scheme is formulated as an algebraic mapping which can be easily implemented with low overhead on commercial multiprocessors. The proposed multicoloring scheme bas been tested on an Alliant FX/80 multiprocessor for solving 2D and 3D problems using the CGNR method. Compared to the results reported by Saad (1989) on an identical Alliant system, our results show a factor of 30 times higher performance in Mflops. Multicoloring transforms sparse matrices into ones with a diagonal diagonal block (DDB) structure, enabling parallel LU decomposition in solving PDE problems. The multicoloring technique can also be extended to solve other scientific problems characterized by sparse matrices.

Predicting performance of parallel computations

An accurate and computationally efficient method for predicting the performance of a class of parallel computations running on concurrent systems is described. A parallel computation is modeled as a task system with precedence relationships expressed as a series-parallel directed acyclic graph. Resources in a concurrent system are modeled as service centers in a queuing network model. Using these two models as inputs, the method outputs predictions of expected execution time of the parallel computation and the concurrent system utilization. The method is validated against both detailed simulation and actual execution on a commercial multiprocessor. Using 100 test cases, the average error of the prediction when compared to simulation statistics is 1.7%, with a standard deviation of 1.5%; the maximum error is about 10%. >

Low-synchronization translation lookaside buffer consistency in large-scale shared-memory multiprocessors

Operating systems for most current shared-memory multiprocessors must maintain translation lookaside buffer (TLB) consistency across processors. A processor that changes a shared page table must flush outdated mapping information from its own TLB, and it must force the other processors using the page table to do so as well. Published algorithms for maintaining TLB consistency on some popular commercial multiprocessors incur excessively high synchronization costs. We present an efficient TLB consistency algorithm that can be implemented on multiprocessors that include a small set of reasonable architectural features. This algorithm has been incorporated in a version of the MACH operating system developed for the IBM Research Parallel Processor Prototype (RP3).

Logarithmic indices for multiprocessor evaluation

A method of logarithmic indices for a partial evaluation of potential performance capability of multiprocessors is proposed. The method is independent of the nature of the programs run or any available software capabilities. Consideration parameters can be flexibly added or eliminated as well as relatively weighted. The method is applied to three commercial multiprocessors as an example.

Parallelization of an event driven simulator for computer systems simulation

The technological revolution fueled by the microprocessor has produced commercial multiprocessors. Using basic parallel pro gramming constructs, an existing multiprocessor system simulator is modified to execute in parallel on a shared memory multi processor. Several key techniques used to maximize parallelism are discussed. The simulation speedups achieved while simulating a proposed large scale multiprocessor architecture are reported. Finally, the techniques used in this research are compared with those that have been used by other parallelized simulators.

Parallel Discrete-Event Simulation

The availability of commercial multiprocessors gives a new importance to distributed simulation. However, while existing techniques exploit some levels of parallelism in the discrete-event simulation algorithm, they are usually targeted to specific applications and architectures. In the general scheme presented here, the algorithm is executed in parrallel using a compilation strategy that can be implemented on shared-memory multiprocessors.

Commercial multiprocessors (title only)

No abstract available.

VLSI based design principles for MIMD multiprocessor computers with distributed memory management

Design principles for MIMD multiprocessor computers with virtual memory based on a common, global and uniform logical address space, supporting parallel, procedural languages such as Ada (Ada is a registered trademark of the US Government, AJPO), are discussed. The major design issues are identified and suggested solutions given, the most important of which are distributed, associative address translation, and local mechanisms supporting efficient resource allocation policies to reduce over-all communication costs. Arguments are given for using shared memory and bus-based global communication. Some preliminary studies of bus-based intercommunication schemes, parallel language implementation, capacity simulation and VLSI implementation are reviewed, as well as a number of existing experimental and commercial multiprocessors. Finally an experimental system for evaluation of different mechanisms and policies in systems of the suggested type is outlined.