Commercial Complementary Metal Oxide Semiconductor Research Articles

Subthreshold CMOS transistors are largely immune to magnetic field effects when operated above 11 T

ABSTRACTWe report on measurements of n‐channel field‐effect transistor structures with multiple drain/source contacts, fabricated in a commercial complementary metal‐oxide‐semiconductor (CMOS) technology, at high magnetic field strengths. The focus lies on field dependent effects such as the Hall effect to better understand how these key electronic devices behave when their embedding circuits are immersed in strong magnetic fields. In addition, measurement results of relevant electrical parameters for circuit design, i.e., the saturation current of IDS as well as the slope of IDS and threshold voltage Vt will be shown. The results are in agreement with theory and it is possible to predict the Hall voltage as well as the channel resistance. This allows to simulate noise behavior of amplifiers using silicon MOSFETs in high magnetic fields. The measurements show that, electrically, CMOS transistors operated in subthreshold mode are largely immune to magnetic field effects when operated above 11 T. © 2015 Wiley Periodicals, Inc. Concepts Magn Reson Part B (Magn Reson Engineering) 45B: 97–105, 2015

High-Speed, Radiation-Tolerant Laser Drivers in 0.13 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex></formula>m CMOS Technology for HEP Applications

The gigabit laser driver (GBLD) and low-power GBLD (LpGBLD) are two radiation-tolerant laser drivers designed to drive laser diodes at data rates up to 4.8 Gb/s. They have been designed in the framework of the gigabit-transceiver (GBT) and versatile-link projects to provide fast optical links capable of operation in the radiation environment of future high-luminosity high-energy physics experiments. The GBLD provides laser bias and modulation currents up to 43 mA and 24 mA, respectively. It can thus be used to drive vertical cavity surface emitting laser (VCSEL) and edge-emitting laser diodes. A pre-emphasis circuit, which can provide up to 12 mA in 70 ps pulses, has also been implemented to compensate for high external capacitive loads. The current driving capabilities of the LpGBLD are 2 times smaller that those of the GBLD as it has been optimized to drive VCSELs in order to minimize the power consumption. Both application-specific integrated circuits are designed in 0.13 μm commercial complementary metal-oxide semiconductor technology and are powered by a single 2.5 V supply. The power consumption of the core circuit is 89 mW for the GBLD and 55 mW for the LpGBLD.

Ion traps fabricated in a CMOS foundry

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Nanomechanical switches based on metal-insulator-metal capacitors from a standard complementary-metal-oxide semiconductor technology

We report experimental demonstrations of contact-mode nano-electromechanical switches obtained using a capacitor module based on metal-insulator-metal configuration of a standard commercial complementary metal oxide semiconductor technology. The developed 2 terminals Titanium Nitride switches operate at low voltages (∼10 V) thanks to its small gap (27 nm), showing an excellent ION/IOFF ratio (104) and abrupt behavior (5 mV/decade, one decade of current change is achieved with a 5 mV voltage variation). A switch configuration is also presented where using two electrodes three different contact mode states can be obtained, adding functionalities to mechanical switches configurations.

Radiation effect of deep-submicron metal-oxide-semiconductor field-effect transistor and parasitic transistor

The metal-oxide-semiconductor field-effect transistor (MOSFET) and the parasitic bipolar transistor of domestic complementary metal oxide semiconductor (CMOS) process are irradiated with 60Coγ rays to investigate the failure mechanism of the mixed-signal ICs fabricated by deep submicron CMOS process, caused by total dose radiation. The research results are as follows. 1) The parasitic sidewall and top corner regions contribute to the intra-device leakage. 2) The parasitic bipolar transistor of CMOS process is not sensitive to total dose radiation, which is very different from the conventional bipolar transistor. Preliminary analysis suggests that the difference originates from the differences in the structural and making process. 3) The total dose radiation damage to the parasitic bipolar transistors is not coupled with the damage to the NMOS transistor in the same CMOS process. 4) Based on the above study, the radiation failure mechanisms of the analog and digital module in mixed-signal ICs fabricated respectively by the domestic and commercial CMOS process are investigated. Preliminary analysis suggests that the increase of off-leakage current of MOSFET is responsible mainly for the increase in power consumption of digital module, and the insensitivity of bandgap voltage reference to total dose radiation originates from the radiation resistance of the parasitic bipolar transistor which is the important part of bandgap voltage reference in CMOS mixed-signal ICs.

Nonblocking 4×4 silicon electro-optic switch matrix with push–pull drive

A compact rearrangeable nonblocking 4×4 silicon electro-optic switch matrix based on a Spanke-Beneš network is proposed and fabricated by a 0.18 μm standard commercial complementary metal-oxide semiconductor line. By respectively modulating the two modulation arms with a push-pull drive, a cross talk (CT) of less than -18 dB is obtained for the switching element with 150-μm-long modulation arms. The total steady-state power consumption of the switch matrix ranges from 4.46 to 35.92 mW for different routing states. The CT values of the routing state with the minimum and maximum power consumptions are less than -19 dB and less than -12 dB, respectively.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal–oxide–semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Energy Harvesting Thermoelectric Generators Manufactured Using the Complementary Metal Oxide Semiconductor Process

This paper presents the fabrication and characterization of energy harvesting thermoelectric micro generators using the commercial complementary metal oxide semiconductor (CMOS) process. The micro generator consists of 33 thermocouples in series. Thermocouple materials are p-type and n-type polysilicon since they have a large Seebeck coefficient difference. The output power of the micro generator depends on the temperature difference in the hot and cold parts of the thermocouples. In order to increase this temperature difference, the hot part of the thermocouples is suspended to reduce heat-sinking. The micro generator needs a post-CMOS process to release the suspended structures of hot part, which the post-process includes an anisotropic dry etching to etch the sacrificial oxide layer and an isotropic dry etching to remove the silicon substrate. Experiments show that the output power of the micro generator is 9.4 μW at a temperature difference of 15 K.

Passive Photonics in an Unmodified CMOS Technology With No Post-Processing Required

Passive photonic components consisting of sub-micrometer waveguides, grating couplers, and ring resonators are demonstrated in an unmodified commercial complementary metal-oxide-semiconductor (CMOS) process. Waveguides demonstrate propagation losses of approximately 1 dB/mm at 1.3-μm wavelengths. Grating couplers achieve better than -5.8-dB coupling efficiencies. Ring resonators exhibit Qs greater than 5000 with extinction ratios of more than 20 dB. Furthermore, due to the utilization of front-end-of-the-line design layers for creating the waveguide cores coupled with a relatively thick buried-oxide layer standard within the process, no post-processing is required at the chip or wafer level to achieve the reported device performance. Hence, for the first time, designers without processing capabilities may design custom CMOS photonic circuits for a broad range of applications. One such application which may appropriately leverage the low-cost platform could be disposable bio-photonic sensor arrays.

Smart Flow Sensor With On-Chip CMOS Interface Performing Offset and Pressure Effect Compensation

A single-chip smart flow sensor based on a thermal principle is presented. The device is fabricated through a commercial complementary metal-oxide-semiconductor (CMOS) process combined with a postprocessing procedure. A configurable electronic interface performing signal reading and nonideality compensation is integrated with the sensing structures on the same chip. The interface implements recently proposed approaches to offset and pressure effect compensation. Detailed experimental results are presented demonstrating correct operation of the proposed microsystem.

Mach–Zehnder-Based Four-Port Switching Module on SOI

In this letter, a Mach-Zehnder-based four-port switching module was designed and fabricated by a 0.8-μm standard commercial complementary metal-oxide semiconductor line. The module is composed of five electro-optic switching elements and can be used to realize nonblocking switching for the duplex interconnection among four ports. The switching elements are electrically driven with a nanosecond response. Full routing functionality of the four-port switching module is demonstrated with crosstalk levels lower than -11.8 dB under a common spectral bandwidth of 40 nm.

Experimental Determination of Stress Distributions Under Electroless Nickel Bumps and Correlation to Numerical Models

This paper presents high-density arrays of 7 × 7 n- and p-type piezoresistive field effect transistor (piezo-FET)-based stress sensors realized with a pitch of 23 μm using a commercial complementary metal-oxide semiconductor (CMOS) technology. The sensor elements make it possible to extract the distribution of the in-plane normal stress difference σxx-σyy and the in-plane shear stress σxy under electroless nickel (eNi) bumps. For the first time, pre-deposition stress caused by openings in the passivation, stress induced by the eNi bump deposition, and stress redistribution during anneals between 50°C and 260°C are presented. Typical values of σxx-σyy of ±25 MPa are introduced by bump deposition. These values are further increased by up to 160% during anneals up to 260°C. The in situ monitoring of the mechanical stress redistribution during annealing and thermal cycling is studied. At the deposition temperature, the system is found to be almost stress free. The stress due to bump deposition is numerically modeled. The unknown adhesion strength between nickel bump and silicon nitride (SiN) passivation is taken into account using an adjustable Young's modulus of SiN. For an optimized model, the correlation between measured and simulated spatial stress distributions is found to be high, while the magnitude of the stress values is underestimated in the model by about 35%.

A gain-optimising regulated charge pump

A high-efficiency charge-pump regulator formed by the proposed reconfigurable charge pump is presented in this article. The voltage gain of the reconfigurable charge pump can be adaptively adjusted based on the input voltage and the regulated output voltage. Enhancement of power efficiency is therefore achieved by reducing the conduction loss of the cascaded linear regulator due to the optimised gain of the reconfigurable charge pump. The proposed charge-pump regulator was implemented in commercial complementary metal-oxide semiconductor (CMOS) 0.35 μm technology. The active chip area is 0.46 mm2. The input range is from 1.5 to 3.3 V. The experimental results show that the proposed charge-pump regulator improves the power efficiency by as much as 40% when regulated at 1.2 V.

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

Fabrication of Wireless Micro Pressure Sensor Using the CMOS Process

In this study, we fabricated a wireless micro FET (field effect transistor) pressure sensor based on the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The wireless micro pressure sensor is composed of a FET pressure sensor, an oscillator, an amplifier and an antenna. The oscillator is adopted to generate an ac signal, and the amplifier is used to amplify the sensing signal of the pressure sensor. The antenna is utilized to transmit the output voltage of the pressure sensor to a receiver. The pressure sensor is constructed by 16 sensing cells in parallel. Each sensing cell contains an MOS (metal oxide semiconductor) and a suspended membrane, which the gate of the MOS is the suspended membrane. The post-process employs etchants to etch the sacrificial layers in the pressure sensor for releasing the suspended membranes, and a LPCVD (low pressure chemical vapor deposition) parylene is adopted to seal the etch holes in the pressure. Experimental results show that the pressure sensor has a sensitivity of 0.08 mV/kPa in the pressure range of 0–500 kPa and a wireless transmission distance of 10 cm.

Sheet resistance determination of electrically symmetric planar four-terminal devices with extended contacts

This paper reports an analytic method to determine the sheet resistance Rsq of symmetric planar four-terminal devices based on resistance measurements. Using the technique of conformal mapping it is first shown that any such device is electrically equivalent to a corresponding symmetric unit disk with the same Rsq and invariant under rotations by 90°. Two independent resistances measurable on these devices are expressed analytically as a function of Rsq and of the contact opening angle α. These two resistances fully characterize the electrical properties of such planar conductive devices. A simple procedure to extract both α and Rsq from the resistance values is then presented. These findings are corroborated by the experimental characterization of four-contact devices of ten different geometries fabricated using a commercial complementary metal oxide semiconductor process. From these widely different devices, the sheet resistance of a n-well is extracted to be 1042Ω with a relative uncertainty of only 0.45%.

A 50 GHz Divide-by-4 Injection Lock Frequency Divider Using Matching Method

A fully integrated divide-by-4 frequency divider has been designed, fabricated, and measured in the standard bulk 0.18-m complementary metal-oxide semiconductor (CMOS) technology. A newly proposed matching technique was used to eliminate the unwanted low frequency mixing terms at the common node of the circuit so as to achieve a high division ratio of 4. The frequency divider exhibits a measured operation range of 5 GHz from 45.9 to 50.9 GHz. It consumes a dc power of 7.56 mW at a 1.2 V supply in the steady state operation. The phase noise of the free running divider is 88.51 dBc/Hz at 1 MHz offset and the locked divider is 110.74 dBc/Hz at 1 MHz offset. The chip size is only 0.35 mm 0.5 mm including the pad frame. To our knowledge, this divider has the highest operation frequency to date among the high division ratio injection-lock type frequency dividers in commercial CMOS 0.18-m process.

A Polarization Beam Splitter for Optical Telecommunications Based on Two-Dimensional Metallic Photonic Crystal Structures

We proposed a novel method of constructing a chip polarization beam splitter (PBS) based on two-dimensional metallic photonic crystal (2D-MPC) structures that can be realized using the industrial-based semiconductor IC Cu-interconnect technology. The performance of such a PBS at wavelengths for optical telecommunications is evaluated by the finite-difference-time-domain (FDTD) simulation method. This 2D-MPC PBS device uses three rows of one-dimensional (1D) arrays (3×N-MPC-2D-MPC) as a basic building block to construct the PBS. Using this architecture, the incoming transverse magnetic (TM) and transverse electric (TE) waves can be splitted with very high splitting efficiency (polarization ratio over 1000 for both the TM and TE modes). The implication of our scheme is that the fabrication of such a 2D-MPC PBS is totally compatible with current commercial complementary metal oxide semiconductor (CMOS) fabrication technology. This makes it a ready-to-use technology for the fabrication of a chip-base 2D-MPC PBS.

A miniature Q-band low noise amplifier using 0.13-μm CMOS technology

A miniature Q-band low noise amplifier (LNA) using 0.13-μm standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.

Fabrication of a Micromachined Tunable Capacitor Using the Complementary Metal–Oxide–Semiconductor Post-Process of Etching Metal Layers

In this study, we investigate the fabrication of a micromechanical tunable capacitor using the commercial complementary metal–oxide–semiconductor (CMOS) process and the post-process of maskless wet etching metal layers. The post-process has merits of easy execution and low cost. The post-process uses two etchants to etch the metal layers to release the suspended structures of the tunable capacitor. The comb-drive actuator is employed to change the position of the movable plate in the parallel capacitor, such that the overlap area between the two plates in the parallel capacitor is changed. The experimental results show a capacitance of 3.5 pF and a tuning range of 3.5:1 at 20 V.