Commercial CMOS Technology Research Articles

Utilizing layout effects for analog logic locking

While numerous obfuscation techniques are available for securing digital assets in the digital domain, there has been a notable lack of focus on protecting intellectual property (IP) in the analog domain. This is primarily due to the relatively smaller footprint of analog components within an integrated circuit (IC), with the majority of the surface dedicated to digital elements. However, despite their smaller nature, analog components are highly valuable IP and warrant effective protection. In this paper, we present a groundbreaking method for safeguarding analog IP by harnessing layout-based effects that are typically considered undesirable in IC design. Specifically, we exploit the impact of length of oxide diffusion and well proximity effect on transistors to fine-tune critical parameters such as transconductance (gm\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$g_{m}$$\\end{document}) and threshold voltage (Vth\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_{th}$$\\end{document}). These parameters remain concealed behind key inputs, akin to the logic locking approach employed in digital ICs. Our research explores the application of layout-based effects in two commercial CMOS technologies, namely a 28 nm and a 65 nm node. To demonstrate the efficacy of our proposed technique, we implement it for locking an operational transconductance amplifier. Extensive simulations are performed, evaluating the obfuscation strength by applying a large number of key sets (over 50,000 and 300,000). The results exhibit a significant degradation in performance metrics, such as open-loop gain (up to 130 dB), phase margin (up to 50∘\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$^\\circ $$\\end{document}), 3 dB bandwidth (approximately 2.5 MHz), and power consumption (around 1 mW) when incorrect keys are employed. Our findings highlight the advantages of our approach as well as the associated overhead.

A 5.12-Gbps serializer circuit for front-end fast readout electronics of silicon pixelated detectors

Advanced synchrotron radiation sources are major facilities for analyzing the formation and evolution of material structure in multidisciplinary research, owing to their high luminosity, low emittance, wide energy bandwidth and other characteristics. In China, several advanced synchrotron radiation sources are under construction, including the HEPS (High Energy Photon Source) and SHINE (Shanghai high repetition rate X-ray Free Electron Laser and extreme light facility). These facilities are poised to become major multidisciplinary research platforms in China. To meet the requirements of pixel detectors in these facilities, dedicated pixel readout chips are being developed, including HEPS-BPIX and HYLITE. This paper presents a high-speed serializer circuit developed in a commercial 130-nm CMOS technology for the full-scale (128 × 128) pixel readout chip of HYLITE, which requires a data rate of 4 Gbps currently. The serializer consists of a 16-to-1 binary-tree multiplexer, a ring-oscillating-based phase-locked loop (RO-PLL) and a current-mode logic driving stage with a multi-stage pre-amplifier. Test results demonstrate its expected functionality within a wide operating range from 0.52 Gbps to 5.5 Gbps. At 5.12 Gbps, the measured jitter values are about 2 ps for random jitter, 20 ps for deterministic jitter, and 47 ps for total jitter with a 10−12 bit error rate. Additionally, the horizontal and vertical eye openings are 0.84 UI and 72%, respectively. These positive results indicate that the serializer meets the requirements of HYLITE.

A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4–8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4–100 MHz) with a $2^{31}-1$ pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of $10^{-12}$ .

Experimental demonstration of coupled differential oscillator networks for versatile applications.

Oscillatory neural networks (ONNs) exhibit a high potential for energy-efficient computing. In ONNs, neurons are implemented with oscillators and synapses with resistive and/or capacitive coupling between pairs of oscillators. Computing is carried out on the basis of the rich, complex, non-linear synchronization dynamics of a system of coupled oscillators. The exploited synchronization phenomena in ONNs are an example of fully parallel collective computing. A fast system's convergence to stable states, which correspond to the desired processed information, enables an energy-efficient solution if small area and low-power oscillators are used, specifically when they are built on the basis of the hysteresis exhibited by phase-transition materials such as VO2. In recent years, there have been numerous studies on ONNs using VO2. Most of them report simulation results. Although in some cases experimental results are also shown, they do not implement the design techniques that other works on electrical simulations report that allow to improve the behavior of the ONNs. Experimental validation of these approaches is necessary. Therefore, in this study, we describe an ONN realized in a commercial CMOS technology in which the oscillators are built using a circuit that we have developed to emulate the VO2 device. The purpose is to be able to study in-depth the synchronization dynamics of relaxation oscillators similar to those that can be performed with VO2 devices. The fabricated circuit is very flexible. It allows programming the synapses to implement different ONNs, calibrating the frequency of the oscillators, or controlling their initialization. It uses differential oscillators and resistive synapses, equivalent to the use of memristors. In this article, the designed and fabricated circuits are described in detail, and experimental results are shown. Specifically, its satisfactory operation as an associative memory is demonstrated. The experiments carried out allow us to conclude that the ONN must be operated according to the type of computational task to be solved, and guidelines are extracted in this regard.

Metal Microelectromechanical Resonator Exhibiting Fast Human Activity Detection.

This work presents a MEMS resonator used as an ultra-high resolution water vapor sensor (humidity sensing) to detect human activity through finger movement as a demonstrator example. This microelectromechanical resonator is designed as a clamped-clamped beam fabricated using the top metal layer of a commercial CMOS technology (0.35 μm CMOS-AMS) and monolithically integrated with conditioning and readout circuitry. Sensing is performed through the resonance frequency change due to the addition of water onto the clamped-clamped beam coming from the moisture created by the evaporation of water in the human body. The sensitivity and high-speed response to the addition of water onto the metal bridge, as well as the quick dewetting of the surface, make it suitable for low-power human activity sensing.

Characterization and compact modeling of short channel MOSFETs at cryogenic temperatures

This paper presents an overall characterization, physics-based device analysis, and compact modeling of a commercial 110nm bulk CMOS technology. I−V measurements and DC parameters extraction are performed on low threshold voltage (low VTH, LVT) and regular VTH (RVT) devices with various geometry dimensions from 300 K to 6 K. Different levels of improvement of subthreshold swing (SS), OFF-state current (IOFF), and mobility indicates the potential to optimize the performance of circuits at cryogenic temperatures. However, the temperature characteristics of the mobility and series resistance show a great dependence on the channel length of the devices, which complicates the calculation of the ON-state current at cryogenic temperatures. Moreover, VTH roll-off caused by short channel effect (SCE) get worse, which can be attributed to the increased bulk Fermi potential (ϕf). These channel-length-related effects add extra challenges to the design of cryogenic circuits. An optimized compact model based on BSIM4 is proposed to capture the device characteristics at 6 K, which can produce accurate simulation results only through parameter configuration rather than model equation modification and has been applied to the design of cryogenic CMOS circuits.

SEE and TID characterization of an 8 Gbps SST transmitter in a 28 nm bulk CMOS technology

Single-event effect (SEE) and total ionizing dose effect (TID) characterization of an 8 Gbps transmitter is investigated in the heavy ion and Co60 experiments. Source-series-terminated (SST) transmitter with T-coil and 3-tap feed-forward equalization (FFE) is adopted in the design and fabricated in a 28 nm commercial bulk CMOS technology. Single-event transient (SET) and single-event function interruption (SEFI) were observed in the heavy ion experiment, but the deterministic jitter (DJ) and random jitter (RJ) of the eye diagram were almost unchanged after 1.2 Mrad(Si) Co60 irradiation. The experimental results indicate that SEE is significant in the transmitter, and SET and SEFI need to be mitigated. While the TID effects are almost negligible, showing minor changes in the deterministic jitter. The most sensitive regions of SEEs are further identified by the pulsed laser experiment for the transmitter, which provides useful information for SEE-hardened design.

Photodiode-body-biased MOSFET with adjustable gain from 1 to 106 and wide dynamic range over 160 dB, enabling optical measurement applications

Optical sensors have been found in numerous measurement applications for scientific instrumentation and spectrometers. To achieve a high gain, devices such as photomultiplier tubes (PMTs), avalanche photodiodes (APDs), and phototransistors are commonly used. PMTs with high gain of >105 are bulky and have high power consumption. Compact APDs tend to have high shot noise and strong temperature dependence. Phototransistors taking advantage of current amplification of bipolar junction transistors (BJTs), on the other hand, do not require high electric field to attain a gain of 10–100. Here, this work addresses a new optical sensor design with an adjustable gain from 1 to 106 and a wide dynamic range over 160 dB. The sensor is based on light-modulated body-bias effect and can be manufactured by commercial CMOS technology.

Charge Collection Dynamics of the ARCADIA Passive Pixel Arrays: Laser Characterization and TCAD Modeling

Monolithic Active Pixel Sensors (MAPS) represent one of the most promising technologies for the next generation of radiation detectors. The ARCADIA project aims at the development of Fully Depleted (FD) MAPS employing a production process compatible with a 110 nm commercial CMOS technology. The first engineering run of the project included matrices of active pixels with embedded analog and digital frontend electronics and passive test structures such as passive pixel arrays, MOS capacitors and backside diodes. Although the produced samples were already characterized from the electrical point of view, a thorough study of the charge collection dynamics of the passive pixel arrays was still missing. In this paper we show the results of the dynamic characterization of a group of passive pixel arrays with different pixel pitches (50, 25 and 10 μm) and different pixel layouts. The tested samples have been illuminated from the backside with an infrared and a red laser with wavelengths equal to 1,060 nm and 660 nm, respectively. The pixel arrays have been mounted on a custom readout PCB connected to an external amplifier with 1 GHz bandwidth and the signals have been acquired through a fast digital oscilloscope. We employed both focused and unfocused laser spots to evaluate the change in the measured signal as a function of the laser spot position and the average response of the pixel arrays. An excellent agreement has been demonstrated by comparing the measured signals with the results of transient TCAD simulations and a time for 50% charge collection of 7.8, 4.2 and 2.6 ns has been predicted and experimentally validated in pixels with 50, 25 and 10 μm pitch, respectively.

Design and Applications of Integrated Transducers in Commercial CMOS Technology

Monolithic integration of Microelectromechanical Systems (MEMS) directly within CMOS technology offers enhanced functionality for integrated circuits (IC) and the potential improvement of system-level performance for MEMS devices in close proximity to biasing and sense circuits. While the bulk of CMOS-MEMS solutions involve post-processing of CMOS chips to define freely-suspended MEMS structures, there are key applications and conditions under which a solid, unreleased acoustic structure composed of the CMOS stack is preferred. Unreleased CMOS-MEMS devices benefit from lower barrier-to-entry with no post-processing of the CMOS chip, simplified packaging, robustness under acceleration and shock, stress gradient insensitivity, and opportunities for frequency scaling. This paper provides a review of advances in unreleased CMOS-MEMS devices over the past decade, with focus on dispersion engineering of guided waves in CMOS, acoustic confinement, CMOS-MEMS transducers, and large signal modeling. We discuss performance limits with standard capacitive transduction, with emphasis on performance boost with emerging CMOS materials including ferroelectrics under development for memory.

CMOS-MEMS Thermal-Piezoresistive Resonators and Oscillators for Sensors

Microelectromechanical systems (MEMS) are in widespread commercial use due to their compact size, high performance, and low cost. MEMS resonators have emerged as front runners for sensing (accelerometers, gyroscopes, and particulate matter) and frequency (RF front-end, filters, timing, and frequency source) applications. The excellent stability, resolution, and accuracy of resonators lead them an ideal candidate for sensor implementation. The CMOS-MEMS technology allows for rapid, large-scale, and low-cost manufacturing. Thermal–piezoresistive resonators (TPRs) are promising candidates due to their favorable potential with scaling and robust performance in the ambient environment. A detailed finite element method (FEM) simulation flow is presented along with a mathematical model for device optimization. The devices were fabricated with the commercial CMOS technology utilizing the front-end-of-line (FEOL) polysilicon and back-end-of-line (BEOL) materials like silicon dioxide and interconnect metal. The flexibility of selective material placement in layout and complex routing using multi-metal interconnect is employed to develop a balanced TPR design at 2 MHz. A 5-MHz bulk mode TPR was designed for mass sensing application. The fabricated devices were characterized, and their performance is compared with other state-of-the-art works. Finally, the developed devices were used in real-world applications for mass sensing and pressure sensing. The device achieved 20 kHz/ng. The TPR devices combine principles of Pirani gauge and resonant sensors for improving the sensing range from 2 to 760 Torr (1 atm).

ASET and TID Characterization of a Radiation Hardened Bandgap Voltage Reference in a 28-nm Bulk CMOS Technology

Analog single-event transient (ASET) and total ionizing dose (TID) characterization of a radiation-hardened bandgap voltage reference (BGR) is investigated in a 28-nm commercial bulk CMOS technology. Different radiation hardened by design (RHBD) techniques are used for ASET mitigation in the circuit and layout, and the circuit is optimized to ensure the BGR can still work correctly even using fast nMOS and slow pMOS for TID mitigation. Heavy-ion (linear energy transfer (LET) = 76.3 MeV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg) experiments show the maximum amplitude of positive (negative) ASET is just 30 mV (90 mV), and Co <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> gamma-ray experiments show the maximum output voltage reduction is just 37 mV after 1.2 Mrad(Si) irradiation, and the final output voltage reduction is just 11 mV after 48 h of annealing. All of the experiments indicate that ASET is significantly mitigated by the RHBD techniques, and the BGR has naturally good TID response due to the design margin. The investigation also indicates that the proposed BGR is a good substitute for space application due to the excellent ASET and TID tolerance capability.

Cryogenic Characterization and Analysis of Nanoscale SOI FETs Using a Virtual Source Model

This article reports the temperature-dependent characterization and analysis of quasi-ballistic transport in fully depleted silicon-on-insulator (FD-SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) from a 22-nm commercial CMOS technology. Measurements of current–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> ) characteristics for temperatures ranging from 10 up to 300 K are presented in this article. Key electrical parameters are extracted as a function of temperature, including threshold voltage, subthreshold swing, ON-state current, series resistance, mobility, mean free path, and ballistic ratio. An experimentally validated virtual source modeling approach that incorporates back-gate biasing is presented in this article for temperatures down to 10 K. A comparison with bulk devices reveals less reduction in ballisticity at low temperatures and is attributed to a smaller contribution from ionized impurity scattering due to lower doping in the fully depleted (FD) channel.

Development of a serial link transmitter for monolithic active pixel sensors

In this paper, a 5-Gbps serial link transmitter has been designed for monolithic active pixel sensor. The serial link is designed in a commercial 130-nm CMOS technology with a power supply of 1.2 V. The transmitter consists of a 16b/20b encoder, a three-stage 20:1 serializer core, the CML driver with pre-emphasis function, and a high-speed receiver to deal with the external clock. The root mean square jitter of this serial link transmitter is 2.2 ps, indicating a bit error rate of 1 × 10−14. This paper will discuss the design and performance of this serial link transmitter.

Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs

This brief presents a general technique for achieving the highest possible RO oscillation frequency accompanied by lower phase noise in an enhanced circuit design utilizing novel delay cells. The circuit architecture has the delay cells’ inputs separated by an optimized skew offset. Skew-offset optimization is attained by integrating a pre-charge/discharge auxiliary feed-forward loop into the separately driven delay cells. This technique reduces the transition time when Supply and GND are simultaneously connected/disconnected to the delay cell’s output node. When these delay cells are connected in loops to form a Ring Oscillator, they provide high performance, even/odd multi-phase signals. The proposed methodology is validated in commercial 65nm and 180nm CMOS technologies. The post-layout simulations show that the proposed designs improve the performance by modulating the delay cell output node’s charging and discharging. The operating frequency of the proposed design, e.g., for odd stage 5/7 and even stage 4/8/16 stage, is almost 50%/40%, (80%/30%/20%) higher than that of the MSSRO (Multi-Loop Skew based Single-ended Ring Oscillator) with the same number of stages. Additionally, the designs proposed for the targeted phase noise and center frequency consume around 8–20% (odd stages)/ (6–28%) (Even stages) lesser power, a lower supply sensitivity up to 9%, and lower PVT variability up to 6% compared to its equivalent stages MSSRO (3-stages single-ended RO) counterparts in 180 nm CMOS Technology.

Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS

This article describes a previously unreported single-event radiation effect in spiral inductors manufactured in a commercial CMOS technology when subjected to ionizing radiation. Inductors play a major role as the component determining the frequency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> tank oscillators, which is why any radiation effect in these passive components can have a detrimental impact on the performance of clock generation circuits. Different experiments performed to localize and characterize the single-event effect (SEE) response in a radiation-hardened PLL circuit are discussed and presented together with a hypothesis for the underlying physical mechanism.

Low-Noise Analog Channel for the Readout of the Si(Li) Detector of the GAPS Experiment

This work is focused on the design and the experimental characterization of an analog channel developed for the readout of lithium-drifted silicon detectors of the General AntiParticle Spectrometer (GAPS) experiment aimed at the search for dark matter. The instrument is designed for the identification of antideuteron particles from cosmic rays during an Antarctic balloon mission scheduled for late 2022. A low-noise analog front-end, featuring a dynamic signal compression to comply with the wide input range, has been designed in commercial 180-nm CMOS technology. The channel was fabricated in 2018 and is the first building block toward the development of a multichannel readout ASIC. The article will provide a description of the design criteria, the architecture of the channel, and a summary of the results of the experimental characterization.

Cryogenic characterization and modeling of a CMOS floating-gate device for quantum control hardware

We perform the characterization and modeling of a floating-gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and flexible cryogenic system for qubits control in large-scale quantum computers. The device stores onto a floating-gate node a non-volatile charge, which can be bidirectionally modified by Fowler-Nordheim tunneling and impact-ionized hot-electron injection. These two injection mechanisms are characterized and modelled in compact equations both at 300 K and 15 K. At cryogenic temperature, we show a fine-tuning of the stored charge compatible with the operation of a precise analog memory. Moreover, we developed accurate simulation models of the proposed floating-gate device that set the stage for designing a programmable analog circuit with better performances and accuracy at a few Kelvin. This work offers a solution in the design of configurable analog electronics to be employed for accurately read out the qubit state at deep-cryogenic temperature.

Wideband Modeling of CMOS Schottky Barrier Diode Detectors for THz Radiometry

A complete system modeling and characterization of a wideband differential terahertz (THz) direct detector, integrated in a commercial CMOS technology, is presented. The detector consists of a recently developed double leaky-slot lens antenna that operates from 200 to 600 GHz in combination with a differential Schottky barrier diode (SBD) direct detection circuit. The proposed methodology, starting from low-frequency measurements on a standalone SBD, is able to adequately model the spectral radiometric performance. The system noise-equivalent power (NEP) is characterized from 325 to 500 GHz in excellent agreement with the proposed system model. The measured NEP, 20 pW/√Hz minimum and 90 pW/√Hz frequency averaged, is compromised with respect to the average NEP of 2.7 pW/√Hz that was initially predicted by simulations using the process design kit (PDK) model, since the available SBDs are operating beyond their cutoff frequency. The diodes and models provided by the PDK proved to be inaccurate in predicting circuit behavior at these high frequencies. By using the proposed analysis and modeling approaches, an accurate wideband antenna-detector codesign could be applied for future passive THz imaging applications based on CMOS technologies.

Mitigation Technique for Single Event Transient via Pulse Quenching

With the technology scaling down, the single event transients produced in the combinational circuit lead to an increasing threat to reliability. In this paper, Dummy Gate Enhanced Charge Sharing (DGECS) technique is proposed to mitigate single event transients, and enhances the pulse quenching of logic cells by increasing the charge sharing between key transistors. Mixed-mode 3-D technology computer aided design simulations were carried out with commercial 65nm dual-well CMOS technology. The simulation results show that the proposed layout technique can significantly reduce single event transient pulse widths and even completely quench transient pulses.