Combinational Logic Circuits Research Articles

Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

Due to the reduction in device feature size and supply voltage, achieving soft error reliability in sub-micrometer digital circuits is becoming extremely challenging. We consider the problem of choosing the gate sizes in a combinational logic circuit in order to minimize the soft error rate (SER) of the circuit. This problem can be solved using the heuristic as well as the greedy-based approaches for small-size problems; however, when the circuit size increases, the computational time grows exponentially, and hence, the previous methods become impractical. This paper proposes a novel technique for soft error tolerant design of large-scale combinational circuits using a cone-oriented gate sizing. Circuit partitioning is used to split the circuit into a set of small sub-circuits. The gates of sub-circuits are resized, such that the entire circuit SER is reduced based on a new soft error descriptor metric. The proposed cone-oriented gate sizing framework is used for selective gate sizing, leading up to 31% SER reduction with less than 17% area overhead when applied to large-scale benchmarks. The results also show that the proposed method is 21% more efficient and up to 292 times faster when compared with that obtained using a similar work based on the sensitive-based gate sizing scheme.

Efficient reliability evaluation of combinational and sequential logic circuits

Reliability has become one of the major goals for designs based on emerging technologies. Therefore, reliability evaluation should be included in the design flow of logic integrated circuits. In this paper, a probability transfer matrix-based method is developed for reliability evaluation of combinational and sequential logic circuits. The proposed method for combinational circuits is based on correct and incorrect probabilities for the binary logic values (0 and 1) of the nodes of the circuit. In this method, the reconvergent fanouts problem is handled using the concept of correlation coefficients. The reliability evaluation of sequential logic circuits is carried out by first breaking the loops, followed by iterative application of the combinational method on the converted circuit. The accuracy and scalability of the proposed methods are proved by various simulations on ISCAS 85 and LGSynth91 benchmark circuits for the combinational method and on ISCAS 89 benchmark circuits for the sequential method. The results show less than 2 % average error for reliability estimation compared with Monte Carlo (MC) simulations, outperforming state-of-the-art methods in terms of reliability estimation and algorithm runtime.

A 5\u2032-BODIPY End-label for Monitoring DNA Duplex-Quadruplex Exchange

Fluorescent probes that can distinguish different DNA topologies through changes in optical readout are sought after for DNA-based diagnostics. In this work, the 4,4-difluoro-4-bora-3a, 4a-diaza-s-indacene (BODIPY) chromophore attached to cyanophenyl substituents (BODIPY-CN) has been tethered to the 5′-end of the 15-mer thrombin binding aptamer (TBA) that contains the guanine (G) nucleobase. TBA folds into a unimolecular antiparallel G-quadruplex (GQ) upon binding thrombin and certain metal ions. The 5′-BODIPY-CN-TBA sample possesses a Stokes shift of ~40 nm with wavelengths of excitation/emission at 550/590 nm and exhibits a 2-fold increase in emission intensity compared to the free BODIPY-CN in aqueous buffer that possesses a brightness (εΦfl) of ~16,956 M−1. cm−1. However, when 5′-BODIPY-CN-TBA is base-paired to a complementary strand in the B-form duplex, the emission of the BODIPY-CN end-label increases 7-fold, 14-fold compared to the free-dye. This signal-on response enables the BODIPY-CN end-label to serve as a quencher-free fluorescent probe for monitoring duplex-GQ exchange. The visible end-label minimally perturbs GQ stability and thrombin binding affinity, and the modified TBA can act as a combinatorial logic circuit having INHIBIT logic functions. These attributes make BODIPY-CN a highly useful end-label for creating nanomolecular devices derived from G-rich oligonucleotides.

Angular dependency on heavy-ion-induced single-event multiple transients (SEMT) in 65 nm twin-well and triple-well CMOS technology

The extreme reduction in minimum transistor-to-transistor spacing has resulted in multiple transistors being often affected by a single ion strike. The charge sharing becomes a prevalent phenomenon, and it usually brings about single-event multiple transients (SEMT) in combinational logic circuits. In this paper, the angular dependency of heavy-ion-induced SEMT is characterized in heavy-ion experiments. We find that angular heavy-ion incidence can induce single-event five transients in 65 nm bulk CMOS technology. Moreover, the characteristics of SEMT are different in twin-well and triple-well technology.

Dynamic control of endogenous metabolism with combinatorial logic circuits

Controlling gene expression during a bioprocess enables real‐time metabolic control, coordinated cellular responses, and staging order‐of‐operations. Achieving this with small molecule inducers is impractical at scale and dynamic circuits are difficult to design. Here, we show that the same set of sensors can be integrated by different combinatorial logic circuits to vary when genes are turned on and off during growth. Three Escherichia coli sensors that respond to the consumption of feedstock (glucose), dissolved oxygen, and by‐product accumulation (acetate) are constructed and optimized. By integrating these sensors, logic circuits implement temporal control over an 18‐h period. The circuit outputs are used to regulate endogenous enzymes at the transcriptional and post‐translational level using CRISPRi and targeted proteolysis, respectively. As a demonstration, two circuits are designed to control acetate production by matching their dynamics to when endogenous genes are expressed (pta or poxB) and respond by turning off the corresponding gene. This work demonstrates how simple circuits can be implemented to enable customizable dynamic gene regulation.

Особенности организации систем функционального контроля комбинационных схем на основе полиномиальных кодов

Objective: To study the specificities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking circuits of concurrent error detection systems, were pointed out. Particularly, one of such essential properties is the presence of a constant term in a generator polynomial (otherwise, all the required test patterns are not generated for a complete check of a coding device). An example of concurrent error detection sys- tem implementation for a combinational circuit was given. Some experimental data on error detection in LGSynth’89 combinational benchmarks were described. Practical importance: The use of polynomial codes for combinational circuit control makes it possible to synthesize self-checking discrete devices of automation and computer engineering.

An Incremental Algorithm for Soft Error Rate Estimation of Combinational Circuits

With the scaling of CMOS transistor dimensions, soft errors in combinational logic circuits are emerging as a significant reliability concern in nano-scale digital systems design. Hence, fast and efficient approaches to estimate the soft error rate (SER) of combinational circuits have become significantly important. SER is a crucial diagnostic metric which provides valuable information to guide SER optimization and reliability-driven logic synthesis. Existing works for SER analysis in the literature, however, computes this metric in a non-incremental manner, that is, after one or more changes in a previously timed circuit, it is required to recompute SER from scratch, which is obviously undesirable for optimizing large circuits. In this paper, an incremental technique is presented to estimate the SER of combinational circuits. An accurate model is proposed for SER estimation by considering all three masking mechanisms (namely, logical, electrical, and timing). The proposed incremental re-estimation SER algorithm is based on the information provided by the primary SER calculation. A set of rules, based on the topological locations of logic gates in the circuit graph, is introduced to identify the portion of the design for which the gates SER are affected, and quickly computes the new SER values. Experimental results on ISCAS’89 benchmarks show that, on average, 10 times speedup is achieved during SER re-estimations without sacrificing accuracy.

A novel fluorescent sensor based on a diarylethene containing a hydrazinylpyridine unit for Cd2+ and Zn2+ with high selectivity

A new diarylethene derivative containing a hydrazinylpyridine unit has been synthesized. The diarylethene derivative was highly selective and sensitive to Cd2+ and Zn2+ with significant fluorescence emission and color changes. Moreover, its multi-controllable photochromism and fluorescent switching characters were studied systematically with various stimuli (UV/vis lights and chemicals) in methanol solution. Based on the multi-addressable fluorescent switching characters, a combinational logic circuit was constructed by using the fluorescence emission intensity at 480 nm as output signal, the UV/vis lights, Cd2+, and EDTA as input signals.

A multi-functional fluorescent sensor for Zn2+ and HSO4− based on a new diarylethene derivative

A new photochromic diarylethene derivative with a hydralazine unit was designed and synthesized. It was not only acted as a Zn2+ sensor with the fluorescent color change from dark blue to bright orange, but also acted as a fluorescent sensor for HSO4− with the fluorescent color change from dark blue to bright blue. Furthermore, the derivative also exhibits multi-addressable switching properties by the stimulations of lights and chemical reagents. Based on these characteristics, two combinational logic circuits were constructed with the emission intensity as the output signals, and the UV/vis lights, chemical species as the input signals.

Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.

ASCGP - Automatic System for Construction of Logical Circuits in FPGA using CGP

In this article is introduced a novel framework for the development of an automatic system using a Cartesian Genetic Programming based approach to construct combinational and sequential logic circuits in FPGAs. The paper is comprised of two parts: the first one is based on a hybrid evolutionary algorithm that by means of parameters provided by the user looks for a logical circuit solution, and the second one is a flexible architecture developed in Verilog-HDL language that converts the solution given in the first part into a hardware implementation inside the FPGA. Good results using this hybrid evolutionary approach have been obtained in all the studied cases in relation to others similar studies in the literature. In addition, the generated hardware is able to manage sequential circuits, being this an innovation of the present project in relation to other projects found in the literature, in which almost all of them can only simulate the automatic generation of combinational circuits.

A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits

Usually, important parameters in the design and implementation of combinational logic circuits are the number of gates, transistors, and the levels used in the design of the circuit. In this regard, various evolutionary paradigms with different competency have recently been introduced. However, while being advantageous, evolutionary paradigms also have some limitations including: a) lack of confidence in reaching at the correct answer, b) long convergence time, and c) restriction on the tests performed with higher number of input variables. In this paper, we have implemented a genetic programming approach that given a Boolean function, outputs its equivalent circuit such that the truth table is covered and the minimum number of gates (and to some extent transistors and levels) are used. Furthermore, our implementation improves the aforementioned limitations by: Incorporating a self-repairing feature (improving limitation a); Efficient use of the conceivable coding space of the problem, which virtually brings about a kind of parallelism and improves the convergence time (improving limitation b). Moreover, we have applied our method to solve Boolean functions with higher number of inputs (improving limitation c). These issues are verified through multiple tests and the results are reported.

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Combinational Logic Analysis with Laser Voltage Probing

Abstract This article explains how laser voltage probing (LVP) can be used to analyze combinational logic circuits. The authors describe how the technique is aided by the development and use of a waveform library and a corresponding truth table. They also present a case study in which the new technique is used to isolate faults in a combinational logic circuit consisting of multiple gates.

Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks

The quantum of power consumption in wireless sensor nodes plays a vital role in power management since more number of functional elements are integrated in a smaller space and operated at very high frequencies. In addition, the variations in the power consumption pave the way for power analysis attacks in which the attacker gains control of the secret parameters involved in the cryptographic implementation embedded in the wireless sensor nodes. Hence, a strong countermeasure is required to provide adequate security in these systems. Traditional digital logic gates are used to build the circuits in wireless sensor nodes and the primary reason for its power consumption is the absence of reversibility property in those gates. These irreversible logic gates consume power as heat due to the loss of per bit information. In order to minimize the power consumption and in turn to circumvent the issues related to power analysis attacks, reversible logic gates can be used in wireless sensor nodes. This shifts the focus from power-hungry irreversible gates to potentially powerful circuits based on controllable quantum systems. Reversible logic gates theoretically consume zero power and have accurate quantum circuit model for practical realization such as quantum computers and implementations based on quantum dot cellular automata. One of the key components in wireless sensor nodes is the cryptographic algorithm implementation which is used to secure the information collected by the sensor nodes. In this work, a novel reversible gate design of 128-bit Advanced Encryption Standard (AES) cryptographic algorithm is presented. The complete structure of AES algorithm is designed by using combinational logic circuits and further they are mapped to reversible logic circuits. The proposed architectures make use of Toffoli family of reversible gates. The performance metrics such as gate count and quantum cost of the proposed designs are rigorously analyzed with respect to the existing designs and are properly tabulated. Our proposed reversible design of AES algorithm shows considerable improvements in the performance metrics when compared to existing designs.

All optical programmable logic array (PLA)

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Ternary Electronic Logic Systems Automation: A Novel Study Based on VHDL Language - First Part: Ternary Logic Gates

In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. 
 Keywords: Ternary logic, Ternary logic gates, VHDL language.

Synthesis of a single 1,8-naphthalimide fluorophore as a molecular logic lab for simultaneously detecting of Fe3+, Hg2+ and Cu2+

A novel fluorescence sensing 1,8-naphthalimide fluorophore is synthesized and investigated. The novel probe comprising two different binding moieties is capable to detect selectively Fe3+ over the other representative metal ions as well as a combination of biologically important cations such as Fe3+, Cu2+ and Hg2+ in the physiological range without an interfering effect of the pHs. Due to the remarkable fluorescence changes in the presence of Fe3+, Hg2+ and Cu2+ ions, INH and AND logic gates are executed and the system is able to act as a single output combinatorial logic circuit with three chemical inputs.

Parallel hardware architecture for implementation of high speed MAC

Multiply and accumulation (MAC) is basic function in most of the signal processing applications like video, image processing, pattern recognition. Multipliers corresponding to the MAC unit are designed using combinational logic circuits. Modern computers consist of dedicated MAC unit and multiplication is usually performed using serial hardware which is referred as a unit cell. This MAC unit cell as supported in many architectures fail to meet the real time response for high rate data applications. The rationale of this paper is to propose parallel architecture for multiply and accumulate operation with high throughput rate. The proposed architecture performs the multiplication of operands involved in the MAC unit parallely and accumulates the result. The architecture also enables reusing of hardware for higher order taps based on the reusability factor. The functional units of the proposed architecture are developed at module level using RTL and behavior is simulated in Xilinx ISE 14.1 and synthesized on Virtex 7 family of FPGA. The obtained throughput for 128 taps is 16 MACs per cycle with reusability equal to 1 at clock frequency of 8.33 MHz for precision fixed to 8 bits.

An Empirical Model for Predicting SE Cross Section for Combinational Logic Circuits in Advanced Technologies

At the gigahertz range of frequencies, contribution of combinational logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any combinational logic circuit. Estimated logic SEU cross section matches well with the measured logic SEU cross section. Estimated logic SEU cross section results obtained with the proposed method are within $2\times $ average error when compared to the experimentally measured logic SEU cross section. This method only needs to be calibrated once for use at a given technology node.