Combinational Research Articles

Mental health among B2B salespeople: A morphological analysis

The intensely competitive landscape of B2B selling makes it highly susceptible to mental health issues (MHI) among the salespersons. MHI has a cascading impact on salespersons’ well-being, and ultimately on organizations’ performance and hence needs to be addressed as a priority. Despite a large body of knowledge on MHI in B2B sales, there is a lack of an integrated framework that could structure this knowledge for academic and managerial pursuits. This review addresses this gap by using morphological analysis (MA) to develop a framework that provides a systematic, modular, tabular-visual representation of MHI literature in B2B sales. Drawing on this framework, we develop a conceptual model that delineates key variables and allows their logical mapping and combination. Collectively, the MA framework and the model serve as a useful toolkit for academics and practitioners. They help to cultivate a clearer understanding of the state-of-the-art on MHI in terms of causal factors, manifestations, boundary conditions, coping resources, mitigation strategies, and theoretical orientation. They also facilitate the development of novel, interesting, and complex research questions for further empirical testing. Addressing these questions will contribute to theory building in support of creating and/or refining managerial strategies and organizational policies to address MHI among B2B salespersons more effectively.

DNA Nanolock-Based Logic Gate-Directed Reciprocal Feedback for Stepwise Cell Typing and Combination Treatment.

To achieve accurate molecular diagnosis and early-stage intervention of disease on demand, there is an urgent need for the monitoring of multiple biomarkers and multipath information acquisition in living cells. The DNA combinatorial logic gate is an appropriate strategy for providing a systematic proof of concept with comprehensive information and function. Herein, a modular DNA logic gate nanomachine is designed for sufficient multistep reciprocal cell identification and therapy via the iteration of simple logic operations. In this logic gate system, this main module is constructed by G-quadruplex-locked gold nanocages (AuNCs), serving dual functions of drug encapsulation and cell recognition. The logic system is composed of OR, XNOR, AND, and NOR gates employing two intracellular disease biomarkers (microRNA 21 and microRNA 155) as inputs and the fluorescence signal of doxorubicin (Dox) as an output. The output signals of the four logic gates are iterated to process the imaging analysis data from the complex matrix in the living cell. Via positive and negative reciprocal feedback, the series circuit of different gates enables different functions, including the preliminary screening and the distinction of the cell type. Through the mutual preliminary screening and further proof, this logic system achieves accurate identification of cells, controlled drug release, and photothermal treatment using the AuNC as a photothermal transducer. This DNA logic system broadens the applications of the biocomputing system in disease screening and logic-controlled treatment fields.

Using a discrete global grid system for a scalable, interoperable, and reproducible system of land-use mapping

ABSTRACT An accurate and timely land-use map of an area is a valuable geospatial dataset. Making one requires assembling heterogeneous geospatial input data. This becomes computationally expensive as the number of inputs grow or the combinational classification logic becomes more convoluted. We present as a solution an analytical framework based on a DGGS. This provides a spatial data structure that: facilitates horizontal scaling; improves geospatial data interoperability; and makes classified geospatial data easier to reproduce. We demonstrate a benchmark of land-use assignment with a DGGS against the vector and raster geospatial data models. Significant performance benefits are apparent over the vector case, while performance is equivalent to raster. Yet a DGGS has other compelling benefits that makes it more convenient to use in the domain of land-use assignment than the raster data model.

Engineered Gate-Based Nanoscaled JK Flip-Flop: Design, Simulation and Applications

In this paper, we design and simulate a novel, highly compact and power-efficient silicon-based JK flip-flop (JKFF) employing an engineered gate technique, for the first time. Herein, the pull-down and the pull-up paths used to realize the JKFF have been realized by 4 and 2 engineered gate transistors, respectively (total six), whereas 8 pull-ups and 8 pull-down (total 16) transistors are used to realize the JK flip-flip in the conventional MOS technology. Two-dimensional (2D) calibrated mixed-mode simulations have revealed substantial improvement in various performance measuring parameters of the proposed JK flip-flop. The proposed technique has resulted in a significant reduction of 62.5% in transistor count, [Formula: see text]9.12% in power consumption, 2.5% decrease in delay and 11.38% in power delay product in comparison to the conventional JKFF realization. Further, the proposed gate-engineered JKFF has been used to realize highly compact D and T flip-flops. It has been observed that a 55.5% and 62.5% decrease in transistor count have been achieved in comparison to the conventional MOS-based JKFF realization of D and T flip-flops, respectively. A significant improvement in power consumption, delay, and power delay products has been achieved in the proposed D and T flip-flops in comparison to the conventional JKFF-based D and T flips. It has been observed that notably, the versatility of this approach allows for straightforward adaptation to realize various other sequential and combinational circuits. Besides, the process flow for the fabrication of the proposed engineered gate transistors for realizing the JKFF, D and T flip-flops has also been given.

3D Nano Hafnium‐Based Ferroelectric Memory Vertical Array for High‐Density and High‐Reliability Logic‐In‐Memory Application

AbstractA new type of ferroelectric memory device with high reliability and complementary metal‐oxide‐semiconductor (CMOS) compatibility characteristics is an important condition for achieving integrated memory and computing chips. Here, 3D stacked ferroelectric memory devices based on ferroelectric materials of HfO2 are fabricated. The device exhibits high speed (50 ns), low read voltage (0.5 V), and great reliability with no substantial degradation after 1010 cycles and a 10‐years data retention at 85 °C. The IMP and NAND logic are achieved with stable memory window (>200 mV) across the vertical devices’ interconnection. On this basis, combining with the traditional CMOS logic device, multiple combination logic functions containing NOT, AND, and NOR are achieved by simulation. The collaboration of devices in the vertical direction providing the possibility of combining multi‐bit logic in memory functions and paves the way for the implementation of high‐density, high‐reliability, and low‐energy consumption computing‐in‐memory chips compatible with the CMOS technology.

Institutional Complexity and Social Innovation: The Case of Chinese Social Enterprises

Abstract Social enterprises (SEs) have emerged throughout the world to address societal challenges through market-based activities and innovation. Research has focused on how SEs manage the tensions arising from the combination of social-welfare and market logics, neglecting the institutional complexity that arises in authoritarian regimes where the state plays a dominant role. Based on the institutional logics perspective and interview data of 42 SE leaders in China, we find that key tensions arise from the state and social-welfare logics and that state logic (re)configures the social–market relationships to be compatible. Chinese SEs employed depoliticization and localization to adapt to this unique form of institutional complexity in their social innovation efforts. This study advances research on SEs, institutional complexity, and hybrid organizing.

The combinatorics of Farey words and their traces

We introduce a family of 3 -variable ‘Farey polynomials’ that are closely connected with the geometry and topology of 3 -manifolds and orbifolds as they can be used to produce concrete realisations of the boundaries and local coordinates for one-dimensional (over \mathbb{C} ) deformation spaces of Kleinian groups. As such, this family of polynomials has a number of quite remarkable properties. We study these polynomials from an abstract combinatorial viewpoint, including a recursive definition extending that which is known in the literature for the special case of manifolds, even beyond what the geometry predicts. We also present some intriguing examples and conjectures which we would like to bring to the attention of researchers interested in algebraic combinatorics and hypergeometric functions. The results in this paper additionally provide a practical approach to various classification problems for rank 2 subgroups of \operatorname{PSL}(2,\mathbb{C}) since they, together with other recent work of the authors, make it possible to provide certificates that certain groups are discrete and free, and effective ways to identify relators.

Analyzing Multilayer Graphene Nanoribbon‐Based Via‐Interconnect Scheme: Prospects and Challenges for Monolithic 3D Integrated Circuits

This article presents a multilayer graphene nanoribbon (MLGNR)‐based single‐tier on‐chip nanoscale via‐interconnect scheme (VIS), which combines the vertical MLGNR via and horizontal MLGNR interconnect, as a prospect for monolithic 3D (M‐3D) integrated circuits (ICs). To go beyond the simplifying assumptions of perfect MLGNR and conventional skin‐effect, this study incorporates the impact of edge‐ and substrate‐induced scatterers in a realistic MLGNR and considers the 1D skin depth formula for MLGNR‐based on‐chip interconnect and via. A combined equivalent circuit model is developed to analyze the challenges induced by scatterers, skin‐effect, and crosstalk effect in perfect MLGNR VIS (P‐VIS) and realistic MLGNR VIS (R‐VIS). The results show that for width in the range of 5–30 nm, P‐VIS outperforms R‐VIS in terms of crosstalk delay. Moreover, at high frequencies ranging from 1 to 104 GHz with a width of 16 nm, R‐VIS demonstrates a performance decline of 243.18% (5.3934 × 103%) for L = 4.8 μm (1 mm), respectively, in comparison with P‐VIS. Hence, in order to leverage the potential of MLGNR‐based VIS for M‐3D ICs at high frequencies, it is imperative to integrate Li‐intercalation doping and mitigate the impact of edge and substrate scatterers in MLGNR.

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection

UV LED Printing Device for PCB Fabrication

Photolithography is commonly used to fabricate printed circuit boards (PCBs) in micromanufacturing. It involves UV exposure to pattern portions of a thin film of a substrate before a geometric design is transferred from a photo mask to a light-sensitive substance (photoresist) on the substrate using light. Conventionally, metal halide lamps and UV fluorescent bulbs make up most of the exposure systems during photolithography. However, both systems are highly costly in educational establishments and consume high electrical energy. Moreover, they also have too broad UV radiation and are not appropriate for the sizes of PCBs that need to be mounted on the apparatus. Hence, this innovation aims to create a low-cost, portable UV exposure system that works well in educational settings by utilizing LED illumination technology. In order to manage time, relay, and LCD, these UV LED exposures were built using a combined LED circuit with a controller board. With a dimension of 120 mm by 190 mm and 3 mm LEDs, the UV LED circuit generates a wavelength of 400 to 405 mm for the UV exposure system. Due to its powerful and flexible design capabilities, LED lighting may be integrated in any shape to create highly efficient illumination. The testing result shows that LED lights have higher application efficiency due to its ability to concentrate light in one area. Therefore, well-designed LED illumination systems may deliver light to the intended spot more effectively. They also brighten up instantly when powered on and can be turned on and off repeatedly. This research has highlighted the advantages of LEDs for infrastructure projects, such as exposure systems, which could be further developed for future technology.

Groupoidal realizability for intensional type theory

Abstract We develop realizability models of intensional type theory, based on groupoids, wherein realizers themselves carry non-trivial (non-discrete) homotopical structure. In the spirit of realizability, this is intended to formalize a homotopical BHK interpretation, whereby evidence for an identification is a path. Specifically, we study partitioned groupoidal assemblies. Categories of such are parameterized by “realizer categories” (instead of the usual partial combinatory algebras) that come equipped with an interval qua internal cogroupoid. The interval furnishes a notion of homotopy as well as a fundamental groupoid construction. Objects in a base groupoid are realized by points in the fundamental groupoid of some object from the realizer category; isomorphisms in the base groupoid are realized by paths in said fundamental groupoid. The main result is that, under mild conditions on the realizer category, the ensuing category of partitioned groupoidal assemblies models intensional (1-truncated) type theory without function extensionality. Moreover, when the underlying realizer category is “untyped,” there exists an impredicative universe of 1-types (the modest fibrations). This is a groupoidal analog of the traditional situation.

EnR: extend and reduce methodology to enable formal verification of truncated adders

Abstract Truncated adders are widely used in applications where using lower bit-width is enough to generate the desired outputs. Truncated adders give benefits in area, power, and delay as compared to their non-truncated counterparts. While prior works deal with the formal verification of n-bit adders, there is no prior work dealing with the formal verification of unverified m-bit truncated adders using verified n-bit adder designs, where m < ${< } $ n. In this work, we propose a methodology that enables the verification for any truncated adder designs, irrespective of the architecture, called Extend and Reduce (EnR). EnR uses a three-step methodology to formally verify the truncated adders, which are considered as Design Under Verification (DUV). Firstly, it extends the bit-width of the DUV (truncated adder) to match with the nearest higher 2 n -bit adder, called an Extended Truncated Adder (ETA). Secondly, it reduces off-the-shelf formally verified golden reference adder design by forcing 0’s at the input bits to match it to the extended DUV design and re-synthesizing it to generate a Reduced Golden Adder (RGA). Lastly, a combinational equivalence check is then performed between the ETA and the RGA for formal verification. If the truncated adder is correct, the ETA and RGA are equivalent and vice versa. We evaluate a number and variety of adder designs to show the efficacy of the EnR methodology. We performed the formal verification using Binary Decision Diagrams (BDDs) and And-Inverter Graphs (AIGs). Lastly, we show the scalability of EnR methodology using adders up to a bit-width of 512 bits. ACM CCS Hardware → Arithmetic and datapath circuits; Combinational circuits; Equivalence checking; Functional verification; Electronic design automation.

Effective correction of manifestations of vaginal microflora disorders

Pathological vaginal discharge is one of the main reasons for visiting gynecologists. Despite the abundance of drugs, not all are compliant and quickly effective for pronounced itching and swelling in the introitus area. One of the most common causes of pathological leukemia is vaginal infections, which are represented by three main clinical forms: bacterial vaginosis (BV) – up to 50% of all cases; vulvovaginal candidiasis (CVV) – 20–25% and trichomonas vaginitis (TV) – 15–20% of cases, respectively. In this regard, retrospective analysis shows that patients with BV, KV, TV most often actively turn to a gynecologist or venereologist However, the fact that the cause of pathological whites in more than 30% of cases can be a mixed infection creates problems in treatment with the use of monodrugs (many relapses up to 40% or more). Therefore, for their treatment, it is considered rational to use the concept of the etiotropic approach, based on the local effect of combined vaginal drugs. The role of a combined topical drug, including those with a rapid anesthetic effect, was evaluated. Neo-Penotran Forte L is a logical combination of antibacterial agents and a local anesthetic used to treat manifest forms of vaginal infections and provide rapid relief of intolerable symptoms.

Hamming distances of unsaturated orthogonal arrays

Orthogonal arrays (OAs) are applied in the statistical design of experiments, coding theory, cryptography, various types of software testing and quality control and have many connections to other combinatorial designs. The Hamming distances of OAs play a critical role in many areas such as algebraic combinatorics, quantum information theory, and wireless sensor networks. However, the calculation method of Hamming distances is difficult, especially for mixed orthogonal arrays (MOAs), since they rely on constructions or structures of OAs in many cases. In this article, by using the number of coincidences, we find some OAs with high strength and MOAs with strength 2 and 3, whose Hamming distances do not depend on their structures. We also calculate Hamming distances of a series of unsaturated asymmetrical OAs via their construction methods such as deleting columns, the expansive replacement method, and difference schemes.

Design and Implementation of a 7-Person Voting Device based on Quartus

As the complexity of digital system design continues to increase, efficient and precise decision support systems have become increasingly important. This paper presents the design and implementation of a 7-voter decision system based on Altera’s Quartus software. The voter is applied in the core decision-making process to ensure the accuracy and efficiency of decisions. The study begins by outlining the design principles of the 7-voter decision system, using a design philosophy that minimizes timing delays and optimizes hardware resource utilization. A complex majority voting logic circuit is implemented using high-level hardware description languages (VHDL/Verilog), ensuring the advanced nature and applicability of the voting circuit. In terms of the logical implementation of the voting circuit, the paper conducts an in-depth analysis of the optimization of combinational and sequential logic and standardizes the input and output to enhance the signal stability and the system’s resistance to interference. On the Quartus platform, the design process of the voting system is elaborated in detail, with careful consideration given to boundary conditions and hardware compatibility. The implementation of the voter has undergone rigorous simulation and testing. Strict parameter setting for simulations and waveform analysis confirm the correctness of the circuit, and fault simulation tests further confirm its reliability. Performance indicators such as response time and percentage of resource utilization have been quantitatively analyzed and meet the design objectives set beforehand. Overall, this research not only realizes a highperformance 7-voter decision system but also provides an effective case study for applications on the high-performance Quartus design platform. Future research can build on the current work to further optimize algorithms and hardware, explore the potential for the application of the voter in a broader range of fields, and adapt to the new features of the Quartus platform to achieve more powerful decision support functions.

RISC-V Leads the Future: Evolution and Outlook of CPU Architecture

This essay mainly talked the development of CPU and some instruction set architecture based on RISCV. CPU is known as the Central Processing Unit, the main appliment is RISCV, Also the ARM architecture is characterized by a focus on the balance between low power consumption and high performance. Then X86, its significant advantage is its complex instruction set and excellent performance, so it can handle complex computational tasks. We also explore the Pipeline technology, it is a widely used parallel processing technology today. The design principle is to divide complex, multilevel combinational logic circuits into multiple levels. Then, we find some experiment data to explore our conclusion. We find that each has its own advantages and is better suited to different scenarios. In terms of performance, x86 offers superior capabilities but consumes more power, making it ideal for high-performance computing and server applications. ARM, on the other hand, excels in power efficiency and finds its primary use in mobile devices and embedded systems. RISC-V, known for its flexibility, allows for a balance between performance and power consumption based on specific requirements, making it suitable for highly customizable applications, IoT devices, and emerging high-performance computing markets. The advantages of each architecture in different fields depend on the specific application environment and demands placed on them.

Implementation of a novel secured authentication protocol for cyber security applications

Robust verification protocols are crucial for maintaining the security and reliability of sensitive information due to the increasing complexity of cyber-attacks. This paper introduces a novel 5G Secure Handover Protocol aimed at addressing security and effectiveness issues encountered in existing systems. The proposed protocol is robust against various attacks, including de-synchronization, replay, man-in-the-middle (MITM), denial of services (DoS), and jamming, ensures perfect forward key secrecy, safeguarding communication confidentiality. The proposed protocol utilizes a combination of spiking neural network and fuzzy logic (SNN-FL) techniques that must choose the goal cell as carefully as possible before initiating the transfer process. By combining fuzzy logic and spiking neural networks to reduce handover latency and thwart several types of cyberattacks, the proposed 5G Secure Handover Protocol improves security. Extensive simulations show its efficacy and emphasize its potential for safe communication in large-scale cybersecurity applications. The paper presents a novel secure authentication protocol that significantly reduces handover delays and improves efficiency. Simulations show its resilience against common security threats, protecting sensitive information and maintaining secure communication channels. The protocol, with low communication expenses, complex spatial, and latency for changeover verification, is ideal for large-scale cybersecurity applications, contributing to the development of secure digital authentication mechanisms.

Drain self-blocking ambipolar transistors for complementary circuit applications

The development of complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) based on two-dimensional (2D) materials offers an important opportunity to reduce static power and increase the integration density of integrated circuits. One promising approach to realize these CMOSFETs is to employ ambipolar 2D materials as channel materials with designed device structure to control the carrier transport properties for CMOSFET characteristics. However, these devices always suffer from complex multi-gate electrode structure, and hence face challenges in complicated inter-connection design and excessive voltage source requirement for circuit implementation. Here, we develop a three-terminal CMOSFET using ambipolar 2D material based on the drain electric field-induced carrier injection self-blocking mechanism. The designed drain electrode can effectively suppress carrier injection from the drain to the channel material, while the gate voltage can only regulate carrier injection in the source region. As a result, we can configure the device as either N-field-effect transistors (FET) or P-FET with a high current on/off ratio of over 105 by adjusting the three voltages (gate, source, and drain). Furthermore, we utilize these devices to demonstrate multifunctional wave modulator, low-static-power logic inverter (<5 pW), and combinational logic computing in the form of a compact complementary circuit. Our work would explore an efficient approach for implementing complementary circuits using 2D materials.

A framework to assess the effectiveness index (EI) of the Indian SMEs to integrate lean and sustainability through combined fuzzy logic and systems approach

PurposeTo become a sustainable lean manufacturing (LM) system, an organization must be first distinctly cognizant of the terms “lean” and “sustainability” as they relate to the state of affairs of their particular industry and business. Next, the organization must identify and acquire the necessary qualities it needs to become sustainable in lean philosophy and its practices in the organization. The LM paradigm has been a top priority for many businesses; thus, this article is based on actual research done in Indian small and medium scale organizations to see how widely it is understood and implemented.Design/methodology/approachA framework was developed based on literature review and academic research. A preliminary analysis of a small number of small and medium-sized enterprises (SMEs) that, conceptually, summarizes and demonstrates the concerted efforts that a company may undertake to increase its leanness. This conceptual model was employed to create a questionnaire that was administered to survey the SMEs of India. The information gathered through this questionnaire was analyzed using the model developed by the researchers. Then fuzzy logic and systems approach were used to find out the effectiveness index (EI) of the organization.FindingsThe EI for system leanness at different organizational levels within an organization is determined using fuzzy logic and systems approach for 48 SMEs in different clusters. The average EI of the system was found to be 0.336 on a scale of 0–1 which indicates that the current state of lean implementation and its sustainability is very low and poor in Indian SMEs. This article outlines the key model components and describes how they were applied to analyze the data gathered from an industry study.Research limitations/implicationsThe research aims to make lean continuously sustainable by surfacing and eliminating the wastes in the Indian SMEs whenever it appears rather than using it as a cleaning tool. The present study was focused on India’s southern industrial areas and it was difficult to gather the information around the country due to its diverse industrial culture and geography. Hence, more research and the comparative study of the same that takes into account the various regions of the nation’s industrial lean behavior can be conducted.Practical implicationsThe generalized sustainable lean framework analyzed using fuzzy logic and systems approach gives the current effectiveness of the leanness in SMEs of south India. This model can be effectively implemented in other areas of the nation to identify the scenario of lean and its sustainability and a final comprehensive model can be developed.Originality/valueThere is a dearth of comprehensive studies on the assessment of sustainability of the lean philosophy in Indian SMEs. With the help of combined fuzzy logic and systems approach, the model developed in this study evaluates the sustainability of the lean methodology using the EI used in SMEs by taking into account both the lean and sustainability factors as well as enablers like customer satisfaction, ethics, innovation and technology.

From Quasi-Symmetric to Schur Expansions with Applications to Symmetric Chain Decompositions and Plethysm

It is an important problem in algebraic combinatorics to deduce the Schur function expansion of a symmetric function whose expansion in terms of the fundamental quasisymmetric function is known. For example, formulas are known for the fundamental expansion of a Macdonald symmetric function and for the plethysm of two Schur functions, while the Schur expansions of these expressions are still elusive. Based on work of Egge, Loehr and Warrington, Garsia and Remmel provided a method to obtain the Schur expansion from the fundamental expansion by replacing each quasisymmetric function by a Schur function (not necessarily indexed by a partition) and using straightening rules to obtain the Schur expansion. Here we provide a new method that only involves the coefficients of the quasisymmetric functions indexed by partitions and the quasi-Kostka matrix. As an application, we identify the lexicographically largest term in the Schur expansion of the plethysm of two Schur functions. We provide the Schur expansion of $s_w[s_h](x,y)$ for $w=2,3,4$ using novel symmetric chain decompositions of Young's lattice for partitions in a $w\times h$ box. For $w=4$, this is the first known combinatorial expression for the coefficient of $s_{\lambda}$ in $s_{w}[s_{h}]$ for two-row partitions $\lambda$, and for $w=3$ the combinatorial expression is new.